@W: BN137 :"f:\microsemi_prj\sf2_standby_tutorial\libero_project\sf2_standby\hdl\standby_control.vhd":119:0:119:5|Found combinational loop during mapping at net Standby_Control_0.PLL_PowerDown
@W: MT530 :"f:\microsemi_prj\sf2_standby_tutorial\libero_project\sf2_standby\hdl\cnt_up.vhd":42:6:42:7|Found inferred clock SF2_Standby_FCCC_0_FCCC|GL0_net_inferred_clock which controls 39591 sequential elements including Fabric_Logic_0.U1_1.F\.0\.F0\.U1.CNTVAL[7:0]. This clock has no specified timing constraint which may adversely impact design performance. 
