Project Settings Project Name PCIe_HPDMA_SMCFIC_top_syn Implementation Name synthesis Top Module PCIe_HPDMA_SMCFIC_top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 44 96 0 - 0m:01s - 3/10/2016 5:58:09 PM (premap) Complete 25 5 0 0m:00s 0m:00s 142MB 3/10/2016 5:58:11 PM (fpga_mapper) Complete 19 30 0 0m:02s 0m:02s 142MB 3/10/2016 5:58:14 PM Multi-srs Generator Complete 0m:01s 3/10/2016 5:58:10 PM Area Summary Carry Cells 38 Sequential Cells 548 DSP Blocks (MACC) (dsp_used) 0 I/O Cells 15 Global Clock Buffers 9 LUTs (total_luts) 286 Timing Summary Clock Name Req Freq Est Freq Slack PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net 75.0 MHz 156.1 MHz 6.922 PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz 278.9 MHz 6.414 PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 431.2 MHz 7.681 PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 123.0 MHz 0.936 Optimizations Summary Combined Clock Conversion 3 / 1