• PCIe_HPDMA_SMCFIC_top_syn (synthesis)
  • Synthesis -
    • Compiler Report
    • Compiler Constraint Applicator
    • Pre-mapping Report
      • Clock Summary
    • Mapper Report
      • Clock Conversion
      • Timing Report
        • Performance Summary
        • Clock Relationships
        • Interface Information
        • Detailed Report for Clocks
          • Clock: PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net
            • Starting Points with Worst Slack
            • Ending Points with Worst Slack
            • Worst Path Information
          • Clock: PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock
            • Starting Points with Worst Slack
            • Ending Points with Worst Slack
            • Worst Path Information
          • Clock: PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock
            • Starting Points with Worst Slack
            • Ending Points with Worst Slack
            • Worst Path Information
          • Clock: PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock
            • Starting Points with Worst Slack
            • Ending Points with Worst Slack
            • Worst Path Information
      • Resource Utilization
    • Constraint Checker Report (21:09 08-Dec)
    • Hierarchical Area Report(PCIe_HPDMA_SMCFIC_top) (17:58 10-Mar)
  • Session Log (17:48 22-Sep)