#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\Libero_SoC_11_7\Synplify #OS: Windows 7 6.1 #Hostname: W764-BALA #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\Libero_SoC_11_7\Synplify\lib\generic\smartfusion2.v" @I::"D:\Libero_SoC_11_7\Synplify\lib\vlog\hypermods.v" @I::"D:\Libero_SoC_11_7\Synplify\lib\vlog\umr_capim.v" @I::"D:\Libero_SoC_11_7\Synplify\lib\vlog\scemi_objects.v" @I::"D:\Libero_SoC_11_7\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AHB_IF.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_MASTER_TO_SLAVE1.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\Debounce.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\CCC_0\PCIe_HPDMA_SMCFIC_CCC_0_FCCC.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_MSS\PCIe_HPDMA_SMCFIC_MSS_syn.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_MSS\PCIe_HPDMA_SMCFIC_MSS.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\PCIe_HPDMA_SMCFIC.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_top\SERDES_IF_0\PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF_syn.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_top\SERDES_IF_0\PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF.v" @I::"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_top\PCIe_HPDMA_SMCFIC_top.v" Verilog syntax check successful! File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\CCC_0\PCIe_HPDMA_SMCFIC_CCC_0_FCCC.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\SgCore\OSC\1.0.105\osc_comps.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\PCIe_HPDMA_SMCFIC.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_top\SERDES_IF_0\PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF_syn.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_top\SERDES_IF_0\PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF.v changed - recompiling File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_top\PCIe_HPDMA_SMCFIC_top.v changed - recompiling Selecting top level module PCIe_HPDMA_SMCFIC_top @N:CG364 : AHB_IF.v(21) | Synthesizing module AHB_IF Idle_1=3'b000 Write_FIC_0=3'b001 Write_FIC_1=3'b010 Write_FIC_2=3'b011 Read_FIC_0=3'b100 Read_FIC_1=3'b101 Read_FIC_2=3'b110 Data_size=5'b00000 Generated name = AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1 @W:CG360 : AHB_IF.v(62) | No assignment to wire HSIZE_int @A:CL282 : AHB_IF.v(85) | Feedback mux created for signal HWDATA_int[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : AHB_IF.v(85) | Feedback mux created for signal HADDR_int[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : AHB_IF.v(85) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : AHB_IF.v(85) | Pruning register bit 0 of HTRANS[1:0] @N:CG364 : AXI_MASTER_TO_SLAVE1.v(21) | Synthesizing module AXI_MASTER_TO_SLAVE1 ID_BITS=32'b00000000000000000000000000000100 ADDR_WIDTH=32'b00000000000000000000000000100000 Generated name = AXI_MASTER_TO_SLAVE1_4s_32s @N:CG364 : AXI_Slave.v(22) | Synthesizing module AXI_Slave @A:CL282 : AXI_Slave.v(174) | Feedback mux created for signal RID[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : AXI_Slave.v(174) | Feedback mux created for signal RDATA[63:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : AXI_Slave.v(82) | Feedback mux created for signal DATAIN[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : AXI_Slave.v(82) | Feedback mux created for signal BID[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[32] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[33] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[34] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[35] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[36] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[37] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[38] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[39] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[40] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[41] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[42] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[43] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[44] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[45] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[46] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[47] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[48] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[49] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[50] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[51] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[52] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[53] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[54] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[55] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[56] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[57] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[58] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[59] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[60] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[61] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[62] is always 0, optimizing ... @W:CL189 : AXI_Slave.v(174) | Register bit RDATA[63] is always 0, optimizing ... @W:CL279 : AXI_Slave.v(174) | Pruning register bits 63 to 32 of RDATA[63:0] @N:CG364 : Debounce.v(20) | Synthesizing module DEBOUNCE @N:CG179 : Debounce.v(81) | Removing redundant assignment @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : PCIe_HPDMA_SMCFIC_CCC_0_FCCC.v(5) | Synthesizing module PCIe_HPDMA_SMCFIC_CCC_0_FCCC @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z2 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z3 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v(5) | Synthesizing module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC @N:CG364 : PCIe_HPDMA_SMCFIC_MSS_syn.v(5) | Synthesizing module MSS_120 @N:CG364 : PCIe_HPDMA_SMCFIC_MSS.v(9) | Synthesizing module PCIe_HPDMA_SMCFIC_MSS @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : PCIe_HPDMA_SMCFIC.v(9) | Synthesizing module PCIe_HPDMA_SMCFIC @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF @N:CG364 : PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_120_0 @N:CG364 : PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF @N:CG364 : PCIe_HPDMA_SMCFIC_top.v(9) | Synthesizing module PCIe_HPDMA_SMCFIC_top @W:CL247 : PCIe_HPDMA_SMCFIC_MSS.v(93) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL157 : PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : AXI_Slave.v(174) | Trying to extract state machine for register rstate Extracted state machine for register rstate State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : AXI_Slave.v(82) | Trying to extract state machine for register wstate Extracted state machine for register wstate State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : AXI_Slave.v(38) | Input port bits 63 to 32 of WDATA[63:0] are unused @W:CL159 : AXI_Slave.v(29) | Input AWLEN is unused @W:CL159 : AXI_Slave.v(30) | Input AWSIZE is unused @W:CL159 : AXI_Slave.v(31) | Input AWBURST is unused @W:CL159 : AXI_Slave.v(32) | Input AWLOCK is unused @W:CL159 : AXI_Slave.v(33) | Input AWCACHE is unused @W:CL159 : AXI_Slave.v(34) | Input AWPROT is unused @W:CL159 : AXI_Slave.v(37) | Input WID is unused @W:CL159 : AXI_Slave.v(39) | Input WSTRB is unused @W:CL159 : AXI_Slave.v(49) | Input ARLEN is unused @W:CL159 : AXI_Slave.v(50) | Input ARSIZE is unused @W:CL159 : AXI_Slave.v(51) | Input ARBURST is unused @W:CL159 : AXI_Slave.v(52) | Input ARLOCK is unused @W:CL159 : AXI_Slave.v(53) | Input ARCACHE is unused @W:CL159 : AXI_Slave.v(54) | Input ARPROT is unused @W:CL159 : AXI_MASTER_TO_SLAVE1.v(146) | Input MM_AWBURST is unused @W:CL159 : AXI_MASTER_TO_SLAVE1.v(166) | Input MM_ARBURST is unused @N:CL201 : AHB_IF.v(85) | Trying to extract state machine for register ahb_fsm_current_state Extracted state machine for register ahb_fsm_current_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 80MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 10 17:58:08 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 10 17:58:09 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 10 17:58:09 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\synwork\PCIe_HPDMA_SMCFIC_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 10 17:58:10 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\PCIe_HPDMA_SMCFIC_top_syn.fdc Linked File: PCIe_HPDMA_SMCFIC_top_scck.rpt Printing clock summary report in "D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\PCIe_HPDMA_SMCFIC_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB) @W:BN132 : axi_slave.v(174) | Removing sequential instance AXI_Slave_0.RVALID, because it is equivalent to instance AXI_Slave_0.RLAST @W:BN132 : coreresetp.v(1089) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.FDDR_CORE_RESET_N_int @N:BN362 : coreconfigp.v(461) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z3(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=236 set on top level netlist PCIe_HPDMA_SMCFIC_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group --------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net 75.0 MHz 13.330 declared default_clkgroup PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ================================================================================================================================= @W:MT530 : coreconfigp.v(447) | Found inferred clock PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1485) | Found inferred clock PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 30 sequential elements including PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp_pcie_hotreset.v(179) | Found inferred clock PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock which controls 37 sequential elements including PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\PCIe_HPDMA_SMCFIC_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 142MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Mar 10 17:58:11 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) @W:MO111 : pcie_hpdma_smcfic_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_smcfic_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_smcfic_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) @W:MO111 : pcie_hpdma_smcfic_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) @W:MO171 : coreresetp.v(695) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:BN132 : coreresetp.v(912) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(884) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif2_areset_n_rcosc, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc @W:BN132 : coreresetp.v(912) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif3_areset_n_rcosc, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc @W:BN132 : coreresetp.v(856) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc @W:BN132 : coreresetp.v(1549) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif2_core, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif1_core @W:BN132 : coreresetp.v(1581) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif3_core, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif1_core @W:BN132 : coreresetp.v(1517) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif1_core, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.ddr_settled @W:BN132 : coreresetp.v(1646) | Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif3_core_q1, because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif2_core_q1 Available hyper_sources - for debug and ip models None Found @N:MT480 : pcie_hpdma_smcfic_top_syn.fdc(18) | Assigning clock "PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net" to command: create_clock {n:PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net} -period {13.33} -waveform {0 6.66} -add Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) Encoding state machine ahb_fsm_current_state[6:0] (view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine rstate[3:0] (view:work.AXI_Slave(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : axi_slave.v(174) | No possible illegal states for state machine rstate[3:0],safe FSM implementation is disabled Encoding state machine wstate[3:0] (view:work.AXI_Slave(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : axi_slave.v(82) | No possible illegal states for state machine wstate[3:0],safe FSM implementation is disabled @N: : debounce.v(53) | Found counter in view:work.DEBOUNCE(verilog) inst q_reg[15:0] Encoding state machine state[2:0] (view:work.CoreConfigP_Z2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z3(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z3(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1170) | No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled @N: : coreresetp.v(1485) | Found counter in view:work.CoreResetP_Z3(verilog) inst count_sdif0[12:0] Encoding state machine state[3:0] (view:work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | No possible illegal states for state machine state[3:0],safe FSM implementation is disabled @N: : coreresetp_pcie_hotreset.v(227) | Found counter in view:work.coreresetp_pcie_hotreset(verilog) inst count[6:0] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 0.67ns 297 / 548 2 0h:00m:01s 0.67ns 294 / 548 @N:FP130 : | Promoting Net PCIe_HPDMA_SMCFIC_0_MSS_READY on CLKINT I_600 @N:FP130 : | Promoting Net PCIe_HPDMA_SMCFIC_0_INIT_APB_S_PRESET_N on CLKINT I_601 @N:FP130 : | Promoting Net PCIe_HPDMA_SMCFIC_0_INIT_APB_S_PCLK on CLKINT I_602 @N:FP130 : | Promoting Net PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_clk_ltssm on CLKINT I_603 @N:FP130 : | Promoting Net PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_604 @N:FP130 : | Promoting Net PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_605 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 441 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 110 clock pin(s) of sequential element(s) 0 instances converted, 110 sequential instances remain driven by gated/generated clocks ====================================================================== Non-Gated/Non-Generated Clocks ====================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_INST CLKINT 385 PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST ClockId0003 PCIe_HPDMA_SMCFIC_0.CCC_0.GL3_INST CLKINT 35 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2.sdif0_phr.count[6] ClockId0004 PCIe_HPDMA_SMCFIC_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 21 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[12] ============================================================================================================================================================================ ==================================================================================================== Gated/Generated Clocks ===================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST MSS_120 110 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.SDIF_RELEASED_q2 No gated clock conversion method for cell cell:ACG4.SLE ================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 142MB) Writing Analyst data base D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\synwork\PCIe_HPDMA_SMCFIC_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 142MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 138MB peak: 142MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 138MB peak: 142MB) @W:MT246 : pcie_hpdma_smcfic_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_SMCFIC_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_SMCFIC_0.CCC_0.GL3_net" Found clock PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net with period 13.33ns @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Mar 10 17:58:14 2016 # Top view: PCIe_HPDMA_SMCFIC_top Requested Frequency: 75.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\PCIe_HPDMA_SMCFIC_top_syn.fdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 0.936 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net 75.0 MHz 156.1 MHz 13.330 6.408 6.922 declared default_clkgroup PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock 100.0 MHz 278.9 MHz 10.000 3.586 6.414 inferred Inferred_clkgroup_2 PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 431.2 MHz 10.000 2.319 7.681 inferred Inferred_clkgroup_1 PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 123.0 MHz 10.000 8.128 0.936 inferred Inferred_clkgroup_0 ======================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net | 13.330 6.922 | No paths - | No paths - | No paths - PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 3.828 | No paths - | 5.000 2.990 | 5.000 0.936 PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net | Diff grp - | No paths - | No paths - | No paths - PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 10.000 7.681 | No paths - | No paths - | No paths - PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock | 10.000 6.414 | No paths - | No paths - | No paths - ========================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net MSS_120 F_FM0_READYOUT AHB_IF_0_BIF_1_HREADYOUT 2.997 6.922 PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net MSS_120 F_RID[0] AXI_MASTER_TO_SLAVE1_1_BIF_1_AWID[0] 4.114 7.073 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[19] SERDES_IF_0_AXI_MASTER_ARADDR[19] 2.569 7.081 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[6] SERDES_IF_0_AXI_MASTER_ARADDR[6] 2.626 7.083 PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net MSS_120 F_ARREADY_HREADYOUT1 AXI_MASTER_TO_SLAVE1_1_BIF_1_AWVALID 4.132 7.112 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[18] SERDES_IF_0_AXI_MASTER_ARADDR[18] 2.563 7.146 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[12] SERDES_IF_0_AXI_MASTER_ARADDR[12] 2.656 7.153 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[26] SERDES_IF_0_AXI_MASTER_ARADDR[26] 2.572 7.160 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[8] SERDES_IF_0_AXI_MASTER_ARADDR[8] 2.523 7.220 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SERDESIF_120_0 M_ARADDR[31] SERDES_IF_0_AXI_MASTER_ARADDR[31] 2.565 7.232 =========================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- AHB_IF_0.HADDR[0] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[1] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[2] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[3] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[4] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[5] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[6] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[7] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[8] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 AHB_IF_0.HADDR[9] PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net SLE EN N_152_mux 13.037 6.922 ============================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 13.330 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 13.037 - Propagation time: 6.114 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 6.922 Number of logic level(s): 2 Starting point: PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: AHB_IF_0.HADDR[0] / EN The start point is clocked by PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net [rising] on pin CLK_BASE The end point is clocked by PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.MSS_ADLIB_INST MSS_120 F_FM0_READYOUT Out 2.997 2.997 - AHB_IF_0_BIF_1_HREADYOUT Net - - 0.990 - 13 AHB_IF_0.ahb_fsm_current_state_RNIH8OJ[5] CFG4 D In - 3.987 - AHB_IF_0.ahb_fsm_current_state_RNIH8OJ[5] CFG4 Y Out 0.284 4.271 - N_148_mux Net - - 0.548 - 2 AHB_IF_0.ahb_fsm_current_state_RNI9Q7L[1] CFG4 D In - 4.819 - AHB_IF_0.ahb_fsm_current_state_RNI9Q7L[1] CFG4 Y Out 0.250 5.069 - N_152_mux Net - - 1.045 - 32 AHB_IF_0.HADDR[0] SLE EN In - 6.114 - ====================================================================================================================================== Total path delay (propagation time + setup) of 6.408 is 3.824(59.7%) logic and 2.583(40.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count 0.094 6.414 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[0] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[0] 0.094 6.569 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[4] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[4] 0.076 6.641 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[3] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[3] 0.076 6.645 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[5] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[5] 0.094 6.677 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[6] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[6] 0.094 6.744 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[1] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[1] 0.094 7.342 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[2] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q count[2] 0.076 7.416 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[1] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q ltssm_q2[1] 0.094 7.422 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.ltssm_q2[0] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE Q ltssm_q2[0] 0.094 7.465 ============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D state_RNO[0] 9.778 6.414 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.hot_reset_n PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE EN N_156_i_0 9.707 6.674 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[1] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D N_8 9.778 7.169 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D LTSSM_DetectQuiet_3 9.778 7.422 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_Disabled PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D LTSSM_Disabled_3 9.778 7.422 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_HotReset PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D LTSSM_HotReset_3 9.778 7.422 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[6] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D count_s[6] 9.778 7.541 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[5] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D count_s[5] 9.778 7.555 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[4] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D count_s[4] 9.778 7.569 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count[3] PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock SLE D count_s[3] 9.778 7.583 ============================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 3.364 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 6.414 Number of logic level(s): 4 Starting point: PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] / Q Ending point: PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] / D The start point is clocked by PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock [rising] on pin CLK The end point is clocked by PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] SLE Q Out 0.094 0.094 - count Net - - 0.848 - 12 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNI522H[3] CFG2 A In - 0.943 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNI522H[3] CFG2 Y Out 0.076 1.018 - m6_3 Net - - 0.483 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNILJ821[1] CFG4 D In - 1.502 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.count_RNILJ821[1] CFG4 Y Out 0.250 1.752 - N_16_mux Net - - 0.590 - 3 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet_entry_p_RNIN6BV1 CFG4 B In - 2.342 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.LTSSM_DetectQuiet_entry_p_RNIN6BV1 CFG4 Y Out 0.143 2.484 - N_156_i_0 Net - - 0.548 - 2 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state_RNO[0] CFG4 C In - 3.032 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state_RNO[0] CFG4 Y Out 0.194 3.226 - state_RNO[0] Net - - 0.138 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[0] SLE D In - 3.364 - ===================================================================================================================================================== Total path delay (propagation time + setup) of 3.586 is 0.979(27.3%) logic and 2.607(72.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[0] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[0] 0.094 7.681 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[1] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[1] 0.094 7.746 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[2] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[2] 0.094 7.760 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[3] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[3] 0.094 7.774 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[4] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[4] 0.094 7.789 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[5] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[5] 0.094 7.803 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[6] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[6] 0.094 7.817 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[7] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[7] 0.094 7.831 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[8] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[8] 0.094 7.845 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[9] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_sdif0[9] 0.094 7.858 ============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[12] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[12] 9.778 7.681 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[11] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[11] 9.778 7.695 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[10] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[10] 9.778 7.709 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[9] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[9] 9.778 7.723 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[8] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[8] 9.778 7.738 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[7] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[7] 9.778 7.752 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[6] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[6] 9.778 7.766 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[5] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[5] 9.778 7.780 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[4] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[4] 9.778 7.795 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[3] PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_sdif0_s[3] 9.778 7.809 =================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.097 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.681 Number of logic level(s): 13 Starting point: PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[0] / Q Ending point: PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[12] / D The start point is clocked by PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK The end point is clocked by PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.094 0.094 - count_sdif0[0] Net - - 0.637 - 3 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_s_598 ARI1 B In - 0.732 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_s_598 ARI1 FCO Out 0.174 0.906 - count_sdif0_s_598_FCO Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[1] ARI1 FCI In - 0.906 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[1] ARI1 FCO Out 0.014 0.920 - count_sdif0_cry[1] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[2] ARI1 FCI In - 0.920 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[2] ARI1 FCO Out 0.014 0.935 - count_sdif0_cry[2] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[3] ARI1 FCI In - 0.935 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[3] ARI1 FCO Out 0.014 0.949 - count_sdif0_cry[3] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[4] ARI1 FCI In - 0.949 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[4] ARI1 FCO Out 0.014 0.963 - count_sdif0_cry[4] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[5] ARI1 FCI In - 0.963 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[5] ARI1 FCO Out 0.014 0.977 - count_sdif0_cry[5] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[6] ARI1 FCI In - 0.977 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[6] ARI1 FCO Out 0.014 0.991 - count_sdif0_cry[6] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[7] ARI1 FCI In - 0.991 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[7] ARI1 FCO Out 0.014 1.006 - count_sdif0_cry[7] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[8] ARI1 FCI In - 1.006 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[8] ARI1 FCO Out 0.014 1.020 - count_sdif0_cry[8] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[9] ARI1 FCI In - 1.020 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[9] ARI1 FCO Out 0.014 1.034 - count_sdif0_cry[9] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[10] ARI1 FCI In - 1.034 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[10] ARI1 FCO Out 0.014 1.048 - count_sdif0_cry[10] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[11] ARI1 FCI In - 1.048 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_cry[11] ARI1 FCO Out 0.014 1.062 - count_sdif0_cry[11] Net - - 0.000 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_s[12] ARI1 FCI In - 1.062 - PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0_s[12] ARI1 S Out 0.063 1.126 - count_sdif0_s[12] Net - - 0.971 - 1 PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[12] SLE D In - 2.097 - =================================================================================================================== Total path delay (propagation time + setup) of 2.319 is 0.710(30.6%) logic and 1.609(69.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.psel PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.094 0.936 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.state[1] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.076 2.990 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.SDIF0_PENABLE PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PENABLE 0.094 3.385 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.state[0] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[0] 0.076 3.745 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.paddr[14] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PADDR[14] 0.094 3.765 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_120_0 APB_PRDATA[0] PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PRDATA[0] 4.114 3.828 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.paddr[15] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PADDR[15] 0.076 3.859 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_120_0 APB_PRDATA[2] PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PRDATA[2] 4.098 4.335 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_120_0 APB_PRDATA[5] PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PRDATA[5] 4.056 4.377 SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_120_0 APB_PRDATA[6] PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PRDATA[6] 4.003 4.430 ===================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_120_0 APB_PSEL PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PSELx 2.950 0.936 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 4.778 1.807 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[0] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[1] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[2] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[3] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[4] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[5] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[6] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.soft_reset_reg[7] PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 1.908 ===================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 2.050 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.950 - Propagation time: 2.014 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.936 Number of logic level(s): 1 Starting point: PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.708 - 5 PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.R_SDIF0_PSEL_1_0_a2 CFG3 B In - 0.802 - PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.R_SDIF0_PSEL_1_0_a2 CFG3 Y Out 0.143 0.945 - PCIe_HPDMA_SMCFIC_0_SDIF0_INIT_APB_PSELx Net - - 1.069 - 37 SERDES_IF_0.SERDESIF_INST SERDESIF_120_0 APB_PSEL In - 2.014 - ================================================================================================================================== Total path delay (propagation time + setup) of 4.064 is 2.287(56.3%) logic and 1.777(43.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 142MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 142MB) --------------------------------------- Resource Usage Report for PCIe_HPDMA_SMCFIC_top Mapping to part: m2s150tfc1152-1 Cell usage: CCC 1 use CLKINT 9 uses MSS_120 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_120_0 1 use SYSRESET 1 use CFG1 10 uses CFG2 56 uses CFG3 69 uses CFG4 113 uses Carry primitives used for arithmetic functions: ARI1 38 uses Sequential Cells: SLE 548 uses DSP Blocks: 0 I/O ports: 33 I/O primitives: 15 INBUF 6 uses INBUF_DIFF 1 use OUTBUF 8 uses Global Clock Buffers: 9 Total LUTs: 286 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 548 + 0 + 0 + 0 = 548; Total number of LUTs after P&R: 286 + 0 + 0 + 0 = 286; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 52MB peak: 142MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Thu Mar 10 17:58:14 2016 ###########################################################]