@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\hdl\axi_slave.v":174:0:174:5|Removing sequential instance AXI_Slave_0.RVALID,  because it is equivalent to instance AXI_Slave_0.RLAST
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Found inferred clock PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including PCIe_HPDMA_SMCFIC_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Found inferred clock PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 30 sequential elements including PCIe_HPDMA_SMCFIC_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|Found inferred clock PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock which controls 37 sequential elements including PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.state[3:0]. This clock has no specified timing constraint which may adversely impact design performance. 
