@W: MO111 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\work\pcie_hpdma_smcfic\fabosc_0\pcie_hpdma_smcfic_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) 
@W: MO111 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\work\pcie_hpdma_smcfic\fabosc_0\pcie_hpdma_smcfic_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) 
@W: MO111 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\work\pcie_hpdma_smcfic\fabosc_0\pcie_hpdma_smcfic_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) 
@W: MO111 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\work\pcie_hpdma_smcfic\fabosc_0\pcie_hpdma_smcfic_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIe_HPDMA_SMCFIC_FABOSC_0_OSC) 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_rcosc,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif1_areset_n_rcosc
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif2_core,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif1_core
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif3_core,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif1_core
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif1_core,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.ddr_settled
@W: BN132 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif3_core_q1,  because it is equivalent to instance PCIe_HPDMA_SMCFIC_0.CORERESETP_0.release_sdif2_core_q1
@W: MT246 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\work\pcie_hpdma_smcfic\ccc_0\pcie_hpdma_smcfic_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock PCIe_HPDMA_SMCFIC_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_SMCFIC_0.PCIe_HPDMA_SMCFIC_MSS_0.FIC_2_APB_M_PCLK"
@W: MT420 |Found inferred clock PCIe_HPDMA_SMCFIC_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_SMCFIC_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
@W: MT420 |Found inferred clock PCIe_HPDMA_SMCFIC_CCC_0_FCCC|GL3_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:PCIe_HPDMA_SMCFIC_0.CCC_0.GL3_net"
