@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MT480 :"d:/libero_11_7_publish/dg0535/pcie_hpdma_smc_fic/synthesis/pcie_hpdma_smcfic_top_syn.fdc":18:0:18:0|Assigning clock "PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net" to command: create_clock {n:PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net} -period {13.33} -waveform {0 6.66} -add 
@N: MO225 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\hdl\axi_slave.v":174:0:174:5|No possible illegal states for state machine rstate[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\hdl\axi_slave.v":82:0:82:5|No possible illegal states for state machine wstate[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\libero_11_7_publish\dg0535\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|No possible illegal states for state machine state[3:0],safe FSM implementation is disabled
@N: FP130 |Promoting Net PCIe_HPDMA_SMCFIC_0_MSS_READY on CLKINT  I_600 
@N: FP130 |Promoting Net PCIe_HPDMA_SMCFIC_0_INIT_APB_S_PRESET_N on CLKINT  I_601 
@N: FP130 |Promoting Net PCIe_HPDMA_SMCFIC_0_INIT_APB_S_PCLK on CLKINT  I_602 
@N: FP130 |Promoting Net PCIe_HPDMA_SMCFIC_0.CORERESETP_0.genblk2\.sdif0_phr.reset_n_clk_ltssm on CLKINT  I_603 
@N: FP130 |Promoting Net PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_604 
@N: FP130 |Promoting Net PCIe_HPDMA_SMCFIC_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT  I_605 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
