@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MT480 :"d:/smcfic/150100/pcie_hpdma_smc_fic/synthesis/pcie_hpdma_smcfic_top_syn.fdc":18:0:18:0|Assigning clock "PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net" to command: create_clock {n:PCIe_HPDMA_SMCFIC_0.CCC_0.GL0_net} -period {5} -waveform {0 2.5} -add 
@N: BN362 :"d:\smcfic\150100\pcie_hpdma_smc_fic\hdl\axi_master_to_slave.v":225:4:225:9|Removing sequential instance AXI_MASTER_TO_SLAVE_0.AWSIZE[2] of view:PrimLib.dff(prim) in hierarchy view:work.PCIe_HPDMA_SMCFIC_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\smcfic\150100\pcie_hpdma_smc_fic\hdl\axi_master_to_slave.v":225:4:225:9|Removing sequential instance AXI_MASTER_TO_SLAVE_0.ARSIZE[2] of view:PrimLib.dff(prim) in hierarchy view:work.PCIe_HPDMA_SMCFIC_top(verilog) because there are no references to its outputs 
@N: MO225 :"d:\smcfic\150100\pcie_hpdma_smc_fic\hdl\axi_slave.v":174:0:174:5|No possible illegal states for state machine rstate[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\smcfic\150100\pcie_hpdma_smc_fic\hdl\axi_slave.v":82:0:82:5|No possible illegal states for state machine wstate[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\smcfic\150100\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled
@N: MO225 :"d:\smcfic\150100\pcie_hpdma_smc_fic\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|No possible illegal states for state machine state[3:0],safe FSM implementation is disabled
