@W: CG360 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AHB_IF.v":62:13:62:21|No assignment to wire HSIZE_int
@W: CL190 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AHB_IF.v":85:0:85:5|Optimizing register bit HTRANS[0] to a constant 0
@W: CL260 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AHB_IF.v":85:0:85:5|Pruning register bit 0 of HTRANS[1:0] 
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[32] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[33] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[34] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[35] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[36] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[37] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[38] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[39] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[40] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[41] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[42] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[43] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[44] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[45] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[46] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[47] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[48] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[49] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[50] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[51] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[52] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[53] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[54] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[55] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[56] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[57] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[58] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[59] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[60] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[61] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[62] is always 0, optimizing ...
@W: CL189 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Register bit RDATA[63] is always 0, optimizing ...
@W: CL279 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":174:0:174:5|Pruning register bits 63 to 32 of RDATA[63:0] 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning register count_ddr[13:0] 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_q1 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_rcosc 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register count_ddr_enable 
@W: CL190 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 
@W: CL169 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 
@W: CL247 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC_MSS\PCIe_HPDMA_SMCFIC_MSS.v":93:14:93:31|Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused
@W: CL157 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\work\PCIe_HPDMA_SMCFIC\FABOSC_0\PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL247 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bit 31 of prdata[31:0] is unused
@W: CL246 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bits 25 to 0 of prdata[31:0] are unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL246 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":38:32:38:36|Input port bits 63 to 32 of WDATA[63:0] are unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":29:32:29:36|Input AWLEN is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":30:32:30:37|Input AWSIZE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":31:32:31:38|Input AWBURST is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":32:32:32:37|Input AWLOCK is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":33:32:33:38|Input AWCACHE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":34:32:34:37|Input AWPROT is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":37:25:37:27|Input WID is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":39:32:39:36|Input WSTRB is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":49:32:49:36|Input ARLEN is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":50:32:50:37|Input ARSIZE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":51:32:51:38|Input ARBURST is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":52:32:52:37|Input ARLOCK is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":53:32:53:38|Input ARCACHE is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_Slave.v":54:32:54:37|Input ARPROT is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_MASTER_TO_SLAVE1.v":146:31:146:40|Input MM_AWBURST is unused
@W: CL159 :"D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\hdl\AXI_MASTER_TO_SLAVE1.v":166:31:166:40|Input MM_ARBURST is unused

