#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file D:\Libero_11_7_publish\dg0535\PCIe_HPDMA_SMC_FIC\synthesis\run_options.txt
#--  Written on Thu Mar 10 17:58:08 2016


#project files
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/hdl/AHB_IF.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/hdl/AXI_MASTER_TO_SLAVE1.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/hdl/AXI_Slave.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/hdl/Debounce.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC/CCC_0/PCIe_HPDMA_SMCFIC_CCC_0_FCCC.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC/FABOSC_0/PCIe_HPDMA_SMCFIC_FABOSC_0_OSC.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC_MSS/PCIe_HPDMA_SMCFIC_MSS_syn.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC_MSS/PCIe_HPDMA_SMCFIC_MSS.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC/PCIe_HPDMA_SMCFIC.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC_top/SERDES_IF_0/PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF_syn.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC_top/SERDES_IF_0/PCIe_HPDMA_SMCFIC_top_SERDES_IF_0_SERDES_IF.v"
add_file -verilog "D:/Libero_11_7_publish/dg0535/PCIe_HPDMA_SMC_FIC/component/work/PCIe_HPDMA_SMCFIC_top/PCIe_HPDMA_SMCFIC_top.v"
add_file -fpga_constraint "PCIe_HPDMA_SMCFIC_top_syn.fdc"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S150T
set_option -package FC1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "PCIe_HPDMA_SMCFIC_top"

# mapper_options
set_option -frequency 100.000000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./PCIe_HPDMA_SMCFIC_top.edn"
impl -active "synthesis"
