#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020
#install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
#OS: Windows 8 6.2
#Hostname: HYD-LT-I63442

# Thu Apr  8 02:03:45 2021

#Implementation: synthesis


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @

@N: :  | Running in 64-bit mode 
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v" (library work)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\hdl\AXI_IF.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\CCC_0\MDDR_Demo_sb_CCC_0_FCCC.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS_syn.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v" (library work)
@W:CG1337 : axi_interconnect_ntom.v(5291) | Net RREADY_M0IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5292) | Net RREADY_M0IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5293) | Net RREADY_M0IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5294) | Net RREADY_M0IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5295) | Net RREADY_M0IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5296) | Net RREADY_M0IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5297) | Net RREADY_M0IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5298) | Net RREADY_M0IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5299) | Net RREADY_M0IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5300) | Net RREADY_M0IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5301) | Net RREADY_M0IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5302) | Net RREADY_M0IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5303) | Net RREADY_M0IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5304) | Net RREADY_M0IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5305) | Net RREADY_M0IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5306) | Net RREADY_M0IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5307) | Net RREADY_M0IS16_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5309) | Net RREADY_M1IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5310) | Net RREADY_M1IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5311) | Net RREADY_M1IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5312) | Net RREADY_M1IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5313) | Net RREADY_M1IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5314) | Net RREADY_M1IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5315) | Net RREADY_M1IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5316) | Net RREADY_M1IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5317) | Net RREADY_M1IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5318) | Net RREADY_M1IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5319) | Net RREADY_M1IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5320) | Net RREADY_M1IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5321) | Net RREADY_M1IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5322) | Net RREADY_M1IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5323) | Net RREADY_M1IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5324) | Net RREADY_M1IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5325) | Net RREADY_M1IS16_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5327) | Net RREADY_M2IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5328) | Net RREADY_M2IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5329) | Net RREADY_M2IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5330) | Net RREADY_M2IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5331) | Net RREADY_M2IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5332) | Net RREADY_M2IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5333) | Net RREADY_M2IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5334) | Net RREADY_M2IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5335) | Net RREADY_M2IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5336) | Net RREADY_M2IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5337) | Net RREADY_M2IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5338) | Net RREADY_M2IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5339) | Net RREADY_M2IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5340) | Net RREADY_M2IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5341) | Net RREADY_M2IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5342) | Net RREADY_M2IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5343) | Net RREADY_M2IS16_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5345) | Net RREADY_M3IS0_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5346) | Net RREADY_M3IS1_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5347) | Net RREADY_M3IS2_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5348) | Net RREADY_M3IS3_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5349) | Net RREADY_M3IS4_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5350) | Net RREADY_M3IS5_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5351) | Net RREADY_M3IS6_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5352) | Net RREADY_M3IS7_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5353) | Net RREADY_M3IS8_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5354) | Net RREADY_M3IS9_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5355) | Net RREADY_M3IS10_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5356) | Net RREADY_M3IS11_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5357) | Net RREADY_M3IS12_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5358) | Net RREADY_M3IS13_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5359) | Net RREADY_M3IS14_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5360) | Net RREADY_M3IS15_gated is not declared.
@W:CG1337 : axi_interconnect_ntom.v(5361) | Net RREADY_M3IS16_gated is not declared.
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\MDDR_Demo_sb.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo\MDDR_Demo.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_top\MDDR_Demo_top.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\hdl\DATA_HANDLE_FSM.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\hdl\UART_IF_FSM.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\UART_IF\TPSRAM_0\UART_IF_TPSRAM_0_TPSRAM.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\UART_IF\UART_IF.v" (library work)
@I::"C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\top\top.v" (library work)
Verilog syntax check successful!
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\CCC_0\MDDR_Demo_sb_CCC_0_FCCC.v changed - recompiling
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v changed - recompiling
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS_syn.v changed - recompiling
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS.v changed - recompiling
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v changed - recompiling
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\component\work\MDDR_Demo_sb\MDDR_Demo_sb.v changed - recompiling
Selecting top level module top
@N:CG364 : AXI_IF.v(21) | Synthesizing module AXI_IF in library work.

	Idle_0=3'b000
	Idle_1=3'b001
	Write_0=3'b010
	Write_1=3'b011
	Read_0=3'b010
	Read_1=3'b011
	Read_2=3'b100
	Bresp_0=3'b100
	Write_2=3'b101
   Generated name = AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1
Running optimization stage 1 on AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1 .......
@A:CL282 : AXI_IF.v(222) | Feedback mux created for signal ARLEN[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : AXI_IF.v(95) | Feedback mux created for signal AWLEN[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : AXI_IF.v(95) | Feedback mux created for signal AWADDR[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL190 : AXI_IF.v(95) | Optimizing register bit AWBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : AXI_IF.v(95) | Optimizing register bit AWSIZE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : AXI_IF.v(222) | Optimizing register bit ARBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : AXI_IF.v(95) | Pruning register bit 1 of AWBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : AXI_IF.v(95) | Pruning register bit 2 of AWSIZE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : AXI_IF.v(222) | Pruning register bit 1 of ARBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work.
Running optimization stage 1 on VCC .......
@N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work.
Running optimization stage 1 on GND .......
@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work.
Running optimization stage 1 on CLKINT .......
@N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work.
Running optimization stage 1 on CCC .......
@N:CG364 : MDDR_Demo_sb_CCC_0_FCCC.v(5) | Synthesizing module MDDR_Demo_sb_CCC_0_FCCC in library work.
Running optimization stage 1 on MDDR_Demo_sb_CCC_0_FCCC .......
@N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
Running optimization stage 1 on COREAPB3_MUXPTOB3 .......
@N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB.

	APB_DWIDTH=6'b100000
	IADDR_OPTION=32'b00000000000000000000000000000000
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	MADDR_BITS=6'b010000
	UPR_NIBBLE_POSN=4'b0011
	FAMILY=32'b00000000000000000000000000010011
	SYNC_RESET=32'b00000000000000000000000000000000
	IADDR_NOTINUSE=32'b00000000000000000000000000000000
	IADDR_EXTERNAL=32'b00000000000000000000000000000001
	IADDR_SLOT0=32'b00000000000000000000000000000010
	IADDR_SLOT1=32'b00000000000000000000000000000011
	IADDR_SLOT2=32'b00000000000000000000000000000100
	IADDR_SLOT3=32'b00000000000000000000000000000101
	IADDR_SLOT4=32'b00000000000000000000000000000110
	IADDR_SLOT5=32'b00000000000000000000000000000111
	IADDR_SLOT6=32'b00000000000000000000000000001000
	IADDR_SLOT7=32'b00000000000000000000000000001001
	IADDR_SLOT8=32'b00000000000000000000000000001010
	IADDR_SLOT9=32'b00000000000000000000000000001011
	IADDR_SLOT10=32'b00000000000000000000000000001100
	IADDR_SLOT11=32'b00000000000000000000000000001101
	IADDR_SLOT12=32'b00000000000000000000000000001110
	IADDR_SLOT13=32'b00000000000000000000000000001111
	IADDR_SLOT14=32'b00000000000000000000000000010000
	IADDR_SLOT15=32'b00000000000000000000000000010001
	SL0=16'b0000000000000001
	SL1=16'b0000000000000000
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b0000000000000000
	SC=16'b0000000000000000
	SC_qual=16'b0000000000000000
   Generated name = CoreAPB3_Z2
@W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it.
Running optimization stage 1 on CoreAPB3_Z2 .......
@W:CG1283 : MDDR_Demo_sb.v(1081) | Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value
@N:CG364 : coreaxi.v(29) | Synthesizing module MDDR_Demo_sb_COREAXI_0_COREAXI in library work.

	FAMILY=32'b00000000000000000000000000010011
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	AWIDTH1=32'b00000000000000000000000000011000
	AWIDTH2=32'b00000000000000000000000000100000
	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SINGLE_MASTER=32'b00000000000000000000000000000001
	SINGLE_SLAVE=32'b00000000000000000000000000000000
	SINGLE_MASTER_SINGLE_SLAVE=32'b00000000000000000000000000000000
	COMB_REG=512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	SLAVE_0=17'b00000000000000001
	SLAVE_1=17'b00000000000000010
	SLAVE_2=17'b00000000000000100
	SLAVE_3=17'b00000000000001000
	SLAVE_4=17'b00000000000010000
	SLAVE_5=17'b00000000000100000
	SLAVE_6=17'b00000000001000000
	SLAVE_7=17'b00000000010000000
	SLAVE_8=17'b00000000100000000
	SLAVE_9=17'b00000001000000000
	SLAVE_A=17'b00000010000000000
	SLAVE_B=17'b00000100000000000
	SLAVE_C=17'b00001000000000000
	SLAVE_D=17'b00010000000000000
	SLAVE_E=17'b00100000000000000
	SLAVE_F=17'b01000000000000000
	SLAVE_N=17'b10000000000000000
	SYNC_RESET=32'b00000000000000000000000000000000
   Generated name = MDDR_Demo_sb_COREAXI_0_COREAXI_Z3
@N:CG364 : axi_feedthrough.v(30) | Synthesizing module axi_feedthrough in library work.

	AXI_AWIDTH=32'b00000000000000000000000000011000
	AXI_DWIDTH=32'b00000000000000000000000001000000
	M0_SLAVE0ENABLE=32'b00000000000000000000000000000001
	M0_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M0_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M1_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M2_SLAVE16ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE0ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE1ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE2ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE3ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE4ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE5ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE6ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE7ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE8ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE9ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE10ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE11ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE12ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE13ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE14ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE15ENABLE=32'b00000000000000000000000000000000
	M3_SLAVE16ENABLE=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000000100
	NUM_SLAVE_SLOT=32'b00000000000000000000000000010000
	NUM_MASTER_SLOT=32'b00000000000000000000000000000001
	MEMSPACE=32'b00000000000000000000000000000011
	HGS_CFG=32'b00000000000000000000000000000001
	ADDR_HGS_CFG=32'b00000000000000000000000000000001
	SC_0=32'b00000000000000000000000000000000
	SC_1=32'b00000000000000000000000000000000
	SC_2=32'b00000000000000000000000000000000
	SC_3=32'b00000000000000000000000000000000
	SC_4=32'b00000000000000000000000000000000
	SC_5=32'b00000000000000000000000000000000
	SC_6=32'b00000000000000000000000000000000
	SC_7=32'b00000000000000000000000000000000
	SC_8=32'b00000000000000000000000000000000
	SC_9=32'b00000000000000000000000000000000
	SC_10=32'b00000000000000000000000000000000
	SC_11=32'b00000000000000000000000000000000
	SC_12=32'b00000000000000000000000000000000
	SC_13=32'b00000000000000000000000000000000
	SC_14=32'b00000000000000000000000000000000
	SC_15=32'b00000000000000000000000000000000
	FEED_THROUGH=32'b00000000000000000000000000000001
	INP_REG_BUF=32'b00000000000000000000000000000001
	OUT_REG_BUF=32'b00000000000000000000000000000001
	WR_ACCEPTANCE=32'b00000000000000000000000000000100
	RD_ACCEPTANCE=32'b00000000000000000000000000000100
	BASE_ID_WIDTH=32'b00000000000000000000000000000010
	SYNC_RESET=32'b00000000000000000000000000000000
	AXI_STRBWIDTH=32'b00000000000000000000000000001000
   Generated name = axi_feedthrough_Z4
Running optimization stage 1 on axi_feedthrough_Z4 .......
@W:CG360 : coreaxi.v(1307) | Removing wire AWID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1308) | Removing wire AWADDR_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1309) | Removing wire AWLEN_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1310) | Removing wire AWSIZE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1311) | Removing wire AWBURST_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1312) | Removing wire AWLOCK_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1313) | Removing wire AWCACHE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1314) | Removing wire AWPROT_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1315) | Removing wire AWVALID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1318) | Removing wire WID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1319) | Removing wire WDATA_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1320) | Removing wire WSTRB_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1321) | Removing wire WLAST_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1322) | Removing wire WVALID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1328) | Removing wire BREADY_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1330) | Removing wire ARID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1331) | Removing wire ARADDR_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1332) | Removing wire ARLEN_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1333) | Removing wire ARSIZE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1334) | Removing wire ARBURST_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1335) | Removing wire ARLOCK_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1336) | Removing wire ARCACHE_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1337) | Removing wire ARPROT_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1338) | Removing wire ARVALID_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1346) | Removing wire RREADY_S1, as there is no assignment to it.
@W:CG360 : coreaxi.v(1350) | Removing wire AWID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1351) | Removing wire AWADDR_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1352) | Removing wire AWLEN_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1353) | Removing wire AWSIZE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1354) | Removing wire AWBURST_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1355) | Removing wire AWLOCK_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1356) | Removing wire AWCACHE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1357) | Removing wire AWPROT_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1358) | Removing wire AWVALID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1361) | Removing wire WID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1362) | Removing wire WDATA_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1363) | Removing wire WSTRB_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1364) | Removing wire WLAST_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1365) | Removing wire WVALID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1371) | Removing wire BREADY_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1373) | Removing wire ARID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1374) | Removing wire ARADDR_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1375) | Removing wire ARLEN_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1376) | Removing wire ARSIZE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1377) | Removing wire ARBURST_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1378) | Removing wire ARLOCK_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1379) | Removing wire ARCACHE_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1380) | Removing wire ARPROT_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1381) | Removing wire ARVALID_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1389) | Removing wire RREADY_S2, as there is no assignment to it.
@W:CG360 : coreaxi.v(1393) | Removing wire AWID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1394) | Removing wire AWADDR_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1395) | Removing wire AWLEN_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1396) | Removing wire AWSIZE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1397) | Removing wire AWBURST_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1398) | Removing wire AWLOCK_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1399) | Removing wire AWCACHE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1400) | Removing wire AWPROT_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1401) | Removing wire AWVALID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1404) | Removing wire WID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1405) | Removing wire WDATA_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1406) | Removing wire WSTRB_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1407) | Removing wire WLAST_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1408) | Removing wire WVALID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1414) | Removing wire BREADY_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1416) | Removing wire ARID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1417) | Removing wire ARADDR_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1418) | Removing wire ARLEN_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1419) | Removing wire ARSIZE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1420) | Removing wire ARBURST_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1421) | Removing wire ARLOCK_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1422) | Removing wire ARCACHE_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1423) | Removing wire ARPROT_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1424) | Removing wire ARVALID_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1432) | Removing wire RREADY_S3, as there is no assignment to it.
@W:CG360 : coreaxi.v(1436) | Removing wire AWID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1437) | Removing wire AWADDR_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1438) | Removing wire AWLEN_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1439) | Removing wire AWSIZE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1440) | Removing wire AWBURST_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1441) | Removing wire AWLOCK_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1442) | Removing wire AWCACHE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1443) | Removing wire AWPROT_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1444) | Removing wire AWVALID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1447) | Removing wire WID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1448) | Removing wire WDATA_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1449) | Removing wire WSTRB_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1450) | Removing wire WLAST_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1451) | Removing wire WVALID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1457) | Removing wire BREADY_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1459) | Removing wire ARID_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1460) | Removing wire ARADDR_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1461) | Removing wire ARLEN_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1462) | Removing wire ARSIZE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1463) | Removing wire ARBURST_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1464) | Removing wire ARLOCK_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1465) | Removing wire ARCACHE_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1466) | Removing wire ARPROT_S4, as there is no assignment to it.
@W:CG360 : coreaxi.v(1467) | Removing wire ARVALID_S4, as there is no assignment to it.

Only the first 100 messages of id 'CG360' are reported. To see all messages use 'report_messages -log C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synlog\top_compiler.srr -id CG360' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG360} -count unlimited' in the Tcl shell.
Running optimization stage 1 on MDDR_Demo_sb_COREAXI_0_COREAXI_Z3 .......
@W:CL318 : coreaxi.v(1144) | *Output AWREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1151) | *Output WREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1153) | *Output BID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1154) | *Output BRESP_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1155) | *Output BVALID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1167) | *Output ARREADY_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1169) | *Output RID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1170) | *Output RDATA_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1171) | *Output RRESP_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1172) | *Output RLAST_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1173) | *Output RVALID_M1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1187) | *Output AWREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1194) | *Output WREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1196) | *Output BID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1197) | *Output BRESP_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1198) | *Output BVALID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1210) | *Output ARREADY_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1212) | *Output RID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1213) | *Output RDATA_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1214) | *Output RRESP_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1215) | *Output RLAST_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1216) | *Output RVALID_M2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1230) | *Output AWREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1237) | *Output WREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1239) | *Output BID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1240) | *Output BRESP_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1241) | *Output BVALID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1253) | *Output ARREADY_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1255) | *Output RID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1256) | *Output RDATA_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1257) | *Output RRESP_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1258) | *Output RLAST_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1259) | *Output RVALID_M3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1307) | *Output AWID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1308) | *Output AWADDR_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1309) | *Output AWLEN_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1310) | *Output AWSIZE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1311) | *Output AWBURST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1312) | *Output AWLOCK_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1313) | *Output AWCACHE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1314) | *Output AWPROT_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1315) | *Output AWVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1318) | *Output WID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1319) | *Output WDATA_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1320) | *Output WSTRB_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1321) | *Output WLAST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1322) | *Output WVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1328) | *Output BREADY_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1330) | *Output ARID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1331) | *Output ARADDR_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1332) | *Output ARLEN_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1333) | *Output ARSIZE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1334) | *Output ARBURST_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1335) | *Output ARLOCK_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1336) | *Output ARCACHE_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1337) | *Output ARPROT_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1338) | *Output ARVALID_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1346) | *Output RREADY_S1 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1350) | *Output AWID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1351) | *Output AWADDR_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1352) | *Output AWLEN_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1353) | *Output AWSIZE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1354) | *Output AWBURST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1355) | *Output AWLOCK_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1356) | *Output AWCACHE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1357) | *Output AWPROT_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1358) | *Output AWVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1361) | *Output WID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1362) | *Output WDATA_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1363) | *Output WSTRB_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1364) | *Output WLAST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1365) | *Output WVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1371) | *Output BREADY_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1373) | *Output ARID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1374) | *Output ARADDR_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1375) | *Output ARLEN_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1376) | *Output ARSIZE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1377) | *Output ARBURST_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1378) | *Output ARLOCK_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1379) | *Output ARCACHE_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1380) | *Output ARPROT_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1381) | *Output ARVALID_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1389) | *Output RREADY_S2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1393) | *Output AWID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1394) | *Output AWADDR_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1395) | *Output AWLEN_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1396) | *Output AWSIZE_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1397) | *Output AWBURST_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1398) | *Output AWLOCK_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1399) | *Output AWCACHE_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1400) | *Output AWPROT_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1401) | *Output AWVALID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1404) | *Output WID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1405) | *Output WDATA_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1406) | *Output WSTRB_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1407) | *Output WLAST_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1408) | *Output WVALID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1414) | *Output BREADY_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1416) | *Output ARID_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : coreaxi.v(1417) | *Output ARADDR_S3 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.

Only the first 100 messages of id 'CL318' are reported. To see all messages use 'report_messages -log C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synlog\top_compiler.srr -id CL318' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL318} -count unlimited' in the Tcl shell.
@N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work.

	FAMILY=32'b00000000000000000000000000010011
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000001
	VERSION_MAJOR=32'b00000000000000000000000000000111
	VERSION_MINOR=32'b00000000000000000000000000000000
	VERSION_MAJOR_VECTOR=16'b0000000000000111
	VERSION_MINOR_VECTOR=16'b0000000000000000
	S0=2'b00
	S1=2'b01
	S2=2'b10
   Generated name = CoreConfigP_Z5
Running optimization stage 1 on CoreConfigP_Z5 .......
@W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work.

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
	DEVICE_090=32'b00000000000000000000000000000001
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z6
Running optimization stage 1 on CoreResetP_Z6 .......
@W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work.
Running optimization stage 1 on RCOSC_25_50MHZ_FAB .......
@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work.
Running optimization stage 1 on RCOSC_25_50MHZ .......
@N:CG364 : MDDR_Demo_sb_FABOSC_0_OSC.v(5) | Synthesizing module MDDR_Demo_sb_FABOSC_0_OSC in library work.
Running optimization stage 1 on MDDR_Demo_sb_FABOSC_0_OSC .......
@N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work.
Running optimization stage 1 on OUTBUF .......
@N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF in library work.
Running optimization stage 1 on OUTBUF_DIFF .......
@N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work.
Running optimization stage 1 on BIBUF .......
@N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work.
Running optimization stage 1 on INBUF .......
@N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work.
Running optimization stage 1 on TRIBUFF .......
@N:CG364 : MDDR_Demo_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work.
Running optimization stage 1 on MSS_075 .......
@N:CG364 : MDDR_Demo_sb_MSS.v(9) | Synthesizing module MDDR_Demo_sb_MSS in library work.
Running optimization stage 1 on MDDR_Demo_sb_MSS .......
@N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work.
Running optimization stage 1 on SYSRESET .......
@N:CG364 : MDDR_Demo_sb.v(9) | Synthesizing module MDDR_Demo_sb in library work.
Running optimization stage 1 on MDDR_Demo_sb .......
@N:CG364 : MDDR_Demo.v(9) | Synthesizing module MDDR_Demo in library work.
Running optimization stage 1 on MDDR_Demo .......
@N:CG364 : MDDR_Demo_top.v(9) | Synthesizing module MDDR_Demo_top in library work.
Running optimization stage 1 on MDDR_Demo_top .......
@N:CG364 : DATA_HANDLE_FSM.v(22) | Synthesizing module DATAHANDLE_FSM in library work.

	DATA_WIDTH=32'b00000000000000000000000000100000
	ADDR_WIDTH=32'b00000000000000000000000000100000
   Generated name = DATAHANDLE_FSM_32s_32s
@W:CG296 : DATA_HANDLE_FSM.v(74) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W:CG290 : DATA_HANDLE_FSM.v(78) | Referenced variable user_option is not in sensitivity list.
@W:CG290 : DATA_HANDLE_FSM.v(84) | Referenced variable user_address is not in sensitivity list.
@W:CG290 : DATA_HANDLE_FSM.v(90) | Referenced variable user_data1 is not in sensitivity list.
@W:CG290 : DATA_HANDLE_FSM.v(96) | Referenced variable user_data2 is not in sensitivity list.
@W:CG290 : DATA_HANDLE_FSM.v(104) | Referenced variable ram_rdata is not in sensitivity list.
@W:CG133 : DATA_HANDLE_FSM.v(63) | Object SEL is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on DATAHANDLE_FSM_32s_32s .......
@N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work.
Running optimization stage 1 on RAM1K18 .......
@N:CG364 : UART_IF_TPSRAM_0_TPSRAM.v(5) | Synthesizing module UART_IF_TPSRAM_0_TPSRAM in library work.
Running optimization stage 1 on UART_IF_TPSRAM_0_TPSRAM .......
@N:CG364 : UART_IF_FSM.v(20) | Synthesizing module UART_IF_FSM in library work.
@N:CG179 : UART_IF_FSM.v(237) | Removing redundant assignment.
@N:CG179 : UART_IF_FSM.v(244) | Removing redundant assignment.
Running optimization stage 1 on UART_IF_FSM .......
@N:CG364 : UART_IF.v(9) | Synthesizing module UART_IF in library work.
Running optimization stage 1 on UART_IF .......
@N:CG364 : top.v(9) | Synthesizing module top in library work.
Running optimization stage 1 on top .......
Running optimization stage 2 on top .......
Running optimization stage 2 on UART_IF .......
Running optimization stage 2 on UART_IF_FSM .......
@N:CL201 : UART_IF_FSM.v(102) | Trying to extract state machine for register fsm.
Extracted state machine for register fsm
State machine has 12 reachable states with original encodings of:
   000000
   000001
   000010
   000100
   000101
   000111
   001000
   001010
   001011
   001100
   001101
   001110
@W:CL279 : UART_IF_FSM.v(102) | Pruning register bits 3 to 1 of RLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : UART_IF_FSM.v(102) | Pruning register bits 3 to 1 of WLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Running optimization stage 2 on UART_IF_TPSRAM_0_TPSRAM .......
Running optimization stage 2 on RAM1K18 .......
Running optimization stage 2 on DATAHANDLE_FSM_32s_32s .......
@N:CL201 : DATA_HANDLE_FSM.v(110) | Trying to extract state machine for register fsm.
Extracted state machine for register fsm
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL246 : DATA_HANDLE_FSM.v(49) | Input port bits 31 to 13 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : DATA_HANDLE_FSM.v(49) | Input port bits 1 to 0 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : DATA_HANDLE_FSM.v(48) | Input PENABLE is unused.
Running optimization stage 2 on MDDR_Demo_top .......
Running optimization stage 2 on MDDR_Demo .......
Running optimization stage 2 on MDDR_Demo_sb .......
Running optimization stage 2 on SYSRESET .......
Running optimization stage 2 on MDDR_Demo_sb_MSS .......
Running optimization stage 2 on MSS_075 .......
Running optimization stage 2 on TRIBUFF .......
Running optimization stage 2 on INBUF .......
Running optimization stage 2 on BIBUF .......
Running optimization stage 2 on OUTBUF_DIFF .......
Running optimization stage 2 on OUTBUF .......
Running optimization stage 2 on MDDR_Demo_sb_FABOSC_0_OSC .......
@N:CL159 : MDDR_Demo_sb_FABOSC_0_OSC.v(14) | Input XTL is unused.
Running optimization stage 2 on RCOSC_25_50MHZ .......
Running optimization stage 2 on RCOSC_25_50MHZ_FAB .......
Running optimization stage 2 on CoreResetP_Z6 .......
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state.
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state.
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state.
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state.
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state.
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused.
@N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused.
@N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused.
@N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused.
@N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused.
@N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused.
@N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused.
@N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused.
@N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused.
@N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused.
@N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused.
@N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused.
@N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused.
@N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused.
Running optimization stage 2 on CoreConfigP_Z5 .......
@N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused.
@N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused.
Running optimization stage 2 on axi_feedthrough_Z4 .......
@W:CL246 : axi_feedthrough.v(310) | Input port bits 5 to 4 of BID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : axi_feedthrough.v(326) | Input port bits 5 to 4 of RID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : axi_feedthrough.v(243) | Input ACLK is unused.
@N:CL159 : axi_feedthrough.v(244) | Input ARESETN is unused.
Running optimization stage 2 on MDDR_Demo_sb_COREAXI_0_COREAXI_Z3 .......
@N:CL159 : coreaxi.v(1135) | Input AWID_M1 is unused.
@N:CL159 : coreaxi.v(1136) | Input AWADDR_M1 is unused.
@N:CL159 : coreaxi.v(1137) | Input AWLEN_M1 is unused.
@N:CL159 : coreaxi.v(1138) | Input AWSIZE_M1 is unused.
@N:CL159 : coreaxi.v(1139) | Input AWBURST_M1 is unused.
@N:CL159 : coreaxi.v(1140) | Input AWLOCK_M1 is unused.
@N:CL159 : coreaxi.v(1141) | Input AWCACHE_M1 is unused.
@N:CL159 : coreaxi.v(1142) | Input AWPROT_M1 is unused.
@N:CL159 : coreaxi.v(1143) | Input AWVALID_M1 is unused.
@N:CL159 : coreaxi.v(1146) | Input WID_M1 is unused.
@N:CL159 : coreaxi.v(1147) | Input WDATA_M1 is unused.
@N:CL159 : coreaxi.v(1148) | Input WSTRB_M1 is unused.
@N:CL159 : coreaxi.v(1149) | Input WLAST_M1 is unused.
@N:CL159 : coreaxi.v(1150) | Input WVALID_M1 is unused.
@N:CL159 : coreaxi.v(1156) | Input BREADY_M1 is unused.
@N:CL159 : coreaxi.v(1158) | Input ARID_M1 is unused.
@N:CL159 : coreaxi.v(1159) | Input ARADDR_M1 is unused.
@N:CL159 : coreaxi.v(1160) | Input ARLEN_M1 is unused.
@N:CL159 : coreaxi.v(1161) | Input ARSIZE_M1 is unused.
@N:CL159 : coreaxi.v(1162) | Input ARBURST_M1 is unused.
@N:CL159 : coreaxi.v(1163) | Input ARLOCK_M1 is unused.
@N:CL159 : coreaxi.v(1164) | Input ARCACHE_M1 is unused.
@N:CL159 : coreaxi.v(1165) | Input ARPROT_M1 is unused.
@N:CL159 : coreaxi.v(1166) | Input ARVALID_M1 is unused.
@N:CL159 : coreaxi.v(1174) | Input RREADY_M1 is unused.
@N:CL159 : coreaxi.v(1178) | Input AWID_M2 is unused.
@N:CL159 : coreaxi.v(1179) | Input AWADDR_M2 is unused.
@N:CL159 : coreaxi.v(1180) | Input AWLEN_M2 is unused.
@N:CL159 : coreaxi.v(1181) | Input AWSIZE_M2 is unused.
@N:CL159 : coreaxi.v(1182) | Input AWBURST_M2 is unused.
@N:CL159 : coreaxi.v(1183) | Input AWLOCK_M2 is unused.
@N:CL159 : coreaxi.v(1184) | Input AWCACHE_M2 is unused.
@N:CL159 : coreaxi.v(1185) | Input AWPROT_M2 is unused.
@N:CL159 : coreaxi.v(1186) | Input AWVALID_M2 is unused.
@N:CL159 : coreaxi.v(1189) | Input WID_M2 is unused.
@N:CL159 : coreaxi.v(1190) | Input WDATA_M2 is unused.
@N:CL159 : coreaxi.v(1191) | Input WSTRB_M2 is unused.
@N:CL159 : coreaxi.v(1192) | Input WLAST_M2 is unused.
@N:CL159 : coreaxi.v(1193) | Input WVALID_M2 is unused.
@N:CL159 : coreaxi.v(1199) | Input BREADY_M2 is unused.
@N:CL159 : coreaxi.v(1201) | Input ARID_M2 is unused.
@N:CL159 : coreaxi.v(1202) | Input ARADDR_M2 is unused.
@N:CL159 : coreaxi.v(1203) | Input ARLEN_M2 is unused.
@N:CL159 : coreaxi.v(1204) | Input ARSIZE_M2 is unused.
@N:CL159 : coreaxi.v(1205) | Input ARBURST_M2 is unused.
@N:CL159 : coreaxi.v(1206) | Input ARLOCK_M2 is unused.
@N:CL159 : coreaxi.v(1207) | Input ARCACHE_M2 is unused.
@N:CL159 : coreaxi.v(1208) | Input ARPROT_M2 is unused.
@N:CL159 : coreaxi.v(1209) | Input ARVALID_M2 is unused.
@N:CL159 : coreaxi.v(1217) | Input RREADY_M2 is unused.
@N:CL159 : coreaxi.v(1221) | Input AWID_M3 is unused.
@N:CL159 : coreaxi.v(1222) | Input AWADDR_M3 is unused.
@N:CL159 : coreaxi.v(1223) | Input AWLEN_M3 is unused.
@N:CL159 : coreaxi.v(1224) | Input AWSIZE_M3 is unused.
@N:CL159 : coreaxi.v(1225) | Input AWBURST_M3 is unused.
@N:CL159 : coreaxi.v(1226) | Input AWLOCK_M3 is unused.
@N:CL159 : coreaxi.v(1227) | Input AWCACHE_M3 is unused.
@N:CL159 : coreaxi.v(1228) | Input AWPROT_M3 is unused.
@N:CL159 : coreaxi.v(1229) | Input AWVALID_M3 is unused.
@N:CL159 : coreaxi.v(1232) | Input WID_M3 is unused.
@N:CL159 : coreaxi.v(1233) | Input WDATA_M3 is unused.
@N:CL159 : coreaxi.v(1234) | Input WSTRB_M3 is unused.
@N:CL159 : coreaxi.v(1235) | Input WLAST_M3 is unused.
@N:CL159 : coreaxi.v(1236) | Input WVALID_M3 is unused.
@N:CL159 : coreaxi.v(1242) | Input BREADY_M3 is unused.
@N:CL159 : coreaxi.v(1244) | Input ARID_M3 is unused.
@N:CL159 : coreaxi.v(1245) | Input ARADDR_M3 is unused.
@N:CL159 : coreaxi.v(1246) | Input ARLEN_M3 is unused.
@N:CL159 : coreaxi.v(1247) | Input ARSIZE_M3 is unused.
@N:CL159 : coreaxi.v(1248) | Input ARBURST_M3 is unused.
@N:CL159 : coreaxi.v(1249) | Input ARLOCK_M3 is unused.
@N:CL159 : coreaxi.v(1250) | Input ARCACHE_M3 is unused.
@N:CL159 : coreaxi.v(1251) | Input ARPROT_M3 is unused.
@N:CL159 : coreaxi.v(1252) | Input ARVALID_M3 is unused.
@N:CL159 : coreaxi.v(1260) | Input RREADY_M3 is unused.
@N:CL159 : coreaxi.v(1316) | Input AWREADY_S1 is unused.

Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell.
Running optimization stage 2 on CoreAPB3_Z2 .......
Running optimization stage 2 on COREAPB3_MUXPTOB3 .......
Running optimization stage 2 on MDDR_Demo_sb_CCC_0_FCCC .......
Running optimization stage 2 on CCC .......
Running optimization stage 2 on CLKINT .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1 .......
@N:CL201 : AXI_IF.v(222) | Trying to extract state machine for register axi_fsm_read_state.
Extracted state machine for register axi_fsm_read_state
State machine has 3 reachable states with original encodings of:
   001
   010
   100
@N:CL201 : AXI_IF.v(95) | Trying to extract state machine for register axi_fsm_current_state.
Extracted state machine for register axi_fsm_current_state
State machine has 5 reachable states with original encodings of:
   001
   010
   011
   100
   101
@W:CL260 : AXI_IF.v(222) | Pruning register bit 1 of ARSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL279 : AXI_IF.v(95) | Pruning register bits 7 to 1 of WSTRB[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL260 : AXI_IF.v(95) | Pruning register bit 1 of AWSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synwork\layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:07s; Memory used current: 121MB peak: 131MB)

Process took 0h:00m:09s realtime, 0h:00m:07s cputime

Process completed successfully.
# Thu Apr  8 02:03:55 2021

###########################################################]
###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @

@N: :  | Running in 64-bit mode 
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 106MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Apr  8 02:03:56 2021

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synwork\top_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:08s; Memory used current: 23MB peak: 24MB)

Process took 0h:00m:10s realtime, 0h:00m:08s cputime

Process completed successfully.
# Thu Apr  8 02:03:56 2021

###########################################################]

###########################################################[

Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @

@N: :  | Running in 64-bit mode 
File C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Thu Apr  8 02:03:58 2021

###########################################################]

Premap Report

# Thu Apr  8 02:03:59 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

Reading constraint file: C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\designer\top\synthesis.fdc
@L: C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\top_scck.rpt 
See clock summary report "C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\top_scck.rpt"
@W:BN544 : synthesis.fdc(9) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology
@W:BN544 : synthesis.fdc(10) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 152MB peak: 152MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 152MB peak: 153MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 153MB peak: 153MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 155MB)

@W:BN132 : axi_if.v(95) | Removing sequential instance MDDR_Demo_top_0.AXI_IF_0.AWBURST_1[0] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWSIZE_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(222) | Removing sequential instance MDDR_Demo_top_0.AXI_IF_0.ARBURST_1[0] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARSIZE_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(1089) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_4 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_4 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_5 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_5 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_6 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_6 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_7 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_7 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_8 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_8 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_9 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_9 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_10 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_10 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND.
@W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(769) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(769) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(1388) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@N:BN115 : coreaxi.v(3681) | Removing instance genblk1\.u_axi_feedthrough (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) of type view:work.axi_feedthrough_Z4(verilog) because it does not drive other instances.
@N:BN115 : mddr_demo_sb.v(1081) | Removing instance COREAXI_0 (in view: work.MDDR_Demo_sb(verilog)) of type view:work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : uart_if_fsm.v(102) | Removing sequential instance start_read (in view: work.UART_IF_FSM(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:FX1184 :  | Applying syn_allowed_resources blockrams=109 on top level netlist top  

Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 194MB)

@W:MT688 : synthesis.fdc(9) | No path from master pin (-source) to source of clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 due to black box MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST 
@W:MT688 : synthesis.fdc(10) | No path from master pin (-source) to source of clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 due to black box MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST 


Clock Summary
******************

          Start                                                                            Requested     Requested     Clock                                                                                            Clock                Clock
Level     Clock                                                                            Frequency     Period        Type                                                                                             Group                Load 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT      50.0 MHz      20.000        declared                                                                                         default_clkgroup     31   
1 .         MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                           160.0 MHz     6.250         generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup     429  
1 .         MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                           40.0 MHz      25.000        generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup     153  
                                                                                                                                                                                                                                                  
0 -       MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     40.0 MHz      25.000        declared                                                                                         default_clkgroup     109  
==================================================================================================================================================================================================================================================



Clock Load Summary
***********************

                                                                                 Clock     Source                                                                                                   Clock Pin                                                                                     Non-clock Pin     Non-clock Pin                                                                                 
Clock                                                                            Load      Pin                                                                                                      Seq Example                                                                                   Seq Example       Comb Example                                                                                  
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT      31        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ)              MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_enable_q1.C                 -                 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB)
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                             429       MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST.GL2(CCC)                                       UART_IF_0.UART_IF_FSM_0.option[7:0].C                                                         -                 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.GL2_INST.I(BUFG)                             
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                             153       MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST.GL0(CCC)                                       UART_IF_0.TPSRAM_0.UART_IF_TPSRAM_0_TPSRAM_R0C2.A_CLK                                         -                 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.GL0_INST.I(BUFG)                             
                                                                                                                                                                                                                                                                                                                                                                                                                  
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     109       MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_075)     MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST.CLK_MDDR_APB     -                 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv)       
==================================================================================================================================================================================================================================================================================================================================================================================================================

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\top.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 186MB peak: 194MB)

Encoding state machine axi_fsm_current_state[4:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00001
   010 -> 00010
   011 -> 00100
   100 -> 01000
   101 -> 10000
Encoding state machine axi_fsm_read_state[2:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00
   010 -> 01
   100 -> 10
Encoding state machine state[2:0] (in view: work.CoreConfigP_Z5(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : data_handle_fsm.v(110) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog)); safe FSM implementation is not required.
Encoding state machine fsm[11:0] (in view: work.UART_IF_FSM(verilog))
original code -> new code
   000000 -> 000000000001
   000001 -> 000000000010
   000010 -> 000000000100
   000100 -> 000000001000
   000101 -> 000000010000
   000111 -> 000000100000
   001000 -> 000001000000
   001010 -> 000010000000
   001011 -> 000100000000
   001100 -> 001000000000
   001101 -> 010000000000
   001110 -> 100000000000

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 194MB)

@W:MF511 :  | Found issues with constraints. Please check constraint checker report "C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\top_cck.rpt" . 

Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 189MB peak: 194MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 98MB peak: 194MB)

Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Thu Apr  8 02:04:03 2021

###########################################################]

Map & Optimize Report

# Thu Apr  8 02:04:03 2021


Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I63442

Implementation : synthesis
Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 130MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 130MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB)

@N:MO111 : mddr_demo_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : mddr_demo_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : mddr_demo_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : mddr_demo_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.MDDR_Demo_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)

Encoding state machine axi_fsm_current_state[4:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00001
   010 -> 00010
   011 -> 00100
   100 -> 01000
   101 -> 10000
Encoding state machine axi_fsm_read_state[2:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog))
original code -> new code
   001 -> 00
   010 -> 01
   100 -> 10
@N:MO231 : axi_if.v(95) | Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) instance WDATA_int[63:0] 
Encoding state machine CORECONFIGP_0.state[2:0] (in view: work.MDDR_Demo_sb(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[16] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[17] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[18] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[19] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[20] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[21] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[22] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[23] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[24] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[25] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[26] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[27] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[28] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[29] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[30] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[31] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[11] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[31] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[30] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[29] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[28] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[27] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[26] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[25] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[24] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[23] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[22] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[21] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[20] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[19] (in view view:work.MDDR_Demo_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[14] (in view: work.MDDR_Demo_sb(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@W:BN132 : coreconfigp.v(546) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z6(verilog) instance count_ddr[13:0] 
Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : data_handle_fsm.v(110) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog)); safe FSM implementation is not required.
Encoding state machine fsm[11:0] (in view: work.UART_IF_FSM(verilog))
original code -> new code
   000000 -> 000000000001
   000001 -> 000000000010
   000010 -> 000000000100
   000100 -> 000000001000
   000101 -> 000000010000
   000111 -> 000000100000
   001000 -> 000001000000
   001010 -> 000010000000
   001011 -> 000100000000
   001100 -> 001000000000
   001101 -> 010000000000
   001110 -> 100000000000
@N:MO231 : uart_if_fsm.v(102) | Found counter in view:work.UART_IF_FSM(verilog) instance RAM_WADDR[7:0] 
@N:MO231 : uart_if_fsm.v(102) | Found counter in view:work.UART_IF_FSM(verilog) instance cnt_1k[9:0] 

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB)

@W:BN132 : axi_if.v(95) | Removing instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[3] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(95) | Removing instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[2] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(95) | Removing instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[1] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWLEN[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(222) | Removing instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[3] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(222) | Removing instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[2] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : axi_if.v(222) | Removing instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[1] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARLEN[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.DDR_READY_int (in view: work.MDDR_Demo_top(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 183MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 183MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 183MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 181MB peak: 183MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 181MB peak: 183MB)


Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 183MB)


Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 182MB peak: 183MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -2.87ns		 626 /       669
   2		0h:00m:03s		    -2.87ns		 624 /       669
   3		0h:00m:03s		    -2.87ns		 624 /       669
@N:FX271 : mddr_demo_top.v(318) | Replicating instance MDDR_Demo_top_0.AXI_IF_0.WDATA_intlde_0 (in view: work.top(verilog)) with 64 loads 3 times to improve timing.
@N:FX271 : axi_if.v(95) | Replicating instance MDDR_Demo_top_0.AXI_IF_0.N_145_i_0_o2 (in view: work.top(verilog)) with 68 loads 3 times to improve timing.
@N:FX271 : uart_if_fsm.v(102) | Replicating instance UART_IF_0.UART_IF_FSM_0.fsm_ns[0] (in view: work.top(verilog)) with 2 loads 1 time(s) to improve timing.
Timing driven replication report
Added 0 Registers via timing driven replication
Added 7 LUTs via timing driven replication

   4		0h:00m:03s		    -1.53ns		 631 /       669
   5		0h:00m:03s		    -1.53ns		 632 /       669

@N:FX271 : mddr_demo_top.v(318) | Replicating instance MDDR_Demo_top_0.AXI_IF_0.WDATA_intlde_0_a2 (in view: work.top(verilog)) with 34 loads 2 times to improve timing.
Timing driven replication report
Added 0 Registers via timing driven replication
Added 2 LUTs via timing driven replication

   6		0h:00m:04s		    -1.29ns		 638 /       669
   7		0h:00m:04s		    -0.60ns		 638 /       669
   8		0h:00m:04s		    -0.61ns		 640 /       669
@N:FP130 :  | Promoting Net INIT_DONE_int_arst on CLKINT  I_261  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT  I_262  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_263  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_264  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_265  
@N:FP130 :  | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT  I_266  

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 183MB peak: 183MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 183MB peak: 183MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
2 non-gated/non-generated clock tree(s) driving 106 clock pin(s) of sequential element(s)
2 gated/generated clock tree(s) driving 574 clock pin(s) of sequential element(s)
0 instances converted, 574 sequential instances remain driven by gated/generated clocks

================================================================================================ Non-Gated/Non-Generated Clocks =================================================================================================
Clock Tree ID     Driving Element                                                                  Drive Element Type                     Fanout     Sample Instance                                                             
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0003        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     clock definition on MSS_075            75         MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST
ClockId0004        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ             clock definition on RCOSC_25_50MHZ     31         MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[13]       
=================================================================================================================================================================================================================================
=================================================================================================================== Gated/Generated Clocks ===================================================================================================================
Clock Tree ID     Driving Element                                               Drive Element Type     Fanout     Sample Instance                                                                  Explanation                                                
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST     CCC                    423        MDDR_Demo_top_0.AXI_IF_0.WDATA_int[63]                                           No gated clock conversion method for cell cell:ACG4.SLE    
ClockId0002        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST     CCC                    151        MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     No gated clock conversion method for cell cell:work.MSS_075
==============================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 150MB peak: 183MB)

Writing Analyst data base C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\synwork\top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 181MB peak: 183MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\top.edn 
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
Writing FDC file C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\top_synplify.fdc

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 183MB peak: 183MB)


Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 181MB peak: 183MB)

@W:MT246 : mddr_demo_sb_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns  
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB with period 25.00ns  
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 with period 25.00ns  
@N:MT615 :  | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 with period 6.25ns  


##### START OF TIMING REPORT #####[
# Timing report written on Thu Apr  8 02:04:11 2021
#


Top view:               top
Requested Frequency:    40.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\designer\top\synthesis.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -0.230

                                                                                 Requested     Estimated     Requested     Estimated                Clock                                                                                            Clock           
Starting Clock                                                                   Frequency     Frequency     Period        Period        Slack      Type                                                                                             Group           
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                             40.0 MHz      38.6 MHz      25.000        25.918        -0.230     generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                             160.0 MHz     154.3 MHz     6.250         6.479         2.161      generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT      50.0 MHz      502.7 MHz     20.000        1.989         18.011     declared                                                                                         default_clkgroup
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     40.0 MHz      127.4 MHz     25.000        7.849         8.576      declared                                                                                         default_clkgroup
=====================================================================================================================================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                                      Ending                                                                        |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT   MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT   |  20.000      18.011  |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT   MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          |  5.000       False   |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB  MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB  |  25.000      18.986  |  No paths    -      |  12.500      10.618  |  12.500      8.576
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB  MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          |  25.000      False   |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT   |  5.000       False   |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB  |  25.000      False   |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          |  25.000      15.015  |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                          |  6.250       -0.230  |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0                          |  6.250       3.566   |  No paths    -      |  No paths    -       |  No paths    -    
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                          MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2                          |  6.250       2.161   |  No paths    -      |  No paths    -       |  No paths    -    
====================================================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                                                                                     Arrival           
Instance                                                                         Reference                                                Type        Pin                      Net                                            Time        Slack 
                                                                                 Clock                                                                                                                                                          
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_AWREADY_HREADYOUT0     AXI_IF_0_BIF_1_AWREADY                         3.980       -0.230
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_WREADY                 AXI_IF_0_BIF_1_WREADY                          3.547       -0.201
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_RVALID                 MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0        3.847       -0.064
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_RLAST                  MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0         3.844       0.050 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_RDATA_HRDATA01[31]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[31]     4.508       1.180 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_ARREADY_HREADYOUT1     AXI_IF_0_BIF_1_ARREADY                         3.513       1.324 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_BVALID                 AXI_IF_0_BIF_1_BVALID                          3.457       1.427 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_RDATA_HRDATA01[41]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[41]     4.064       1.624 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_RDATA_HRDATA01[29]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[29]     4.037       1.651 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     MSS_075     F_RDATA_HRDATA01[43]     MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[43]     4.033       1.655 
================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                       Starting                                                                                     Required           
Instance                               Reference                                                Type     Pin     Net                Time         Slack 
                                       Clock                                                                                                           
-------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.AXI_IF_0.WDATA[5]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[6]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[7]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[8]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[9]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[10]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[11]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[12]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[13]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
MDDR_Demo_top_0.AXI_IF_0.WDATA[14]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0     SLE      EN      N_145_i_0_rep1     5.957        -0.230
=======================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.250
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.957

    - Propagation time:                      6.186
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.229

    Number of logic level(s):                1
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_AWREADY_HREADYOUT0
    Ending point:                            MDDR_Demo_top_0.AXI_IF_0.WDATA[5] / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK_BASE
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK

Instance / Net                                                                               Pin                      Pin               Arrival     No. of    
Name                                                                             Type        Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MSS_075     F_AWREADY_HREADYOUT0     Out     3.980     3.980 f     -         
AXI_IF_0_BIF_1_AWREADY                                                           Net         -                        -       0.995     -           16        
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        C                        In      -         4.975 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        Y                        Out     0.182     5.157 f     -         
N_145_i_0_rep1                                                                   Net         -                        -       1.029     -           20        
MDDR_Demo_top_0.AXI_IF_0.WDATA[5]                                                SLE         EN                       In      -         6.186 f     -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 6.479 is 4.456(68.8%) logic and 2.024(31.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      6.250
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.957

    - Propagation time:                      6.186
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.229

    Number of logic level(s):                1
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_AWREADY_HREADYOUT0
    Ending point:                            MDDR_Demo_top_0.AXI_IF_0.WDATA[25] / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK_BASE
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK

Instance / Net                                                                               Pin                      Pin               Arrival     No. of    
Name                                                                             Type        Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MSS_075     F_AWREADY_HREADYOUT0     Out     3.980     3.980 f     -         
AXI_IF_0_BIF_1_AWREADY                                                           Net         -                        -       0.995     -           16        
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V_0[1]                      CFG4        C                        In      -         4.975 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V_0[1]                      CFG4        Y                        Out     0.182     5.157 f     -         
N_145_i_0_rep2                                                                   Net         -                        -       1.029     -           20        
MDDR_Demo_top_0.AXI_IF_0.WDATA[25]                                               SLE         EN                       In      -         6.186 f     -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 6.479 is 4.456(68.8%) logic and 2.024(31.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      6.250
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.957

    - Propagation time:                      6.186
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.229

    Number of logic level(s):                1
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_AWREADY_HREADYOUT0
    Ending point:                            MDDR_Demo_top_0.AXI_IF_0.WDATA[18] / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK_BASE
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK

Instance / Net                                                                               Pin                      Pin               Arrival     No. of    
Name                                                                             Type        Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MSS_075     F_AWREADY_HREADYOUT0     Out     3.980     3.980 f     -         
AXI_IF_0_BIF_1_AWREADY                                                           Net         -                        -       0.995     -           16        
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        C                        In      -         4.975 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        Y                        Out     0.182     5.157 f     -         
N_145_i_0_rep1                                                                   Net         -                        -       1.029     -           20        
MDDR_Demo_top_0.AXI_IF_0.WDATA[18]                                               SLE         EN                       In      -         6.186 f     -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 6.479 is 4.456(68.8%) logic and 2.024(31.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      6.250
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.957

    - Propagation time:                      6.186
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.229

    Number of logic level(s):                1
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_AWREADY_HREADYOUT0
    Ending point:                            MDDR_Demo_top_0.AXI_IF_0.WDATA[17] / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK_BASE
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK

Instance / Net                                                                               Pin                      Pin               Arrival     No. of    
Name                                                                             Type        Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MSS_075     F_AWREADY_HREADYOUT0     Out     3.980     3.980 f     -         
AXI_IF_0_BIF_1_AWREADY                                                           Net         -                        -       0.995     -           16        
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        C                        In      -         4.975 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        Y                        Out     0.182     5.157 f     -         
N_145_i_0_rep1                                                                   Net         -                        -       1.029     -           20        
MDDR_Demo_top_0.AXI_IF_0.WDATA[17]                                               SLE         EN                       In      -         6.186 f     -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 6.479 is 4.456(68.8%) logic and 2.024(31.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      6.250
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.957

    - Propagation time:                      6.186
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.229

    Number of logic level(s):                1
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_AWREADY_HREADYOUT0
    Ending point:                            MDDR_Demo_top_0.AXI_IF_0.WDATA[16] / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK_BASE
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK

Instance / Net                                                                               Pin                      Pin               Arrival     No. of    
Name                                                                             Type        Name                     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MSS_075     F_AWREADY_HREADYOUT0     Out     3.980     3.980 f     -         
AXI_IF_0_BIF_1_AWREADY                                                           Net         -                        -       0.995     -           16        
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        C                        In      -         4.975 f     -         
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state_RNI188V[1]                        CFG4        Y                        Out     0.182     5.157 f     -         
N_145_i_0_rep1                                                                   Net         -                        -       1.029     -           20        
MDDR_Demo_top_0.AXI_IF_0.WDATA[16]                                               SLE         EN                       In      -         6.186 f     -         
==============================================================================================================================================================
Total path delay (propagation time + setup) of 6.479 is 4.456(68.8%) logic and 2.024(31.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2
====================================



Starting Points with Worst Slack
********************************

                                                      Starting                                                                                               Arrival          
Instance                                              Reference                                                Type     Pin     Net                          Time        Slack
                                                      Clock                                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
UART_IF_0.UART_IF_FSM_0.fsm[0]                        MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       fsm_i[0]                     0.076       2.161
UART_IF_0.UART_IF_FSM_0.fsm_rep[0]                    MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       fsm_rep[0]                   0.094       2.346
MDDR_Demo_top_0.AXI_IF_0.BREADY                       MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       MDDR_Demo_top_0_BREADY       0.094       2.388
MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[0]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       axi_fsm_current_state[0]     0.094       2.398
UART_IF_0.UART_IF_FSM_0.WRITE                         MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       UART_IF_0_WRITE              0.094       2.473
UART_IF_0.UART_IF_FSM_0.option[7]                     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       option[7]                    0.094       2.575
UART_IF_0.UART_IF_FSM_0.fsm[7]                        MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       fsm[7]                       0.094       2.584
UART_IF_0.UART_IF_FSM_0.option[6]                     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       option[6]                    0.094       2.618
MDDR_Demo_top_0.AXI_IF_0.AWLEN[0]                     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       AXI_IF_0_BIF_1_AWLEN[0]      0.094       2.958
UART_IF_0.UART_IF_FSM_0.option[3]                     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      Q       option[3]                    0.094       2.963
==============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                            Starting                                                                                        Required          
Instance                                    Reference                                                Type     Pin     Net                   Time         Slack
                                            Clock                                                                                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------
UART_IF_0.UART_IF_FSM_0.AXI_address[31]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[31]     6.028        2.161
UART_IF_0.UART_IF_FSM_0.AXI_address[30]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[30]     6.028        2.175
UART_IF_0.UART_IF_FSM_0.AXI_address[29]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[29]     6.028        2.189
UART_IF_0.UART_IF_FSM_0.AXI_address[28]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[28]     6.028        2.204
UART_IF_0.UART_IF_FSM_0.AXI_address[27]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[27]     6.028        2.218
UART_IF_0.UART_IF_FSM_0.AXI_address[26]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[26]     6.028        2.232
UART_IF_0.UART_IF_FSM_0.AXI_address[25]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[25]     6.028        2.246
UART_IF_0.UART_IF_FSM_0.AXI_address[24]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[24]     6.028        2.260
UART_IF_0.UART_IF_FSM_0.AXI_address[23]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[23]     6.028        2.275
UART_IF_0.UART_IF_FSM_0.AXI_address[22]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2     SLE      D       AXI_address_9[22]     6.028        2.289
==============================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      6.250
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         6.028

    - Propagation time:                      3.867
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.161

    Number of logic level(s):                28
    Starting point:                          UART_IF_0.UART_IF_FSM_0.fsm[0] / Q
    Ending point:                            UART_IF_0.UART_IF_FSM_0.AXI_address[31] / D
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] (rise=0.000 fall=3.125 period=6.250) on pin CLK

Instance / Net                                                Pin      Pin               Arrival     No. of    
Name                                                 Type     Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------
UART_IF_0.UART_IF_FSM_0.fsm[0]                       SLE      Q        Out     0.076     0.076 r     -         
fsm_i[0]                                             Net      -        -       1.839     -           98        
UART_IF_0.UART_IF_FSM_0.fsm_ns_a3_RNITNHC1[8]        CFG4     D        In      -         1.915 r     -         
UART_IF_0.UART_IF_FSM_0.fsm_ns_a3_RNITNHC1[8]        CFG4     Y        Out     0.284     2.199 f     -         
AXI_address_9_0_49_1                                 Net      -        -       0.216     -           1         
UART_IF_0.UART_IF_FSM_0.fsm_ns_a3_RNI7F0I2[8]        ARI1     D        In      -         2.415 f     -         
UART_IF_0.UART_IF_FSM_0.fsm_ns_a3_RNI7F0I2[8]        ARI1     FCO      Out     0.439     2.854 f     -         
AXI_address_9_0_cry_0_cy                             Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIJS653[7]      ARI1     FCI      In      -         2.854 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIJS653[7]      ARI1     FCO      Out     0.014     2.868 f     -         
AXI_address_9_0_cry_0                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI1CDO3[8]      ARI1     FCI      In      -         2.868 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI1CDO3[8]      ARI1     FCO      Out     0.014     2.882 f     -         
AXI_address_9_0_cry_1                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIHTJB4[9]      ARI1     FCI      In      -         2.882 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIHTJB4[9]      ARI1     FCO      Out     0.014     2.897 f     -         
AXI_address_9_0_cry_2                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIH6S25[10]     ARI1     FCI      In      -         2.897 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIH6S25[10]     ARI1     FCO      Out     0.014     2.911 f     -         
AXI_address_9_0_cry_3                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIJH4Q5[11]     ARI1     FCI      In      -         2.911 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIJH4Q5[11]     ARI1     FCO      Out     0.014     2.925 f     -         
AXI_address_9_0_cry_4                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNINUCH6[12]     ARI1     FCI      In      -         2.925 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNINUCH6[12]     ARI1     FCO      Out     0.014     2.939 f     -         
AXI_address_9_0_cry_5                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNITDL87[13]     ARI1     FCI      In      -         2.939 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNITDL87[13]     ARI1     FCO      Out     0.014     2.953 f     -         
AXI_address_9_0_cry_6                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI5VTV7[14]     ARI1     FCI      In      -         2.953 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI5VTV7[14]     ARI1     FCO      Out     0.014     2.968 f     -         
AXI_address_9_0_cry_7                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIFI6N8[15]     ARI1     FCI      In      -         2.968 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIFI6N8[15]     ARI1     FCO      Out     0.014     2.982 f     -         
AXI_address_9_0_cry_8                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIR7FE9[16]     ARI1     FCI      In      -         2.982 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIR7FE9[16]     ARI1     FCO      Out     0.014     2.996 f     -         
AXI_address_9_0_cry_9                                Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI9VN5A[17]     ARI1     FCI      In      -         2.996 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI9VN5A[17]     ARI1     FCO      Out     0.014     3.010 f     -         
AXI_address_9_0_cry_10                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIPO0TA[18]     ARI1     FCI      In      -         3.010 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIPO0TA[18]     ARI1     FCO      Out     0.014     3.024 f     -         
AXI_address_9_0_cry_11                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIBK9KB[19]     ARI1     FCI      In      -         3.024 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIBK9KB[19]     ARI1     FCO      Out     0.014     3.039 f     -         
AXI_address_9_0_cry_12                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNID1KBC[20]     ARI1     FCI      In      -         3.039 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNID1KBC[20]     ARI1     FCO      Out     0.014     3.053 f     -         
AXI_address_9_0_cry_13                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIHGU2D[21]     ARI1     FCI      In      -         3.053 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIHGU2D[21]     ARI1     FCO      Out     0.014     3.067 f     -         
AXI_address_9_0_cry_14                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIN19QD[22]     ARI1     FCI      In      -         3.067 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIN19QD[22]     ARI1     FCO      Out     0.014     3.081 f     -         
AXI_address_9_0_cry_15                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIVKJHE[23]     ARI1     FCI      In      -         3.081 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIVKJHE[23]     ARI1     FCO      Out     0.014     3.095 f     -         
AXI_address_9_0_cry_16                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI9AU8F[24]     ARI1     FCI      In      -         3.095 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI9AU8F[24]     ARI1     FCO      Out     0.014     3.110 f     -         
AXI_address_9_0_cry_17                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIL190G[25]     ARI1     FCI      In      -         3.110 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIL190G[25]     ARI1     FCO      Out     0.014     3.124 f     -         
AXI_address_9_0_cry_18                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI3RJNG[26]     ARI1     FCI      In      -         3.124 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI3RJNG[26]     ARI1     FCO      Out     0.014     3.138 f     -         
AXI_address_9_0_cry_19                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIJMUEH[27]     ARI1     FCI      In      -         3.138 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIJMUEH[27]     ARI1     FCO      Out     0.014     3.152 f     -         
AXI_address_9_0_cry_20                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI5K96I[28]     ARI1     FCI      In      -         3.152 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNI5K96I[28]     ARI1     FCO      Out     0.014     3.166 f     -         
AXI_address_9_0_cry_21                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIPJKTI[29]     ARI1     FCI      In      -         3.166 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIPJKTI[29]     ARI1     FCO      Out     0.014     3.181 f     -         
AXI_address_9_0_cry_22                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIT41LJ[30]     ARI1     FCI      In      -         3.181 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_RNIT41LJ[30]     ARI1     FCO      Out     0.014     3.195 f     -         
AXI_address_9_0_cry_23                               Net      -        -       0.000     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_9_RNO[31]        ARI1     FCI      In      -         3.195 f     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_9_RNO[31]        ARI1     S        Out     0.063     3.258 r     -         
N_425                                                Net      -        -       0.216     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address_9[31]            CFG3     C        In      -         3.474 r     -         
UART_IF_0.UART_IF_FSM_0.AXI_address_9[31]            CFG3     Y        Out     0.177     3.651 r     -         
AXI_address_9[31]                                    Net      -        -       0.216     -           1         
UART_IF_0.UART_IF_FSM_0.AXI_address[31]              SLE      D        In      -         3.867 r     -         
===============================================================================================================
Total path delay (propagation time + setup) of 4.089 is 1.602(39.2%) logic and 2.487(60.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT
====================================



Starting Points with Worst Slack
********************************

                                                                          Starting                                                                                                           Arrival           
Instance                                                                  Reference                                                                       Type     Pin     Net               Time        Slack 
                                                                          Clock                                                                                                                                
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[0]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[0]      0.076       18.011
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[1]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[1]      0.076       18.295
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[6]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[6]      0.076       18.314
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[4]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[4]      0.094       18.350
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[3]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[3]      0.076       18.382
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[11]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[11]     0.076       18.386
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[8]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[8]      0.094       18.418
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[12]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[12]     0.076       18.423
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[5]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[5]      0.076       18.454
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[9]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      Q       count_ddr[9]      0.094       18.457
===============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                          Starting                                                                                                             Required           
Instance                                                                  Reference                                                                       Type     Pin     Net                 Time         Slack 
                                                                          Clock                                                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled       MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      EN      ddr_settled4        19.706       18.011
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[13]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[13]     19.778       18.411
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[12]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[12]     19.778       18.425
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[11]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[11]     19.778       18.440
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[10]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[10]     19.778       18.454
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[9]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[9]      19.778       18.468
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[8]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[8]      19.778       18.482
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[7]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[7]      19.778       18.497
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[6]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[6]      19.778       18.511
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[5]      MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     SLE      D       count_ddr_s[5]      19.778       18.525
==================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.294
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.706

    - Propagation time:                      1.696
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 18.011

    Number of logic level(s):                2
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[0] / Q
    Ending point:                            MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[0]       SLE      Q        Out     0.076     0.076 r     -         
count_ddr[0]                                                               Net      -        -       0.648     -           3         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled4_9     CFG4     D        In      -         0.724 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled4_9     CFG4     Y        Out     0.284     1.008 f     -         
ddr_settled4_9                                                             Net      -        -       0.216     -           1         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled4       CFG4     D        In      -         1.224 f     -         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled4       CFG4     Y        Out     0.250     1.474 f     -         
ddr_settled4                                                               Net      -        -       0.221     -           1         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.ddr_settled        SLE      EN       In      -         1.696 f     -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB
====================================



Starting Points with Worst Slack
********************************

                                                                                 Starting                                                                                                                                                            Arrival           
Instance                                                                         Reference                                                                        Type        Pin                        Net                                         Time        Slack 
                                                                                 Clock                                                                                                                                                                                 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.psel                    MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          psel                                        0.076       8.576 
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.paddr[13]               MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          paddr[13]                                   0.094       10.618
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.paddr[12]               MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          paddr[12]                                   0.094       10.767
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[1]                MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          state[1]                                    0.076       10.826
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.paddr[15]               MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          paddr[15]                                   0.094       11.172
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[0]                MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          state[0]                                    0.076       11.195
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.MDDR_PENABLE            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE         Q                          CORECONFIGP_0_MDDR_APBmslave_PENABLE        0.094       11.434
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     MSS_075     MDDR_FABRIC_PRDATA[1]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[1]      4.666       18.986
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     MSS_075     MDDR_FABRIC_PREADY         CORECONFIGP_0_MDDR_APBmslave_PREADY         4.525       19.026
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     MSS_075     MDDR_FABRIC_PRDATA[15]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[15]     4.956       19.154
=======================================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                   Starting                                                                                                                                       Required          
Instance                                                                           Reference                                                                        Type     Pin     Net                                          Time         Slack
                                                                                   Clock                                                                                                                                                            
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY        MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      EN      un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0     12.207       8.576
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[1]                  MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       state_ns[1]                                  12.278       8.666
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[1]                                    12.278       8.688
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[0]                                    12.278       8.796
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[5]                                    12.278       8.796
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[2]                                    12.278       9.079
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[3]                                    12.278       9.079
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[4]                                    12.278       9.079
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[6]                                    12.278       9.079
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7]     MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB     SLE      D       prdata[7]                                    12.278       9.079
====================================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      12.500
    - Setup time:                            0.293
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.207

    - Propagation time:                      3.631
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 8.576

    Number of logic level(s):                4
    Starting point:                          MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.psel / Q
    Ending point:                            MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY / EN
    The start point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=12.500 period=25.000) on pin CLK
    The end   point is clocked by            MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK

Instance / Net                                                                                                 Pin      Pin               Arrival     No. of    
Name                                                                                                  Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.psel                                         SLE      Q        Out     0.076     0.076 r     -         
psel                                                                                                  Net      -        -       0.744     -           5         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_int_sel_0_sqmuxa_0_0                     CFG2     A        In      -         0.820 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_int_sel_0_sqmuxa_0_0                     CFG2     Y        Out     0.087     0.907 f     -         
un1_int_sel_0_sqmuxa_i                                                                                Net      -        -       0.744     -           5         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_e1_0_a2                               CFG3     A        In      -         1.651 f     -         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_e1_0_a2                               CFG3     Y        Out     0.087     1.738 r     -         
prdata_e1                                                                                             Net      -        -       1.010     -           18        
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_e1_0_a2_RNIJ6QL                       CFG2     A        In      -         2.747 r     -         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_e1_0_a2_RNIJ6QL                       CFG2     Y        Out     0.087     2.835 f     -         
pready                                                                                                Net      -        -       0.432     -           2         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0     CFG4     B        In      -         3.267 f     -         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0     CFG4     Y        Out     0.143     3.409 f     -         
un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0                                                              Net      -        -       0.221     -           1         
MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY                           SLE      EN       In      -         3.631 f     -         
================================================================================================================================================================
Total path delay (propagation time + setup) of 3.924 is 0.774(19.7%) logic and 3.150(80.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
@W:MT447 : synthesis.fdc(13) | Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(14) | Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(16) | Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(17) | Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT443 : synthesis.fdc(18) | Timing constraint (through [get_nets { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
None

Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 182MB peak: 183MB)


Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 182MB peak: 183MB)

---------------------------------------
Resource Usage Report for top 

Mapping to part: m2s090tsfbga484-1
Cell usage:
CCC             1 use
CLKINT          9 uses
MSS_075         1 use
RCOSC_25_50MHZ  1 use
RCOSC_25_50MHZ_FAB  1 use
SYSRESET        1 use
CFG1           6 uses
CFG2           64 uses
CFG3           194 uses
CFG4           146 uses

Carry cells:
ARI1            193 uses - used for arithmetic functions


Sequential Cells: 
SLE            670 uses

DSP Blocks:    0 of 84 (0%)

I/O ports: 54
I/O primitives: 52
BIBUF          20 uses
INBUF          2 uses
OUTBUF         28 uses
OUTBUF_DIFF    1 use
TRIBUFF        1 use


Global Clock Buffers: 9

RAM/ROM usage summary
Total Block RAMs (RAM1K18) : 4 of 109 (3%)

Total LUTs:    603

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 144; LUTs = 144;
MACC     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  670 + 0 + 144 + 0 = 814;
Total number of LUTs after P&R:  603 + 0 + 144 + 0 = 747;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 69MB peak: 183MB)

Process took 0h:00m:08s realtime, 0h:00m:07s cputime
# Thu Apr  8 02:04:11 2021

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