Project Settings Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090TS Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 148 323 0 - 00m:11s - 4/8/2021 2:03:56 AM (premap) Complete 46 23 0 0m:03s 0m:04s 194MB 4/8/2021 2:04:03 AM (fpga_mapper) Complete 50 27 0 0m:07s 0m:08s 183MB 4/8/2021 2:04:11 AM Multi-srs Generator Complete 4/8/2021 2:03:58 AM Area Summary Carry Cells 193 Sequential Cells 670 DSP Blocks (dsp_used) 0 I/O Cells 52 Global Clock Buffers 9 RAM1K18 (v_ram) 4 LUTs (total_luts) 603 Timing Summary Clock Name Req Freq Est Freq Slack MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 40.0 MHz 38.6 MHz -0.230 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 160.0 MHz 154.3 MHz 2.161 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 18.011 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB 40.0 MHz 127.4 MHz 8.576 Optimizations Summary Combined Clock Conversion 2 / 2