#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: D:\cap\sympify_bug_fix\synplify_L201609M-2_W #OS: Windows 8 6.2 #Hostname: W764D-ATHULDEEP # Tue Sep 12 09:32:58 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v" (library work) @I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\CCC_0\MDDR_Demo_sb_CCC_0_FCCC.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS_syn.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\MDDR_Demo_sb.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo\MDDR_Demo.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_top\MDDR_Demo_top.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\UART_IF\TPSRAM_0\UART_IF_TPSRAM_0_TPSRAM.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\UART_IF\UART_IF.v" (library work) @I::"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\SF2_MDDR_Demo\SF2_MDDR_Demo.v" (library work) Verilog syntax check successful! Selecting top level module SF2_MDDR_Demo @N:CG364 : AXI_IF.v(21) | Synthesizing module AXI_IF in library work. Idle_0=3'b000 Idle_1=3'b001 Write_0=3'b010 Write_1=3'b011 Read_0=3'b010 Read_1=3'b011 Read_2=3'b100 Bresp_0=3'b100 Write_2=3'b101 Generated name = AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1 @A:CL282 : AXI_IF.v(222) | Feedback mux created for signal ARLEN[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : AXI_IF.v(95) | Feedback mux created for signal AWLEN[3:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:CL282 : AXI_IF.v(95) | Feedback mux created for signal AWADDR[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CL190 : AXI_IF.v(95) | Optimizing register bit AWBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : AXI_IF.v(95) | Optimizing register bit AWSIZE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : AXI_IF.v(222) | Optimizing register bit ARBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : AXI_IF.v(95) | Pruning register bit 1 of AWBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : AXI_IF.v(95) | Pruning register bit 2 of AWSIZE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : AXI_IF.v(222) | Pruning register bit 1 of ARBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work. @N:CG364 : MDDR_Demo_sb_CCC_0_FCCC.v(5) | Synthesizing module MDDR_Demo_sb_CCC_0_FCCC in library work. @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z2 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. @W:CG1283 : MDDR_Demo_sb.v(1081) | Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value @N:CG364 : coreaxi.v(29) | Synthesizing module MDDR_Demo_sb_COREAXI_0_COREAXI in library work. FAMILY=32'b00000000000000000000000000010011 AXI_DWIDTH=32'b00000000000000000000000001000000 M0_SLAVE0ENABLE=32'b00000000000000000000000000000001 M0_SLAVE1ENABLE=32'b00000000000000000000000000000000 M0_SLAVE2ENABLE=32'b00000000000000000000000000000000 M0_SLAVE3ENABLE=32'b00000000000000000000000000000000 M0_SLAVE4ENABLE=32'b00000000000000000000000000000000 M0_SLAVE5ENABLE=32'b00000000000000000000000000000000 M0_SLAVE6ENABLE=32'b00000000000000000000000000000000 M0_SLAVE7ENABLE=32'b00000000000000000000000000000000 M0_SLAVE8ENABLE=32'b00000000000000000000000000000000 M0_SLAVE9ENABLE=32'b00000000000000000000000000000000 M0_SLAVE10ENABLE=32'b00000000000000000000000000000000 M0_SLAVE11ENABLE=32'b00000000000000000000000000000000 M0_SLAVE12ENABLE=32'b00000000000000000000000000000000 M0_SLAVE13ENABLE=32'b00000000000000000000000000000000 M0_SLAVE14ENABLE=32'b00000000000000000000000000000000 M0_SLAVE15ENABLE=32'b00000000000000000000000000000000 M0_SLAVE16ENABLE=32'b00000000000000000000000000000000 M1_SLAVE0ENABLE=32'b00000000000000000000000000000000 M1_SLAVE1ENABLE=32'b00000000000000000000000000000000 M1_SLAVE2ENABLE=32'b00000000000000000000000000000000 M1_SLAVE3ENABLE=32'b00000000000000000000000000000000 M1_SLAVE4ENABLE=32'b00000000000000000000000000000000 M1_SLAVE5ENABLE=32'b00000000000000000000000000000000 M1_SLAVE6ENABLE=32'b00000000000000000000000000000000 M1_SLAVE7ENABLE=32'b00000000000000000000000000000000 M1_SLAVE8ENABLE=32'b00000000000000000000000000000000 M1_SLAVE9ENABLE=32'b00000000000000000000000000000000 M1_SLAVE10ENABLE=32'b00000000000000000000000000000000 M1_SLAVE11ENABLE=32'b00000000000000000000000000000000 M1_SLAVE12ENABLE=32'b00000000000000000000000000000000 M1_SLAVE13ENABLE=32'b00000000000000000000000000000000 M1_SLAVE14ENABLE=32'b00000000000000000000000000000000 M1_SLAVE15ENABLE=32'b00000000000000000000000000000000 M1_SLAVE16ENABLE=32'b00000000000000000000000000000000 M2_SLAVE0ENABLE=32'b00000000000000000000000000000000 M2_SLAVE1ENABLE=32'b00000000000000000000000000000000 M2_SLAVE2ENABLE=32'b00000000000000000000000000000000 M2_SLAVE3ENABLE=32'b00000000000000000000000000000000 M2_SLAVE4ENABLE=32'b00000000000000000000000000000000 M2_SLAVE5ENABLE=32'b00000000000000000000000000000000 M2_SLAVE6ENABLE=32'b00000000000000000000000000000000 M2_SLAVE7ENABLE=32'b00000000000000000000000000000000 M2_SLAVE8ENABLE=32'b00000000000000000000000000000000 M2_SLAVE9ENABLE=32'b00000000000000000000000000000000 M2_SLAVE10ENABLE=32'b00000000000000000000000000000000 M2_SLAVE11ENABLE=32'b00000000000000000000000000000000 M2_SLAVE12ENABLE=32'b00000000000000000000000000000000 M2_SLAVE13ENABLE=32'b00000000000000000000000000000000 M2_SLAVE14ENABLE=32'b00000000000000000000000000000000 M2_SLAVE15ENABLE=32'b00000000000000000000000000000000 M2_SLAVE16ENABLE=32'b00000000000000000000000000000000 M3_SLAVE0ENABLE=32'b00000000000000000000000000000000 M3_SLAVE1ENABLE=32'b00000000000000000000000000000000 M3_SLAVE2ENABLE=32'b00000000000000000000000000000000 M3_SLAVE3ENABLE=32'b00000000000000000000000000000000 M3_SLAVE4ENABLE=32'b00000000000000000000000000000000 M3_SLAVE5ENABLE=32'b00000000000000000000000000000000 M3_SLAVE6ENABLE=32'b00000000000000000000000000000000 M3_SLAVE7ENABLE=32'b00000000000000000000000000000000 M3_SLAVE8ENABLE=32'b00000000000000000000000000000000 M3_SLAVE9ENABLE=32'b00000000000000000000000000000000 M3_SLAVE10ENABLE=32'b00000000000000000000000000000000 M3_SLAVE11ENABLE=32'b00000000000000000000000000000000 M3_SLAVE12ENABLE=32'b00000000000000000000000000000000 M3_SLAVE13ENABLE=32'b00000000000000000000000000000000 M3_SLAVE14ENABLE=32'b00000000000000000000000000000000 M3_SLAVE15ENABLE=32'b00000000000000000000000000000000 M3_SLAVE16ENABLE=32'b00000000000000000000000000000000 ID_WIDTH=32'b00000000000000000000000000000100 NUM_SLAVE_SLOT=32'b00000000000000000000000000010000 NUM_MASTER_SLOT=32'b00000000000000000000000000000001 MEMSPACE=32'b00000000000000000000000000000011 HGS_CFG=32'b00000000000000000000000000000001 ADDR_HGS_CFG=32'b00000000000000000000000000000001 SC_0=32'b00000000000000000000000000000000 SC_1=32'b00000000000000000000000000000000 SC_2=32'b00000000000000000000000000000000 SC_3=32'b00000000000000000000000000000000 SC_4=32'b00000000000000000000000000000000 SC_5=32'b00000000000000000000000000000000 SC_6=32'b00000000000000000000000000000000 SC_7=32'b00000000000000000000000000000000 SC_8=32'b00000000000000000000000000000000 SC_9=32'b00000000000000000000000000000000 SC_10=32'b00000000000000000000000000000000 SC_11=32'b00000000000000000000000000000000 SC_12=32'b00000000000000000000000000000000 SC_13=32'b00000000000000000000000000000000 SC_14=32'b00000000000000000000000000000000 SC_15=32'b00000000000000000000000000000000 FEED_THROUGH=32'b00000000000000000000000000000001 INP_REG_BUF=32'b00000000000000000000000000000001 OUT_REG_BUF=32'b00000000000000000000000000000001 RD_ACCEPTANCE=32'b00000000000000000000000000000100 WR_ACCEPTANCE=32'b00000000000000000000000000000100 AWIDTH1=32'b00000000000000000000000000011000 AWIDTH2=32'b00000000000000000000000000100000 AXI_AWIDTH=32'b00000000000000000000000000011000 AXI_STRBWIDTH=32'b00000000000000000000000000001000 BASE_ID_WIDTH=32'b00000000000000000000000000000010 SINGLE_MASTER=32'b00000000000000000000000000000001 SINGLE_SLAVE=32'b00000000000000000000000000000000 SINGLE_MASTER_SINGLE_SLAVE=32'b00000000000000000000000000000000 COMB_REG=512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 SLAVE_0=17'b00000000000000001 SLAVE_1=17'b00000000000000010 SLAVE_2=17'b00000000000000100 SLAVE_3=17'b00000000000001000 SLAVE_4=17'b00000000000010000 SLAVE_5=17'b00000000000100000 SLAVE_6=17'b00000000001000000 SLAVE_7=17'b00000000010000000 SLAVE_8=17'b00000000100000000 SLAVE_9=17'b00000001000000000 SLAVE_A=17'b00000010000000000 SLAVE_B=17'b00000100000000000 SLAVE_C=17'b00001000000000000 SLAVE_D=17'b00010000000000000 SLAVE_E=17'b00100000000000000 SLAVE_F=17'b01000000000000000 SLAVE_N=17'b10000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = MDDR_Demo_sb_COREAXI_0_COREAXI_Z3 @N:CG364 : axi_feedthrough.v(30) | Synthesizing module axi_feedthrough in library work. AXI_AWIDTH=32'b00000000000000000000000000011000 AXI_DWIDTH=32'b00000000000000000000000001000000 M0_SLAVE0ENABLE=32'b00000000000000000000000000000001 M0_SLAVE1ENABLE=32'b00000000000000000000000000000000 M0_SLAVE2ENABLE=32'b00000000000000000000000000000000 M0_SLAVE3ENABLE=32'b00000000000000000000000000000000 M0_SLAVE4ENABLE=32'b00000000000000000000000000000000 M0_SLAVE5ENABLE=32'b00000000000000000000000000000000 M0_SLAVE6ENABLE=32'b00000000000000000000000000000000 M0_SLAVE7ENABLE=32'b00000000000000000000000000000000 M0_SLAVE8ENABLE=32'b00000000000000000000000000000000 M0_SLAVE9ENABLE=32'b00000000000000000000000000000000 M0_SLAVE10ENABLE=32'b00000000000000000000000000000000 M0_SLAVE11ENABLE=32'b00000000000000000000000000000000 M0_SLAVE12ENABLE=32'b00000000000000000000000000000000 M0_SLAVE13ENABLE=32'b00000000000000000000000000000000 M0_SLAVE14ENABLE=32'b00000000000000000000000000000000 M0_SLAVE15ENABLE=32'b00000000000000000000000000000000 M0_SLAVE16ENABLE=32'b00000000000000000000000000000000 M1_SLAVE0ENABLE=32'b00000000000000000000000000000000 M1_SLAVE1ENABLE=32'b00000000000000000000000000000000 M1_SLAVE2ENABLE=32'b00000000000000000000000000000000 M1_SLAVE3ENABLE=32'b00000000000000000000000000000000 M1_SLAVE4ENABLE=32'b00000000000000000000000000000000 M1_SLAVE5ENABLE=32'b00000000000000000000000000000000 M1_SLAVE6ENABLE=32'b00000000000000000000000000000000 M1_SLAVE7ENABLE=32'b00000000000000000000000000000000 M1_SLAVE8ENABLE=32'b00000000000000000000000000000000 M1_SLAVE9ENABLE=32'b00000000000000000000000000000000 M1_SLAVE10ENABLE=32'b00000000000000000000000000000000 M1_SLAVE11ENABLE=32'b00000000000000000000000000000000 M1_SLAVE12ENABLE=32'b00000000000000000000000000000000 M1_SLAVE13ENABLE=32'b00000000000000000000000000000000 M1_SLAVE14ENABLE=32'b00000000000000000000000000000000 M1_SLAVE15ENABLE=32'b00000000000000000000000000000000 M1_SLAVE16ENABLE=32'b00000000000000000000000000000000 M2_SLAVE0ENABLE=32'b00000000000000000000000000000000 M2_SLAVE1ENABLE=32'b00000000000000000000000000000000 M2_SLAVE2ENABLE=32'b00000000000000000000000000000000 M2_SLAVE3ENABLE=32'b00000000000000000000000000000000 M2_SLAVE4ENABLE=32'b00000000000000000000000000000000 M2_SLAVE5ENABLE=32'b00000000000000000000000000000000 M2_SLAVE6ENABLE=32'b00000000000000000000000000000000 M2_SLAVE7ENABLE=32'b00000000000000000000000000000000 M2_SLAVE8ENABLE=32'b00000000000000000000000000000000 M2_SLAVE9ENABLE=32'b00000000000000000000000000000000 M2_SLAVE10ENABLE=32'b00000000000000000000000000000000 M2_SLAVE11ENABLE=32'b00000000000000000000000000000000 M2_SLAVE12ENABLE=32'b00000000000000000000000000000000 M2_SLAVE13ENABLE=32'b00000000000000000000000000000000 M2_SLAVE14ENABLE=32'b00000000000000000000000000000000 M2_SLAVE15ENABLE=32'b00000000000000000000000000000000 M2_SLAVE16ENABLE=32'b00000000000000000000000000000000 M3_SLAVE0ENABLE=32'b00000000000000000000000000000000 M3_SLAVE1ENABLE=32'b00000000000000000000000000000000 M3_SLAVE2ENABLE=32'b00000000000000000000000000000000 M3_SLAVE3ENABLE=32'b00000000000000000000000000000000 M3_SLAVE4ENABLE=32'b00000000000000000000000000000000 M3_SLAVE5ENABLE=32'b00000000000000000000000000000000 M3_SLAVE6ENABLE=32'b00000000000000000000000000000000 M3_SLAVE7ENABLE=32'b00000000000000000000000000000000 M3_SLAVE8ENABLE=32'b00000000000000000000000000000000 M3_SLAVE9ENABLE=32'b00000000000000000000000000000000 M3_SLAVE10ENABLE=32'b00000000000000000000000000000000 M3_SLAVE11ENABLE=32'b00000000000000000000000000000000 M3_SLAVE12ENABLE=32'b00000000000000000000000000000000 M3_SLAVE13ENABLE=32'b00000000000000000000000000000000 M3_SLAVE14ENABLE=32'b00000000000000000000000000000000 M3_SLAVE15ENABLE=32'b00000000000000000000000000000000 M3_SLAVE16ENABLE=32'b00000000000000000000000000000000 ID_WIDTH=32'b00000000000000000000000000000100 NUM_SLAVE_SLOT=32'b00000000000000000000000000010000 NUM_MASTER_SLOT=32'b00000000000000000000000000000001 MEMSPACE=32'b00000000000000000000000000000011 HGS_CFG=32'b00000000000000000000000000000001 ADDR_HGS_CFG=32'b00000000000000000000000000000001 SC_0=32'b00000000000000000000000000000000 SC_1=32'b00000000000000000000000000000000 SC_2=32'b00000000000000000000000000000000 SC_3=32'b00000000000000000000000000000000 SC_4=32'b00000000000000000000000000000000 SC_5=32'b00000000000000000000000000000000 SC_6=32'b00000000000000000000000000000000 SC_7=32'b00000000000000000000000000000000 SC_8=32'b00000000000000000000000000000000 SC_9=32'b00000000000000000000000000000000 SC_10=32'b00000000000000000000000000000000 SC_11=32'b00000000000000000000000000000000 SC_12=32'b00000000000000000000000000000000 SC_13=32'b00000000000000000000000000000000 SC_14=32'b00000000000000000000000000000000 SC_15=32'b00000000000000000000000000000000 FEED_THROUGH=32'b00000000000000000000000000000001 INP_REG_BUF=32'b00000000000000000000000000000001 OUT_REG_BUF=32'b00000000000000000000000000000001 WR_ACCEPTANCE=32'b00000000000000000000000000000100 RD_ACCEPTANCE=32'b00000000000000000000000000000100 BASE_ID_WIDTH=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 AXI_STRBWIDTH=32'b00000000000000000000000000001000 Generated name = axi_feedthrough_Z4 @W:CG360 : coreaxi.v(1307) | Removing wire AWID_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1308) | Removing wire AWADDR_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1309) | Removing wire AWLEN_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1310) | Removing wire AWSIZE_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1311) | Removing wire AWBURST_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1312) | Removing wire AWLOCK_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1313) | Removing wire AWCACHE_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1314) | Removing wire AWPROT_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1315) | Removing wire AWVALID_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1318) | Removing wire WID_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1319) | Removing wire WDATA_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1320) | Removing wire WSTRB_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1321) | Removing wire WLAST_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1322) | Removing wire WVALID_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1328) | Removing wire BREADY_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1330) | Removing wire ARID_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1331) | Removing wire ARADDR_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1332) | Removing wire ARLEN_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1333) | Removing wire ARSIZE_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1334) | Removing wire ARBURST_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1335) | Removing wire ARLOCK_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1336) | Removing wire ARCACHE_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1337) | Removing wire ARPROT_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1338) | Removing wire ARVALID_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1346) | Removing wire RREADY_S1, as there is no assignment to it. @W:CG360 : coreaxi.v(1350) | Removing wire AWID_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1351) | Removing wire AWADDR_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1352) | Removing wire AWLEN_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1353) | Removing wire AWSIZE_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1354) | Removing wire AWBURST_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1355) | Removing wire AWLOCK_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1356) | Removing wire AWCACHE_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1357) | Removing wire AWPROT_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1358) | Removing wire AWVALID_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1361) | Removing wire WID_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1362) | Removing wire WDATA_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1363) | Removing wire WSTRB_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1364) | Removing wire WLAST_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1365) | Removing wire WVALID_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1371) | Removing wire BREADY_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1373) | Removing wire ARID_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1374) | Removing wire ARADDR_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1375) | Removing wire ARLEN_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1376) | Removing wire ARSIZE_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1377) | Removing wire ARBURST_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1378) | Removing wire ARLOCK_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1379) | Removing wire ARCACHE_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1380) | Removing wire ARPROT_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1381) | Removing wire ARVALID_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1389) | Removing wire RREADY_S2, as there is no assignment to it. @W:CG360 : coreaxi.v(1393) | Removing wire AWID_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1394) | Removing wire AWADDR_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1395) | Removing wire AWLEN_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1396) | Removing wire AWSIZE_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1397) | Removing wire AWBURST_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1398) | Removing wire AWLOCK_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1399) | Removing wire AWCACHE_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1400) | Removing wire AWPROT_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1401) | Removing wire AWVALID_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1404) | Removing wire WID_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1405) | Removing wire WDATA_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1406) | Removing wire WSTRB_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1407) | Removing wire WLAST_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1408) | Removing wire WVALID_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1414) | Removing wire BREADY_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1416) | Removing wire ARID_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1417) | Removing wire ARADDR_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1418) | Removing wire ARLEN_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1419) | Removing wire ARSIZE_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1420) | Removing wire ARBURST_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1421) | Removing wire ARLOCK_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1422) | Removing wire ARCACHE_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1423) | Removing wire ARPROT_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1424) | Removing wire ARVALID_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1432) | Removing wire RREADY_S3, as there is no assignment to it. @W:CG360 : coreaxi.v(1436) | Removing wire AWID_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1437) | Removing wire AWADDR_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1438) | Removing wire AWLEN_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1439) | Removing wire AWSIZE_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1440) | Removing wire AWBURST_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1441) | Removing wire AWLOCK_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1442) | Removing wire AWCACHE_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1443) | Removing wire AWPROT_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1444) | Removing wire AWVALID_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1447) | Removing wire WID_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1448) | Removing wire WDATA_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1449) | Removing wire WSTRB_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1450) | Removing wire WLAST_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1451) | Removing wire WVALID_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1457) | Removing wire BREADY_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1459) | Removing wire ARID_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1460) | Removing wire ARADDR_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1461) | Removing wire ARLEN_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1462) | Removing wire ARSIZE_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1463) | Removing wire ARBURST_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1464) | Removing wire ARLOCK_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1465) | Removing wire ARCACHE_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1466) | Removing wire ARPROT_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1467) | Removing wire ARVALID_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1475) | Removing wire RREADY_S4, as there is no assignment to it. @W:CG360 : coreaxi.v(1479) | Removing wire AWID_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1480) | Removing wire AWADDR_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1481) | Removing wire AWLEN_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1482) | Removing wire AWSIZE_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1483) | Removing wire AWBURST_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1484) | Removing wire AWLOCK_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1485) | Removing wire AWCACHE_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1486) | Removing wire AWPROT_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1487) | Removing wire AWVALID_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1490) | Removing wire WID_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1491) | Removing wire WDATA_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1492) | Removing wire WSTRB_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1493) | Removing wire WLAST_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1494) | Removing wire WVALID_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1500) | Removing wire BREADY_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1502) | Removing wire ARID_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1503) | Removing wire ARADDR_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1504) | Removing wire ARLEN_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1505) | Removing wire ARSIZE_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1506) | Removing wire ARBURST_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1507) | Removing wire ARLOCK_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1508) | Removing wire ARCACHE_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1509) | Removing wire ARPROT_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1510) | Removing wire ARVALID_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1518) | Removing wire RREADY_S5, as there is no assignment to it. @W:CG360 : coreaxi.v(1522) | Removing wire AWID_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1523) | Removing wire AWADDR_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1524) | Removing wire AWLEN_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1525) | Removing wire AWSIZE_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1526) | Removing wire AWBURST_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1527) | Removing wire AWLOCK_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1528) | Removing wire AWCACHE_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1529) | Removing wire AWPROT_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1530) | Removing wire AWVALID_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1533) | Removing wire WID_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1534) | Removing wire WDATA_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1535) | Removing wire WSTRB_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1536) | Removing wire WLAST_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1537) | Removing wire WVALID_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1543) | Removing wire BREADY_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1545) | Removing wire ARID_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1546) | Removing wire ARADDR_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1547) | Removing wire ARLEN_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1548) | Removing wire ARSIZE_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1549) | Removing wire ARBURST_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1550) | Removing wire ARLOCK_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1551) | Removing wire ARCACHE_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1552) | Removing wire ARPROT_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1553) | Removing wire ARVALID_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1561) | Removing wire RREADY_S6, as there is no assignment to it. @W:CG360 : coreaxi.v(1565) | Removing wire AWID_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1566) | Removing wire AWADDR_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1567) | Removing wire AWLEN_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1568) | Removing wire AWSIZE_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1569) | Removing wire AWBURST_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1570) | Removing wire AWLOCK_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1571) | Removing wire AWCACHE_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1572) | Removing wire AWPROT_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1573) | Removing wire AWVALID_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1576) | Removing wire WID_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1577) | Removing wire WDATA_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1578) | Removing wire WSTRB_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1579) | Removing wire WLAST_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1580) | Removing wire WVALID_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1586) | Removing wire BREADY_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1588) | Removing wire ARID_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1589) | Removing wire ARADDR_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1590) | Removing wire ARLEN_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1591) | Removing wire ARSIZE_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1592) | Removing wire ARBURST_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1593) | Removing wire ARLOCK_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1594) | Removing wire ARCACHE_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1595) | Removing wire ARPROT_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1596) | Removing wire ARVALID_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1604) | Removing wire RREADY_S7, as there is no assignment to it. @W:CG360 : coreaxi.v(1608) | Removing wire AWID_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1609) | Removing wire AWADDR_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1610) | Removing wire AWLEN_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1611) | Removing wire AWSIZE_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1612) | Removing wire AWBURST_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1613) | Removing wire AWLOCK_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1614) | Removing wire AWCACHE_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1615) | Removing wire AWPROT_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1616) | Removing wire AWVALID_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1619) | Removing wire WID_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1620) | Removing wire WDATA_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1621) | Removing wire WSTRB_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1622) | Removing wire WLAST_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1623) | Removing wire WVALID_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1629) | Removing wire BREADY_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1631) | Removing wire ARID_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1632) | Removing wire ARADDR_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1633) | Removing wire ARLEN_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1634) | Removing wire ARSIZE_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1635) | Removing wire ARBURST_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1636) | Removing wire ARLOCK_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1637) | Removing wire ARCACHE_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1638) | Removing wire ARPROT_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1639) | Removing wire ARVALID_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1647) | Removing wire RREADY_S8, as there is no assignment to it. @W:CG360 : coreaxi.v(1651) | Removing wire AWID_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1652) | Removing wire AWADDR_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1653) | Removing wire AWLEN_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1654) | Removing wire AWSIZE_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1655) | Removing wire AWBURST_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1656) | Removing wire AWLOCK_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1657) | Removing wire AWCACHE_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1658) | Removing wire AWPROT_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1659) | Removing wire AWVALID_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1662) | Removing wire WID_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1663) | Removing wire WDATA_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1664) | Removing wire WSTRB_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1665) | Removing wire WLAST_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1666) | Removing wire WVALID_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1672) | Removing wire BREADY_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1674) | Removing wire ARID_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1675) | Removing wire ARADDR_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1676) | Removing wire ARLEN_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1677) | Removing wire ARSIZE_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1678) | Removing wire ARBURST_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1679) | Removing wire ARLOCK_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1680) | Removing wire ARCACHE_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1681) | Removing wire ARPROT_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1682) | Removing wire ARVALID_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1690) | Removing wire RREADY_S9, as there is no assignment to it. @W:CG360 : coreaxi.v(1694) | Removing wire AWID_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1695) | Removing wire AWADDR_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1696) | Removing wire AWLEN_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1697) | Removing wire AWSIZE_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1698) | Removing wire AWBURST_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1699) | Removing wire AWLOCK_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1700) | Removing wire AWCACHE_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1701) | Removing wire AWPROT_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1702) | Removing wire AWVALID_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1705) | Removing wire WID_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1706) | Removing wire WDATA_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1707) | Removing wire WSTRB_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1708) | Removing wire WLAST_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1709) | Removing wire WVALID_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1715) | Removing wire BREADY_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1717) | Removing wire ARID_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1718) | Removing wire ARADDR_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1719) | Removing wire ARLEN_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1720) | Removing wire ARSIZE_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1721) | Removing wire ARBURST_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1722) | Removing wire ARLOCK_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1723) | Removing wire ARCACHE_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1724) | Removing wire ARPROT_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1725) | Removing wire ARVALID_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1733) | Removing wire RREADY_S10, as there is no assignment to it. @W:CG360 : coreaxi.v(1737) | Removing wire AWID_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1738) | Removing wire AWADDR_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1739) | Removing wire AWLEN_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1740) | Removing wire AWSIZE_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1741) | Removing wire AWBURST_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1742) | Removing wire AWLOCK_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1743) | Removing wire AWCACHE_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1744) | Removing wire AWPROT_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1745) | Removing wire AWVALID_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1748) | Removing wire WID_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1749) | Removing wire WDATA_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1750) | Removing wire WSTRB_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1751) | Removing wire WLAST_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1752) | Removing wire WVALID_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1758) | Removing wire BREADY_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1760) | Removing wire ARID_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1761) | Removing wire ARADDR_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1762) | Removing wire ARLEN_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1763) | Removing wire ARSIZE_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1764) | Removing wire ARBURST_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1765) | Removing wire ARLOCK_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1766) | Removing wire ARCACHE_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1767) | Removing wire ARPROT_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1768) | Removing wire ARVALID_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1776) | Removing wire RREADY_S11, as there is no assignment to it. @W:CG360 : coreaxi.v(1780) | Removing wire AWID_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1781) | Removing wire AWADDR_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1782) | Removing wire AWLEN_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1783) | Removing wire AWSIZE_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1784) | Removing wire AWBURST_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1785) | Removing wire AWLOCK_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1786) | Removing wire AWCACHE_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1787) | Removing wire AWPROT_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1788) | Removing wire AWVALID_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1791) | Removing wire WID_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1792) | Removing wire WDATA_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1793) | Removing wire WSTRB_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1794) | Removing wire WLAST_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1795) | Removing wire WVALID_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1801) | Removing wire BREADY_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1803) | Removing wire ARID_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1804) | Removing wire ARADDR_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1805) | Removing wire ARLEN_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1806) | Removing wire ARSIZE_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1807) | Removing wire ARBURST_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1808) | Removing wire ARLOCK_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1809) | Removing wire ARCACHE_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1810) | Removing wire ARPROT_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1811) | Removing wire ARVALID_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1819) | Removing wire RREADY_S12, as there is no assignment to it. @W:CG360 : coreaxi.v(1823) | Removing wire AWID_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1824) | Removing wire AWADDR_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1825) | Removing wire AWLEN_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1826) | Removing wire AWSIZE_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1827) | Removing wire AWBURST_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1828) | Removing wire AWLOCK_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1829) | Removing wire AWCACHE_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1830) | Removing wire AWPROT_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1831) | Removing wire AWVALID_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1834) | Removing wire WID_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1835) | Removing wire WDATA_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1836) | Removing wire WSTRB_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1837) | Removing wire WLAST_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1838) | Removing wire WVALID_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1844) | Removing wire BREADY_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1846) | Removing wire ARID_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1847) | Removing wire ARADDR_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1848) | Removing wire ARLEN_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1849) | Removing wire ARSIZE_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1850) | Removing wire ARBURST_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1851) | Removing wire ARLOCK_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1852) | Removing wire ARCACHE_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1853) | Removing wire ARPROT_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1854) | Removing wire ARVALID_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1862) | Removing wire RREADY_S13, as there is no assignment to it. @W:CG360 : coreaxi.v(1866) | Removing wire AWID_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1867) | Removing wire AWADDR_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1868) | Removing wire AWLEN_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1869) | Removing wire AWSIZE_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1870) | Removing wire AWBURST_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1871) | Removing wire AWLOCK_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1872) | Removing wire AWCACHE_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1873) | Removing wire AWPROT_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1874) | Removing wire AWVALID_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1877) | Removing wire WID_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1878) | Removing wire WDATA_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1879) | Removing wire WSTRB_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1880) | Removing wire WLAST_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1881) | Removing wire WVALID_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1887) | Removing wire BREADY_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1889) | Removing wire ARID_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1890) | Removing wire ARADDR_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1891) | Removing wire ARLEN_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1892) | Removing wire ARSIZE_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1893) | Removing wire ARBURST_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1894) | Removing wire ARLOCK_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1895) | Removing wire ARCACHE_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1896) | Removing wire ARPROT_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1897) | Removing wire ARVALID_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1905) | Removing wire RREADY_S14, as there is no assignment to it. @W:CG360 : coreaxi.v(1909) | Removing wire AWID_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1910) | Removing wire AWADDR_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1911) | Removing wire AWLEN_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1912) | Removing wire AWSIZE_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1913) | Removing wire AWBURST_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1914) | Removing wire AWLOCK_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1915) | Removing wire AWCACHE_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1916) | Removing wire AWPROT_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1917) | Removing wire AWVALID_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1920) | Removing wire WID_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1921) | Removing wire WDATA_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1922) | Removing wire WSTRB_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1923) | Removing wire WLAST_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1924) | Removing wire WVALID_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1930) | Removing wire BREADY_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1932) | Removing wire ARID_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1933) | Removing wire ARADDR_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1934) | Removing wire ARLEN_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1935) | Removing wire ARSIZE_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1936) | Removing wire ARBURST_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1937) | Removing wire ARLOCK_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1938) | Removing wire ARCACHE_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1939) | Removing wire ARPROT_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1940) | Removing wire ARVALID_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1948) | Removing wire RREADY_S15, as there is no assignment to it. @W:CG360 : coreaxi.v(1952) | Removing wire AWID_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1953) | Removing wire AWADDR_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1954) | Removing wire AWLEN_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1955) | Removing wire AWSIZE_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1956) | Removing wire AWBURST_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1957) | Removing wire AWLOCK_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1958) | Removing wire AWCACHE_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1959) | Removing wire AWPROT_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1960) | Removing wire AWVALID_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1963) | Removing wire WID_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1964) | Removing wire WDATA_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1965) | Removing wire WSTRB_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1966) | Removing wire WLAST_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1967) | Removing wire WVALID_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1973) | Removing wire BREADY_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1975) | Removing wire ARID_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1976) | Removing wire ARADDR_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1977) | Removing wire ARLEN_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1978) | Removing wire ARSIZE_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1979) | Removing wire ARBURST_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1980) | Removing wire ARLOCK_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1981) | Removing wire ARCACHE_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1982) | Removing wire ARPROT_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1983) | Removing wire ARVALID_S16, as there is no assignment to it. @W:CG360 : coreaxi.v(1996) | Removing wire AWREADY_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(1997) | Removing wire AWREADY_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(1998) | Removing wire AWREADY_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(1999) | Removing wire AWREADY_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2000) | Removing wire WREADY_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2001) | Removing wire WREADY_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2002) | Removing wire WREADY_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2003) | Removing wire WREADY_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2004) | Removing wire ARREADY_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2005) | Removing wire ARREADY_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2006) | Removing wire ARREADY_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2007) | Removing wire ARREADY_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2009) | Removing wire BREADY_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2010) | Removing wire BREADY_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2011) | Removing wire BREADY_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2012) | Removing wire BREADY_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2013) | Removing wire RREADY_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2014) | Removing wire RREADY_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2015) | Removing wire RREADY_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2016) | Removing wire RREADY_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2019) | Removing wire BVALID_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2020) | Removing wire BVALID_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2021) | Removing wire BVALID_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2022) | Removing wire BVALID_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2025) | Removing wire AWID_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2026) | Removing wire AWADDR_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2027) | Removing wire AWLEN_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2028) | Removing wire AWSIZE_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2029) | Removing wire AWBURST_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2030) | Removing wire AWLOCK_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2031) | Removing wire AWCACHE_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2032) | Removing wire AWPROT_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2033) | Removing wire AWVALID_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2036) | Removing wire WID_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2037) | Removing wire WDATA_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2038) | Removing wire WSTRB_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2039) | Removing wire WLAST_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2040) | Removing wire WVALID_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2042) | Removing wire BREADY_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2044) | Removing wire ARID_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2045) | Removing wire ARADDR_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2046) | Removing wire ARLEN_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2047) | Removing wire ARSIZE_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2048) | Removing wire ARBURST_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2049) | Removing wire ARLOCK_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2050) | Removing wire ARCACHE_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2051) | Removing wire ARPROT_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2052) | Removing wire ARVALID_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2055) | Removing wire RREADY_IS0, as there is no assignment to it. @W:CG360 : coreaxi.v(2057) | Removing wire AWID_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2058) | Removing wire AWADDR_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2059) | Removing wire AWLEN_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2060) | Removing wire AWSIZE_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2061) | Removing wire AWBURST_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2062) | Removing wire AWLOCK_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2063) | Removing wire AWCACHE_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2064) | Removing wire AWPROT_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2065) | Removing wire AWVALID_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2068) | Removing wire WID_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2069) | Removing wire WDATA_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2070) | Removing wire WSTRB_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2071) | Removing wire WLAST_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2072) | Removing wire WVALID_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2074) | Removing wire BREADY_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2076) | Removing wire ARID_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2077) | Removing wire ARADDR_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2078) | Removing wire ARLEN_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2079) | Removing wire ARSIZE_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2080) | Removing wire ARBURST_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2081) | Removing wire ARLOCK_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2082) | Removing wire ARCACHE_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2083) | Removing wire ARPROT_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2084) | Removing wire ARVALID_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2087) | Removing wire RREADY_IS1, as there is no assignment to it. @W:CG360 : coreaxi.v(2089) | Removing wire AWID_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2090) | Removing wire AWADDR_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2091) | Removing wire AWLEN_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2092) | Removing wire AWSIZE_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2093) | Removing wire AWBURST_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2094) | Removing wire AWLOCK_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2095) | Removing wire AWCACHE_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2096) | Removing wire AWPROT_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2097) | Removing wire AWVALID_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2100) | Removing wire WID_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2101) | Removing wire WDATA_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2102) | Removing wire WSTRB_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2103) | Removing wire WLAST_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2104) | Removing wire WVALID_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2106) | Removing wire BREADY_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2108) | Removing wire ARID_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2109) | Removing wire ARADDR_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2110) | Removing wire ARLEN_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2111) | Removing wire ARSIZE_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2112) | Removing wire ARBURST_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2113) | Removing wire ARLOCK_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2114) | Removing wire ARCACHE_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2115) | Removing wire ARPROT_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2116) | Removing wire ARVALID_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2119) | Removing wire RREADY_IS2, as there is no assignment to it. @W:CG360 : coreaxi.v(2121) | Removing wire AWID_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2122) | Removing wire AWADDR_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2123) | Removing wire AWLEN_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2124) | Removing wire AWSIZE_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2125) | Removing wire AWBURST_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2126) | Removing wire AWLOCK_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2127) | Removing wire AWCACHE_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2128) | Removing wire AWPROT_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2129) | Removing wire AWVALID_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2132) | Removing wire WID_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2133) | Removing wire WDATA_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2134) | Removing wire WSTRB_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2135) | Removing wire WLAST_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2136) | Removing wire WVALID_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2138) | Removing wire BREADY_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2140) | Removing wire ARID_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2141) | Removing wire ARADDR_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2142) | Removing wire ARLEN_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2143) | Removing wire ARSIZE_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2144) | Removing wire ARBURST_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2145) | Removing wire ARLOCK_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2146) | Removing wire ARCACHE_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2147) | Removing wire ARPROT_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2148) | Removing wire ARVALID_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2151) | Removing wire RREADY_IS3, as there is no assignment to it. @W:CG360 : coreaxi.v(2153) | Removing wire AWID_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2154) | Removing wire AWADDR_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2155) | Removing wire AWLEN_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2156) | Removing wire AWSIZE_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2157) | Removing wire AWBURST_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2158) | Removing wire AWLOCK_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2159) | Removing wire AWCACHE_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2160) | Removing wire AWPROT_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2161) | Removing wire AWVALID_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2164) | Removing wire WID_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2165) | Removing wire WDATA_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2166) | Removing wire WSTRB_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2167) | Removing wire WLAST_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2168) | Removing wire WVALID_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2170) | Removing wire BREADY_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2172) | Removing wire ARID_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2173) | Removing wire ARADDR_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2174) | Removing wire ARLEN_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2175) | Removing wire ARSIZE_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2176) | Removing wire ARBURST_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2177) | Removing wire ARLOCK_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2178) | Removing wire ARCACHE_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2179) | Removing wire ARPROT_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2180) | Removing wire ARVALID_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2183) | Removing wire RREADY_IS4, as there is no assignment to it. @W:CG360 : coreaxi.v(2185) | Removing wire AWID_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2186) | Removing wire AWADDR_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2187) | Removing wire AWLEN_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2188) | Removing wire AWSIZE_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2189) | Removing wire AWBURST_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2190) | Removing wire AWLOCK_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2191) | Removing wire AWCACHE_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2192) | Removing wire AWPROT_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2193) | Removing wire AWVALID_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2196) | Removing wire WID_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2197) | Removing wire WDATA_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2198) | Removing wire WSTRB_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2199) | Removing wire WLAST_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2200) | Removing wire WVALID_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2202) | Removing wire BREADY_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2204) | Removing wire ARID_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2205) | Removing wire ARADDR_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2206) | Removing wire ARLEN_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2207) | Removing wire ARSIZE_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2208) | Removing wire ARBURST_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2209) | Removing wire ARLOCK_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2210) | Removing wire ARCACHE_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2211) | Removing wire ARPROT_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2212) | Removing wire ARVALID_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2215) | Removing wire RREADY_IS5, as there is no assignment to it. @W:CG360 : coreaxi.v(2217) | Removing wire AWID_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2218) | Removing wire AWADDR_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2219) | Removing wire AWLEN_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2220) | Removing wire AWSIZE_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2221) | Removing wire AWBURST_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2222) | Removing wire AWLOCK_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2223) | Removing wire AWCACHE_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2224) | Removing wire AWPROT_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2225) | Removing wire AWVALID_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2228) | Removing wire WID_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2229) | Removing wire WDATA_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2230) | Removing wire WSTRB_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2231) | Removing wire WLAST_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2232) | Removing wire WVALID_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2234) | Removing wire BREADY_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2236) | Removing wire ARID_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2237) | Removing wire ARADDR_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2238) | Removing wire ARLEN_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2239) | Removing wire ARSIZE_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2240) | Removing wire ARBURST_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2241) | Removing wire ARLOCK_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2242) | Removing wire ARCACHE_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2243) | Removing wire ARPROT_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2244) | Removing wire ARVALID_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2247) | Removing wire RREADY_IS6, as there is no assignment to it. @W:CG360 : coreaxi.v(2249) | Removing wire AWID_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2250) | Removing wire AWADDR_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2251) | Removing wire AWLEN_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2252) | Removing wire AWSIZE_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2253) | Removing wire AWBURST_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2254) | Removing wire AWLOCK_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2255) | Removing wire AWCACHE_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2256) | Removing wire AWPROT_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2257) | Removing wire AWVALID_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2260) | Removing wire WID_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2261) | Removing wire WDATA_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2262) | Removing wire WSTRB_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2263) | Removing wire WLAST_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2264) | Removing wire WVALID_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2266) | Removing wire BREADY_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2268) | Removing wire ARID_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2269) | Removing wire ARADDR_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2270) | Removing wire ARLEN_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2271) | Removing wire ARSIZE_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2272) | Removing wire ARBURST_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2273) | Removing wire ARLOCK_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2274) | Removing wire ARCACHE_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2275) | Removing wire ARPROT_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2276) | Removing wire ARVALID_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2279) | Removing wire RREADY_IS7, as there is no assignment to it. @W:CG360 : coreaxi.v(2281) | Removing wire AWID_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2282) | Removing wire AWADDR_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2283) | Removing wire AWLEN_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2284) | Removing wire AWSIZE_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2285) | Removing wire AWBURST_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2286) | Removing wire AWLOCK_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2287) | Removing wire AWCACHE_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2288) | Removing wire AWPROT_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2289) | Removing wire AWVALID_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2292) | Removing wire WID_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2293) | Removing wire WDATA_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2294) | Removing wire WSTRB_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2295) | Removing wire WLAST_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2296) | Removing wire WVALID_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2298) | Removing wire BREADY_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2300) | Removing wire ARID_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2301) | Removing wire ARADDR_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2302) | Removing wire ARLEN_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2303) | Removing wire ARSIZE_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2304) | Removing wire ARBURST_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2305) | Removing wire ARLOCK_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2306) | Removing wire ARCACHE_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2307) | Removing wire ARPROT_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2308) | Removing wire ARVALID_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2311) | Removing wire RREADY_IS8, as there is no assignment to it. @W:CG360 : coreaxi.v(2313) | Removing wire AWID_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2314) | Removing wire AWADDR_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2315) | Removing wire AWLEN_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2316) | Removing wire AWSIZE_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2317) | Removing wire AWBURST_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2318) | Removing wire AWLOCK_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2319) | Removing wire AWCACHE_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2320) | Removing wire AWPROT_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2321) | Removing wire AWVALID_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2324) | Removing wire WID_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2325) | Removing wire WDATA_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2326) | Removing wire WSTRB_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2327) | Removing wire WLAST_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2328) | Removing wire WVALID_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2330) | Removing wire BREADY_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2332) | Removing wire ARID_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2333) | Removing wire ARADDR_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2334) | Removing wire ARLEN_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2335) | Removing wire ARSIZE_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2336) | Removing wire ARBURST_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2337) | Removing wire ARLOCK_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2338) | Removing wire ARCACHE_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2339) | Removing wire ARPROT_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2340) | Removing wire ARVALID_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2343) | Removing wire RREADY_IS9, as there is no assignment to it. @W:CG360 : coreaxi.v(2345) | Removing wire AWID_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2346) | Removing wire AWADDR_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2347) | Removing wire AWLEN_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2348) | Removing wire AWSIZE_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2349) | Removing wire AWBURST_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2350) | Removing wire AWLOCK_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2351) | Removing wire AWCACHE_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2352) | Removing wire AWPROT_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2353) | Removing wire AWVALID_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2356) | Removing wire WID_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2357) | Removing wire WDATA_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2358) | Removing wire WSTRB_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2359) | Removing wire WLAST_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2360) | Removing wire WVALID_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2362) | Removing wire BREADY_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2364) | Removing wire ARID_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2365) | Removing wire ARADDR_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2366) | Removing wire ARLEN_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2367) | Removing wire ARSIZE_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2368) | Removing wire ARBURST_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2369) | Removing wire ARLOCK_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2370) | Removing wire ARCACHE_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2371) | Removing wire ARPROT_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2372) | Removing wire ARVALID_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2375) | Removing wire RREADY_IS10, as there is no assignment to it. @W:CG360 : coreaxi.v(2377) | Removing wire AWID_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2378) | Removing wire AWADDR_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2379) | Removing wire AWLEN_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2380) | Removing wire AWSIZE_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2381) | Removing wire AWBURST_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2382) | Removing wire AWLOCK_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2383) | Removing wire AWCACHE_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2384) | Removing wire AWPROT_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2385) | Removing wire AWVALID_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2388) | Removing wire WID_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2389) | Removing wire WDATA_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2390) | Removing wire WSTRB_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2391) | Removing wire WLAST_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2392) | Removing wire WVALID_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2394) | Removing wire BREADY_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2396) | Removing wire ARID_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2397) | Removing wire ARADDR_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2398) | Removing wire ARLEN_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2399) | Removing wire ARSIZE_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2400) | Removing wire ARBURST_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2401) | Removing wire ARLOCK_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2402) | Removing wire ARCACHE_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2403) | Removing wire ARPROT_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2404) | Removing wire ARVALID_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2407) | Removing wire RREADY_IS11, as there is no assignment to it. @W:CG360 : coreaxi.v(2409) | Removing wire AWID_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2410) | Removing wire AWADDR_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2411) | Removing wire AWLEN_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2412) | Removing wire AWSIZE_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2413) | Removing wire AWBURST_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2414) | Removing wire AWLOCK_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2415) | Removing wire AWCACHE_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2416) | Removing wire AWPROT_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2417) | Removing wire AWVALID_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2420) | Removing wire WID_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2421) | Removing wire WDATA_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2422) | Removing wire WSTRB_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2423) | Removing wire WLAST_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2424) | Removing wire WVALID_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2426) | Removing wire BREADY_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2428) | Removing wire ARID_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2429) | Removing wire ARADDR_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2430) | Removing wire ARLEN_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2431) | Removing wire ARSIZE_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2432) | Removing wire ARBURST_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2433) | Removing wire ARLOCK_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2434) | Removing wire ARCACHE_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2435) | Removing wire ARPROT_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2436) | Removing wire ARVALID_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2439) | Removing wire RREADY_IS12, as there is no assignment to it. @W:CG360 : coreaxi.v(2441) | Removing wire AWID_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2442) | Removing wire AWADDR_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2443) | Removing wire AWLEN_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2444) | Removing wire AWSIZE_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2445) | Removing wire AWBURST_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2446) | Removing wire AWLOCK_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2447) | Removing wire AWCACHE_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2448) | Removing wire AWPROT_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2449) | Removing wire AWVALID_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2452) | Removing wire WID_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2453) | Removing wire WDATA_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2454) | Removing wire WSTRB_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2455) | Removing wire WLAST_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2456) | Removing wire WVALID_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2458) | Removing wire BREADY_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2460) | Removing wire ARID_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2461) | Removing wire ARADDR_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2462) | Removing wire ARLEN_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2463) | Removing wire ARSIZE_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2464) | Removing wire ARBURST_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2465) | Removing wire ARLOCK_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2466) | Removing wire ARCACHE_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2467) | Removing wire ARPROT_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2468) | Removing wire ARVALID_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2471) | Removing wire RREADY_IS13, as there is no assignment to it. @W:CG360 : coreaxi.v(2473) | Removing wire AWID_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2474) | Removing wire AWADDR_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2475) | Removing wire AWLEN_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2476) | Removing wire AWSIZE_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2477) | Removing wire AWBURST_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2478) | Removing wire AWLOCK_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2479) | Removing wire AWCACHE_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2480) | Removing wire AWPROT_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2481) | Removing wire AWVALID_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2484) | Removing wire WID_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2485) | Removing wire WDATA_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2486) | Removing wire WSTRB_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2487) | Removing wire WLAST_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2488) | Removing wire WVALID_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2490) | Removing wire BREADY_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2492) | Removing wire ARID_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2493) | Removing wire ARADDR_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2494) | Removing wire ARLEN_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2495) | Removing wire ARSIZE_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2496) | Removing wire ARBURST_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2497) | Removing wire ARLOCK_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2498) | Removing wire ARCACHE_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2499) | Removing wire ARPROT_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2500) | Removing wire ARVALID_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2503) | Removing wire RREADY_IS14, as there is no assignment to it. @W:CG360 : coreaxi.v(2505) | Removing wire AWID_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2506) | Removing wire AWADDR_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2507) | Removing wire AWLEN_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2508) | Removing wire AWSIZE_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2509) | Removing wire AWBURST_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2510) | Removing wire AWLOCK_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2511) | Removing wire AWCACHE_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2512) | Removing wire AWPROT_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2513) | Removing wire AWVALID_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2516) | Removing wire WID_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2517) | Removing wire WDATA_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2518) | Removing wire WSTRB_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2519) | Removing wire WLAST_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2520) | Removing wire WVALID_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2522) | Removing wire BREADY_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2524) | Removing wire ARID_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2525) | Removing wire ARADDR_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2526) | Removing wire ARLEN_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2527) | Removing wire ARSIZE_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2528) | Removing wire ARBURST_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2529) | Removing wire ARLOCK_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2530) | Removing wire ARCACHE_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2531) | Removing wire ARPROT_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2532) | Removing wire ARVALID_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2535) | Removing wire RREADY_IS15, as there is no assignment to it. @W:CG360 : coreaxi.v(2537) | Removing wire AWID_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2538) | Removing wire AWADDR_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2539) | Removing wire AWLEN_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2540) | Removing wire AWSIZE_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2541) | Removing wire AWBURST_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2542) | Removing wire AWLOCK_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2543) | Removing wire AWCACHE_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2544) | Removing wire AWPROT_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2545) | Removing wire AWVALID_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2548) | Removing wire WID_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2549) | Removing wire WDATA_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2550) | Removing wire WSTRB_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2551) | Removing wire WLAST_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2552) | Removing wire WVALID_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2554) | Removing wire BREADY_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2556) | Removing wire ARID_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2557) | Removing wire ARADDR_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2558) | Removing wire ARLEN_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2559) | Removing wire ARSIZE_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2560) | Removing wire ARBURST_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2561) | Removing wire ARLOCK_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2562) | Removing wire ARCACHE_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2563) | Removing wire ARPROT_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2564) | Removing wire ARVALID_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2567) | Removing wire RREADY_IS16, as there is no assignment to it. @W:CG360 : coreaxi.v(2572) | Removing wire AWID_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2573) | Removing wire AWADDR_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2574) | Removing wire AWLEN_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2575) | Removing wire AWSIZE_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2576) | Removing wire AWBURST_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2577) | Removing wire AWLOCK_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2578) | Removing wire AWCACHE_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2579) | Removing wire AWPROT_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2580) | Removing wire AWVALID_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2582) | Removing wire WID_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2583) | Removing wire WDATA_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2584) | Removing wire WSTRB_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2585) | Removing wire WLAST_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2586) | Removing wire WVALID_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2588) | Removing wire ARID_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2589) | Removing wire ARADDR_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2590) | Removing wire ARLEN_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2591) | Removing wire ARSIZE_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2592) | Removing wire ARBURST_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2593) | Removing wire ARLOCK_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2594) | Removing wire ARCACHE_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2595) | Removing wire ARPROT_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2596) | Removing wire ARVALID_MI0, as there is no assignment to it. @W:CG360 : coreaxi.v(2598) | Removing wire BRESP_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2599) | Removing wire BID_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2601) | Removing wire RID_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2602) | Removing wire RDATA_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2603) | Removing wire RRESP_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2604) | Removing wire RVALID_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2605) | Removing wire RLAST_IM0, as there is no assignment to it. @W:CG360 : coreaxi.v(2610) | Removing wire AWID_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2611) | Removing wire AWADDR_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2612) | Removing wire AWLEN_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2613) | Removing wire AWSIZE_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2614) | Removing wire AWBURST_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2615) | Removing wire AWLOCK_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2616) | Removing wire AWCACHE_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2617) | Removing wire AWPROT_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2618) | Removing wire AWVALID_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2620) | Removing wire WID_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2621) | Removing wire WDATA_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2622) | Removing wire WSTRB_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2623) | Removing wire WLAST_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2624) | Removing wire WVALID_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2626) | Removing wire ARID_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2627) | Removing wire ARADDR_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2628) | Removing wire ARLEN_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2629) | Removing wire ARSIZE_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2630) | Removing wire ARBURST_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2631) | Removing wire ARLOCK_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2632) | Removing wire ARCACHE_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2633) | Removing wire ARPROT_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2634) | Removing wire ARVALID_MI1, as there is no assignment to it. @W:CG360 : coreaxi.v(2636) | Removing wire BRESP_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2637) | Removing wire BID_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2639) | Removing wire RID_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2640) | Removing wire RDATA_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2641) | Removing wire RRESP_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2642) | Removing wire RVALID_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2643) | Removing wire RLAST_IM1, as there is no assignment to it. @W:CG360 : coreaxi.v(2647) | Removing wire AWID_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2648) | Removing wire AWADDR_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2649) | Removing wire AWLEN_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2650) | Removing wire AWSIZE_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2651) | Removing wire AWBURST_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2652) | Removing wire AWLOCK_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2653) | Removing wire AWCACHE_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2654) | Removing wire AWPROT_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2655) | Removing wire AWVALID_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2657) | Removing wire WID_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2658) | Removing wire WDATA_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2659) | Removing wire WSTRB_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2660) | Removing wire WLAST_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2661) | Removing wire WVALID_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2663) | Removing wire ARID_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2664) | Removing wire ARADDR_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2665) | Removing wire ARLEN_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2666) | Removing wire ARSIZE_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2667) | Removing wire ARBURST_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2668) | Removing wire ARLOCK_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2669) | Removing wire ARCACHE_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2670) | Removing wire ARPROT_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2671) | Removing wire ARVALID_MI2, as there is no assignment to it. @W:CG360 : coreaxi.v(2673) | Removing wire BRESP_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2674) | Removing wire BID_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2676) | Removing wire RID_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2677) | Removing wire RDATA_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2678) | Removing wire RRESP_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2679) | Removing wire RVALID_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2680) | Removing wire RLAST_IM2, as there is no assignment to it. @W:CG360 : coreaxi.v(2684) | Removing wire AWID_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2685) | Removing wire AWADDR_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2686) | Removing wire AWLEN_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2687) | Removing wire AWSIZE_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2688) | Removing wire AWBURST_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2689) | Removing wire AWLOCK_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2690) | Removing wire AWCACHE_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2691) | Removing wire AWPROT_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2692) | Removing wire AWVALID_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2694) | Removing wire WID_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2695) | Removing wire WDATA_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2696) | Removing wire WSTRB_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2697) | Removing wire WLAST_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2698) | Removing wire WVALID_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2700) | Removing wire ARID_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2701) | Removing wire ARADDR_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2702) | Removing wire ARLEN_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2703) | Removing wire ARSIZE_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2704) | Removing wire ARBURST_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2705) | Removing wire ARLOCK_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2706) | Removing wire ARCACHE_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2707) | Removing wire ARPROT_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2708) | Removing wire ARVALID_MI3, as there is no assignment to it. @W:CG360 : coreaxi.v(2710) | Removing wire BRESP_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2711) | Removing wire BID_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2713) | Removing wire RID_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2714) | Removing wire RDATA_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2715) | Removing wire RRESP_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2716) | Removing wire RVALID_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(2717) | Removing wire RLAST_IM3, as there is no assignment to it. @W:CG360 : coreaxi.v(3263) | Removing wire AWREADY_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3264) | Removing wire AWREADY_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3265) | Removing wire AWREADY_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3266) | Removing wire AWREADY_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3267) | Removing wire AWREADY_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3268) | Removing wire AWREADY_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3269) | Removing wire AWREADY_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3270) | Removing wire AWREADY_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3271) | Removing wire AWREADY_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3272) | Removing wire AWREADY_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3273) | Removing wire AWREADY_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3274) | Removing wire AWREADY_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3275) | Removing wire AWREADY_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3276) | Removing wire AWREADY_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3277) | Removing wire AWREADY_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3278) | Removing wire AWREADY_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3279) | Removing wire AWREADY_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3281) | Removing wire WREADY_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3282) | Removing wire WREADY_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3283) | Removing wire WREADY_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3284) | Removing wire WREADY_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3285) | Removing wire WREADY_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3286) | Removing wire WREADY_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3287) | Removing wire WREADY_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3288) | Removing wire WREADY_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3289) | Removing wire WREADY_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3290) | Removing wire WREADY_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3291) | Removing wire WREADY_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3292) | Removing wire WREADY_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3293) | Removing wire WREADY_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3294) | Removing wire WREADY_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3295) | Removing wire WREADY_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3296) | Removing wire WREADY_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3297) | Removing wire WREADY_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3299) | Removing wire ARREADY_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3300) | Removing wire ARREADY_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3301) | Removing wire ARREADY_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3302) | Removing wire ARREADY_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3303) | Removing wire ARREADY_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3304) | Removing wire ARREADY_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3305) | Removing wire ARREADY_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3306) | Removing wire ARREADY_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3307) | Removing wire ARREADY_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3308) | Removing wire ARREADY_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3309) | Removing wire ARREADY_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3310) | Removing wire ARREADY_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3311) | Removing wire ARREADY_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3312) | Removing wire ARREADY_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3313) | Removing wire ARREADY_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3314) | Removing wire ARREADY_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3315) | Removing wire ARREADY_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3388) | Removing wire BID_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3389) | Removing wire BRESP_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3390) | Removing wire BVALID_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3391) | Removing wire RID_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3392) | Removing wire RDATA_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3393) | Removing wire RRESP_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3394) | Removing wire RLAST_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3395) | Removing wire RVALID_SI0, as there is no assignment to it. @W:CG360 : coreaxi.v(3397) | Removing wire BID_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3398) | Removing wire BRESP_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3399) | Removing wire BVALID_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3400) | Removing wire RID_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3401) | Removing wire RDATA_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3402) | Removing wire RRESP_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3403) | Removing wire RLAST_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3404) | Removing wire RVALID_SI1, as there is no assignment to it. @W:CG360 : coreaxi.v(3406) | Removing wire BID_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3407) | Removing wire BRESP_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3408) | Removing wire BVALID_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3409) | Removing wire RID_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3410) | Removing wire RDATA_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3411) | Removing wire RRESP_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3412) | Removing wire RLAST_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3413) | Removing wire RVALID_SI2, as there is no assignment to it. @W:CG360 : coreaxi.v(3415) | Removing wire BID_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3416) | Removing wire BRESP_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3417) | Removing wire BVALID_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3418) | Removing wire RID_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3419) | Removing wire RDATA_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3420) | Removing wire RRESP_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3421) | Removing wire RLAST_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3422) | Removing wire RVALID_SI3, as there is no assignment to it. @W:CG360 : coreaxi.v(3424) | Removing wire BID_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3425) | Removing wire BRESP_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3426) | Removing wire BVALID_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3427) | Removing wire RID_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3428) | Removing wire RDATA_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3429) | Removing wire RRESP_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3430) | Removing wire RLAST_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3431) | Removing wire RVALID_SI4, as there is no assignment to it. @W:CG360 : coreaxi.v(3433) | Removing wire BID_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3434) | Removing wire BRESP_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3435) | Removing wire BVALID_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3436) | Removing wire RID_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3437) | Removing wire RDATA_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3438) | Removing wire RRESP_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3439) | Removing wire RLAST_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3440) | Removing wire RVALID_SI5, as there is no assignment to it. @W:CG360 : coreaxi.v(3442) | Removing wire BID_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3443) | Removing wire BRESP_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3444) | Removing wire BVALID_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3445) | Removing wire RID_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3446) | Removing wire RDATA_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3447) | Removing wire RRESP_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3448) | Removing wire RLAST_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3449) | Removing wire RVALID_SI6, as there is no assignment to it. @W:CG360 : coreaxi.v(3451) | Removing wire BID_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3452) | Removing wire BRESP_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3453) | Removing wire BVALID_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3454) | Removing wire RID_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3455) | Removing wire RDATA_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3456) | Removing wire RRESP_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3457) | Removing wire RLAST_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3458) | Removing wire RVALID_SI7, as there is no assignment to it. @W:CG360 : coreaxi.v(3460) | Removing wire BID_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3461) | Removing wire BRESP_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3462) | Removing wire BVALID_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3463) | Removing wire RID_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3464) | Removing wire RDATA_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3465) | Removing wire RRESP_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3466) | Removing wire RLAST_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3467) | Removing wire RVALID_SI8, as there is no assignment to it. @W:CG360 : coreaxi.v(3469) | Removing wire BID_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3470) | Removing wire BRESP_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3471) | Removing wire BVALID_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3472) | Removing wire RID_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3473) | Removing wire RDATA_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3474) | Removing wire RRESP_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3475) | Removing wire RLAST_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3476) | Removing wire RVALID_SI9, as there is no assignment to it. @W:CG360 : coreaxi.v(3478) | Removing wire BID_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3479) | Removing wire BRESP_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3480) | Removing wire BVALID_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3481) | Removing wire RID_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3482) | Removing wire RDATA_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3483) | Removing wire RRESP_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3484) | Removing wire RLAST_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3485) | Removing wire RVALID_SI10, as there is no assignment to it. @W:CG360 : coreaxi.v(3487) | Removing wire BID_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3488) | Removing wire BRESP_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3489) | Removing wire BVALID_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3490) | Removing wire RID_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3491) | Removing wire RDATA_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3492) | Removing wire RRESP_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3493) | Removing wire RLAST_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3494) | Removing wire RVALID_SI11, as there is no assignment to it. @W:CG360 : coreaxi.v(3496) | Removing wire BID_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3497) | Removing wire BRESP_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3498) | Removing wire BVALID_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3499) | Removing wire RID_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3500) | Removing wire RDATA_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3501) | Removing wire RRESP_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3502) | Removing wire RLAST_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3503) | Removing wire RVALID_SI12, as there is no assignment to it. @W:CG360 : coreaxi.v(3505) | Removing wire BID_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3506) | Removing wire BRESP_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3507) | Removing wire BVALID_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3508) | Removing wire RID_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3509) | Removing wire RDATA_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3510) | Removing wire RRESP_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3511) | Removing wire RLAST_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3512) | Removing wire RVALID_SI13, as there is no assignment to it. @W:CG360 : coreaxi.v(3514) | Removing wire BID_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3515) | Removing wire BRESP_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3516) | Removing wire BVALID_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3517) | Removing wire RID_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3518) | Removing wire RDATA_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3519) | Removing wire RRESP_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3520) | Removing wire RLAST_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3521) | Removing wire RVALID_SI14, as there is no assignment to it. @W:CG360 : coreaxi.v(3523) | Removing wire BID_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3524) | Removing wire BRESP_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3525) | Removing wire BVALID_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3526) | Removing wire RID_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3527) | Removing wire RDATA_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3528) | Removing wire RRESP_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3529) | Removing wire RLAST_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3530) | Removing wire RVALID_SI15, as there is no assignment to it. @W:CG360 : coreaxi.v(3532) | Removing wire BID_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3533) | Removing wire BRESP_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3534) | Removing wire BVALID_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3535) | Removing wire RID_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3536) | Removing wire RDATA_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3537) | Removing wire RRESP_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3538) | Removing wire RLAST_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3539) | Removing wire RVALID_SI16, as there is no assignment to it. @W:CG360 : coreaxi.v(3542) | Removing wire BID_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3543) | Removing wire BRESP_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3544) | Removing wire BVALID_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3545) | Removing wire RID_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3546) | Removing wire RDATA_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3547) | Removing wire RRESP_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3548) | Removing wire RLAST_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3549) | Removing wire RVALID_IM, as there is no assignment to it. @W:CG360 : coreaxi.v(3551) | Removing wire m0_rd_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3552) | Removing wire m1_rd_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3553) | Removing wire m2_rd_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3554) | Removing wire m3_rd_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3555) | Removing wire m0_wr_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3556) | Removing wire m1_wr_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3557) | Removing wire m2_wr_end, as there is no assignment to it. @W:CG360 : coreaxi.v(3558) | Removing wire m3_wr_end, as there is no assignment to it. @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z5 @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z6 @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : MDDR_Demo_sb_FABOSC_0_OSC.v(5) | Synthesizing module MDDR_Demo_sb_FABOSC_0_OSC in library work. @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work. @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF in library work. @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. @N:CG364 : MDDR_Demo_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. @N:CG364 : MDDR_Demo_sb_MSS.v(9) | Synthesizing module MDDR_Demo_sb_MSS in library work. @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : MDDR_Demo_sb.v(9) | Synthesizing module MDDR_Demo_sb in library work. @N:CG364 : MDDR_Demo.v(9) | Synthesizing module MDDR_Demo in library work. @N:CG364 : MDDR_Demo_top.v(9) | Synthesizing module MDDR_Demo_top in library work. @N:CG364 : DATA_HANDLE_FSM.v(22) | Synthesizing module DATAHANDLE_FSM in library work. DATA_WIDTH=32'b00000000000000000000000000100000 ADDR_WIDTH=32'b00000000000000000000000000100000 Generated name = DATAHANDLE_FSM_32s_32s @W:CG296 : DATA_HANDLE_FSM.v(74) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(78) | Referenced variable user_option is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(84) | Referenced variable user_address is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(90) | Referenced variable user_data1 is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(96) | Referenced variable user_data2 is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(104) | Referenced variable ram_rdata is not in sensitivity list. @W:CG133 : DATA_HANDLE_FSM.v(63) | Object SEL is declared but not assigned. Either assign a value or remove the declaration. @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. @N:CG364 : UART_IF_TPSRAM_0_TPSRAM.v(5) | Synthesizing module UART_IF_TPSRAM_0_TPSRAM in library work. @N:CG364 : UART_IF_FSM.v(20) | Synthesizing module UART_IF_FSM in library work. @N:CG179 : UART_IF_FSM.v(237) | Removing redundant assignment. @N:CG179 : UART_IF_FSM.v(244) | Removing redundant assignment. @N:CG364 : UART_IF.v(9) | Synthesizing module UART_IF in library work. @N:CG364 : SF2_MDDR_Demo.v(9) | Synthesizing module SF2_MDDR_Demo in library work. @N:CL201 : UART_IF_FSM.v(102) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 12 reachable states with original encodings of: 000000 000001 000010 000100 000101 000111 001000 001010 001011 001100 001101 001110 @W:CL279 : UART_IF_FSM.v(102) | Pruning register bits 3 to 1 of RLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL279 : UART_IF_FSM.v(102) | Pruning register bits 3 to 1 of WLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CL201 : DATA_HANDLE_FSM.v(110) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : DATA_HANDLE_FSM.v(49) | Input port bits 31 to 13 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : DATA_HANDLE_FSM.v(49) | Input port bits 1 to 0 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : DATA_HANDLE_FSM.v(48) | Input PENABLE is unused. @W:CL157 : MDDR_Demo_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : MDDR_Demo_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : MDDR_Demo_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : MDDR_Demo_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : MDDR_Demo_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused. @N:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused. @W:CL246 : axi_feedthrough.v(310) | Input port bits 5 to 4 of BID_S0[5:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : axi_feedthrough.v(326) | Input port bits 5 to 4 of RID_S0[5:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : axi_feedthrough.v(243) | Input ACLK is unused. @N:CL159 : axi_feedthrough.v(244) | Input ARESETN is unused. @W:CL157 : coreaxi.v(1144) | *Output AWREADY_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1151) | *Output WREADY_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1153) | *Output BID_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1154) | *Output BRESP_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1155) | *Output BVALID_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1167) | *Output ARREADY_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1169) | *Output RID_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1170) | *Output RDATA_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1171) | *Output RRESP_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1172) | *Output RLAST_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1173) | *Output RVALID_M1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1187) | *Output AWREADY_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1194) | *Output WREADY_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1196) | *Output BID_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1197) | *Output BRESP_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1198) | *Output BVALID_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1210) | *Output ARREADY_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1212) | *Output RID_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1213) | *Output RDATA_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1214) | *Output RRESP_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1215) | *Output RLAST_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1216) | *Output RVALID_M2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1230) | *Output AWREADY_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1237) | *Output WREADY_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1239) | *Output BID_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1240) | *Output BRESP_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1241) | *Output BVALID_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1253) | *Output ARREADY_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1255) | *Output RID_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1256) | *Output RDATA_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1257) | *Output RRESP_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1258) | *Output RLAST_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1259) | *Output RVALID_M3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1307) | *Output AWID_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1308) | *Output AWADDR_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1309) | *Output AWLEN_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1310) | *Output AWSIZE_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1311) | *Output AWBURST_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1312) | *Output AWLOCK_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1313) | *Output AWCACHE_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1314) | *Output AWPROT_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1315) | *Output AWVALID_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1318) | *Output WID_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1319) | *Output WDATA_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1320) | *Output WSTRB_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1321) | *Output WLAST_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1322) | *Output WVALID_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1328) | *Output BREADY_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1330) | *Output ARID_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1331) | *Output ARADDR_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1332) | *Output ARLEN_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1333) | *Output ARSIZE_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1334) | *Output ARBURST_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1335) | *Output ARLOCK_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1336) | *Output ARCACHE_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1337) | *Output ARPROT_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1338) | *Output ARVALID_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1346) | *Output RREADY_S1 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1350) | *Output AWID_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1351) | *Output AWADDR_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1352) | *Output AWLEN_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1353) | *Output AWSIZE_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1354) | *Output AWBURST_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1355) | *Output AWLOCK_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1356) | *Output AWCACHE_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1357) | *Output AWPROT_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1358) | *Output AWVALID_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1361) | *Output WID_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1362) | *Output WDATA_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1363) | *Output WSTRB_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1364) | *Output WLAST_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1365) | *Output WVALID_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1371) | *Output BREADY_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1373) | *Output ARID_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1374) | *Output ARADDR_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1375) | *Output ARLEN_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1376) | *Output ARSIZE_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1377) | *Output ARBURST_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1378) | *Output ARLOCK_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1379) | *Output ARCACHE_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1380) | *Output ARPROT_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1381) | *Output ARVALID_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1389) | *Output RREADY_S2 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1393) | *Output AWID_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1394) | *Output AWADDR_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1395) | *Output AWLEN_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1396) | *Output AWSIZE_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1397) | *Output AWBURST_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1398) | *Output AWLOCK_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1399) | *Output AWCACHE_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1400) | *Output AWPROT_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1401) | *Output AWVALID_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1404) | *Output WID_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1405) | *Output WDATA_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1406) | *Output WSTRB_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1407) | *Output WLAST_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1408) | *Output WVALID_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1414) | *Output BREADY_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1416) | *Output ARID_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1417) | *Output ARADDR_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1418) | *Output ARLEN_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1419) | *Output ARSIZE_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1420) | *Output ARBURST_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1421) | *Output ARLOCK_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1422) | *Output ARCACHE_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1423) | *Output ARPROT_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1424) | *Output ARVALID_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1432) | *Output RREADY_S3 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1436) | *Output AWID_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1437) | *Output AWADDR_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1438) | *Output AWLEN_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1439) | *Output AWSIZE_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1440) | *Output AWBURST_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1441) | *Output AWLOCK_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1442) | *Output AWCACHE_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1443) | *Output AWPROT_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1444) | *Output AWVALID_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1447) | *Output WID_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1448) | *Output WDATA_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1449) | *Output WSTRB_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1450) | *Output WLAST_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1451) | *Output WVALID_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1457) | *Output BREADY_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1459) | *Output ARID_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1460) | *Output ARADDR_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1461) | *Output ARLEN_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1462) | *Output ARSIZE_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1463) | *Output ARBURST_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1464) | *Output ARLOCK_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1465) | *Output ARCACHE_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1466) | *Output ARPROT_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1467) | *Output ARVALID_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1475) | *Output RREADY_S4 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1479) | *Output AWID_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1480) | *Output AWADDR_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1481) | *Output AWLEN_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1482) | *Output AWSIZE_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1483) | *Output AWBURST_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1484) | *Output AWLOCK_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1485) | *Output AWCACHE_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1486) | *Output AWPROT_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1487) | *Output AWVALID_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1490) | *Output WID_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1491) | *Output WDATA_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1492) | *Output WSTRB_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1493) | *Output WLAST_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1494) | *Output WVALID_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1500) | *Output BREADY_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1502) | *Output ARID_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1503) | *Output ARADDR_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1504) | *Output ARLEN_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1505) | *Output ARSIZE_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1506) | *Output ARBURST_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1507) | *Output ARLOCK_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1508) | *Output ARCACHE_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1509) | *Output ARPROT_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1510) | *Output ARVALID_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1518) | *Output RREADY_S5 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1522) | *Output AWID_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1523) | *Output AWADDR_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1524) | *Output AWLEN_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1525) | *Output AWSIZE_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1526) | *Output AWBURST_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1527) | *Output AWLOCK_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1528) | *Output AWCACHE_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1529) | *Output AWPROT_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1530) | *Output AWVALID_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1533) | *Output WID_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1534) | *Output WDATA_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1535) | *Output WSTRB_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1536) | *Output WLAST_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1537) | *Output WVALID_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1543) | *Output BREADY_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1545) | *Output ARID_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1546) | *Output ARADDR_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1547) | *Output ARLEN_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1548) | *Output ARSIZE_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1549) | *Output ARBURST_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1550) | *Output ARLOCK_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1551) | *Output ARCACHE_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1552) | *Output ARPROT_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1553) | *Output ARVALID_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1561) | *Output RREADY_S6 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1565) | *Output AWID_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1566) | *Output AWADDR_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1567) | *Output AWLEN_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1568) | *Output AWSIZE_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1569) | *Output AWBURST_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1570) | *Output AWLOCK_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1571) | *Output AWCACHE_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1572) | *Output AWPROT_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1573) | *Output AWVALID_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1576) | *Output WID_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1577) | *Output WDATA_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1578) | *Output WSTRB_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1579) | *Output WLAST_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1580) | *Output WVALID_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1586) | *Output BREADY_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1588) | *Output ARID_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1589) | *Output ARADDR_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1590) | *Output ARLEN_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1591) | *Output ARSIZE_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1592) | *Output ARBURST_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1593) | *Output ARLOCK_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1594) | *Output ARCACHE_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1595) | *Output ARPROT_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1596) | *Output ARVALID_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1604) | *Output RREADY_S7 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1608) | *Output AWID_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1609) | *Output AWADDR_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1610) | *Output AWLEN_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1611) | *Output AWSIZE_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1612) | *Output AWBURST_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1613) | *Output AWLOCK_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1614) | *Output AWCACHE_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1615) | *Output AWPROT_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1616) | *Output AWVALID_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1619) | *Output WID_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1620) | *Output WDATA_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1621) | *Output WSTRB_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1622) | *Output WLAST_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1623) | *Output WVALID_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1629) | *Output BREADY_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1631) | *Output ARID_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1632) | *Output ARADDR_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1633) | *Output ARLEN_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1634) | *Output ARSIZE_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1635) | *Output ARBURST_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1636) | *Output ARLOCK_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1637) | *Output ARCACHE_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1638) | *Output ARPROT_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1639) | *Output ARVALID_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1647) | *Output RREADY_S8 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1651) | *Output AWID_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1652) | *Output AWADDR_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1653) | *Output AWLEN_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1654) | *Output AWSIZE_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1655) | *Output AWBURST_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1656) | *Output AWLOCK_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1657) | *Output AWCACHE_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1658) | *Output AWPROT_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1659) | *Output AWVALID_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1662) | *Output WID_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1663) | *Output WDATA_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1664) | *Output WSTRB_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1665) | *Output WLAST_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1666) | *Output WVALID_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1672) | *Output BREADY_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1674) | *Output ARID_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1675) | *Output ARADDR_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1676) | *Output ARLEN_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1677) | *Output ARSIZE_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1678) | *Output ARBURST_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1679) | *Output ARLOCK_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1680) | *Output ARCACHE_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1681) | *Output ARPROT_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1682) | *Output ARVALID_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1690) | *Output RREADY_S9 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1694) | *Output AWID_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1695) | *Output AWADDR_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1696) | *Output AWLEN_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1697) | *Output AWSIZE_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1698) | *Output AWBURST_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1699) | *Output AWLOCK_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1700) | *Output AWCACHE_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1701) | *Output AWPROT_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1702) | *Output AWVALID_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1705) | *Output WID_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1706) | *Output WDATA_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1707) | *Output WSTRB_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1708) | *Output WLAST_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1709) | *Output WVALID_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1715) | *Output BREADY_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1717) | *Output ARID_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1718) | *Output ARADDR_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1719) | *Output ARLEN_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1720) | *Output ARSIZE_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1721) | *Output ARBURST_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1722) | *Output ARLOCK_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1723) | *Output ARCACHE_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1724) | *Output ARPROT_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1725) | *Output ARVALID_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1733) | *Output RREADY_S10 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1737) | *Output AWID_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1738) | *Output AWADDR_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1739) | *Output AWLEN_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1740) | *Output AWSIZE_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1741) | *Output AWBURST_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1742) | *Output AWLOCK_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1743) | *Output AWCACHE_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1744) | *Output AWPROT_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1745) | *Output AWVALID_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1748) | *Output WID_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1749) | *Output WDATA_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1750) | *Output WSTRB_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1751) | *Output WLAST_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1752) | *Output WVALID_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1758) | *Output BREADY_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1760) | *Output ARID_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1761) | *Output ARADDR_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1762) | *Output ARLEN_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1763) | *Output ARSIZE_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1764) | *Output ARBURST_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1765) | *Output ARLOCK_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1766) | *Output ARCACHE_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1767) | *Output ARPROT_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1768) | *Output ARVALID_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1776) | *Output RREADY_S11 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1780) | *Output AWID_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1781) | *Output AWADDR_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1782) | *Output AWLEN_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1783) | *Output AWSIZE_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1784) | *Output AWBURST_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1785) | *Output AWLOCK_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1786) | *Output AWCACHE_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1787) | *Output AWPROT_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1788) | *Output AWVALID_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1791) | *Output WID_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1792) | *Output WDATA_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1793) | *Output WSTRB_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1794) | *Output WLAST_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1795) | *Output WVALID_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1801) | *Output BREADY_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1803) | *Output ARID_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1804) | *Output ARADDR_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1805) | *Output ARLEN_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1806) | *Output ARSIZE_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1807) | *Output ARBURST_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1808) | *Output ARLOCK_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1809) | *Output ARCACHE_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1810) | *Output ARPROT_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1811) | *Output ARVALID_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1819) | *Output RREADY_S12 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1823) | *Output AWID_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1824) | *Output AWADDR_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1825) | *Output AWLEN_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1826) | *Output AWSIZE_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1827) | *Output AWBURST_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1828) | *Output AWLOCK_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1829) | *Output AWCACHE_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1830) | *Output AWPROT_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1831) | *Output AWVALID_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1834) | *Output WID_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1835) | *Output WDATA_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1836) | *Output WSTRB_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1837) | *Output WLAST_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1838) | *Output WVALID_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1844) | *Output BREADY_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1846) | *Output ARID_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1847) | *Output ARADDR_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1848) | *Output ARLEN_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1849) | *Output ARSIZE_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1850) | *Output ARBURST_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1851) | *Output ARLOCK_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1852) | *Output ARCACHE_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1853) | *Output ARPROT_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1854) | *Output ARVALID_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1862) | *Output RREADY_S13 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1866) | *Output AWID_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1867) | *Output AWADDR_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1868) | *Output AWLEN_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1869) | *Output AWSIZE_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1870) | *Output AWBURST_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1871) | *Output AWLOCK_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1872) | *Output AWCACHE_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1873) | *Output AWPROT_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1874) | *Output AWVALID_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1877) | *Output WID_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1878) | *Output WDATA_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1879) | *Output WSTRB_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1880) | *Output WLAST_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1881) | *Output WVALID_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1887) | *Output BREADY_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1889) | *Output ARID_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1890) | *Output ARADDR_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1891) | *Output ARLEN_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1892) | *Output ARSIZE_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1893) | *Output ARBURST_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1894) | *Output ARLOCK_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1895) | *Output ARCACHE_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1896) | *Output ARPROT_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1897) | *Output ARVALID_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1905) | *Output RREADY_S14 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1909) | *Output AWID_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1910) | *Output AWADDR_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1911) | *Output AWLEN_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1912) | *Output AWSIZE_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1913) | *Output AWBURST_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1914) | *Output AWLOCK_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1915) | *Output AWCACHE_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1916) | *Output AWPROT_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1917) | *Output AWVALID_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1920) | *Output WID_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1921) | *Output WDATA_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1922) | *Output WSTRB_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1923) | *Output WLAST_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1924) | *Output WVALID_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1930) | *Output BREADY_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1932) | *Output ARID_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1933) | *Output ARADDR_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1934) | *Output ARLEN_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1935) | *Output ARSIZE_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1936) | *Output ARBURST_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1937) | *Output ARLOCK_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1938) | *Output ARCACHE_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1939) | *Output ARPROT_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1940) | *Output ARVALID_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1948) | *Output RREADY_S15 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1952) | *Output AWID_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1953) | *Output AWADDR_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1954) | *Output AWLEN_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1955) | *Output AWSIZE_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1956) | *Output AWBURST_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1957) | *Output AWLOCK_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1958) | *Output AWCACHE_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1959) | *Output AWPROT_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1960) | *Output AWVALID_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1963) | *Output WID_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1964) | *Output WDATA_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1965) | *Output WSTRB_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1966) | *Output WLAST_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1967) | *Output WVALID_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1973) | *Output BREADY_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1975) | *Output ARID_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1976) | *Output ARADDR_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1977) | *Output ARLEN_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1978) | *Output ARSIZE_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1979) | *Output ARBURST_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1980) | *Output ARLOCK_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1981) | *Output ARCACHE_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1982) | *Output ARPROT_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1983) | *Output ARVALID_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : coreaxi.v(1991) | *Output RREADY_S16 has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : coreaxi.v(1135) | Input AWID_M1 is unused. @N:CL159 : coreaxi.v(1136) | Input AWADDR_M1 is unused. @N:CL159 : coreaxi.v(1137) | Input AWLEN_M1 is unused. @N:CL159 : coreaxi.v(1138) | Input AWSIZE_M1 is unused. @N:CL159 : coreaxi.v(1139) | Input AWBURST_M1 is unused. @N:CL159 : coreaxi.v(1140) | Input AWLOCK_M1 is unused. @N:CL159 : coreaxi.v(1141) | Input AWCACHE_M1 is unused. @N:CL159 : coreaxi.v(1142) | Input AWPROT_M1 is unused. @N:CL159 : coreaxi.v(1143) | Input AWVALID_M1 is unused. @N:CL159 : coreaxi.v(1146) | Input WID_M1 is unused. @N:CL159 : coreaxi.v(1147) | Input WDATA_M1 is unused. @N:CL159 : coreaxi.v(1148) | Input WSTRB_M1 is unused. @N:CL159 : coreaxi.v(1149) | Input WLAST_M1 is unused. @N:CL159 : coreaxi.v(1150) | Input WVALID_M1 is unused. @N:CL159 : coreaxi.v(1156) | Input BREADY_M1 is unused. @N:CL159 : coreaxi.v(1158) | Input ARID_M1 is unused. @N:CL159 : coreaxi.v(1159) | Input ARADDR_M1 is unused. @N:CL159 : coreaxi.v(1160) | Input ARLEN_M1 is unused. @N:CL159 : coreaxi.v(1161) | Input ARSIZE_M1 is unused. @N:CL159 : coreaxi.v(1162) | Input ARBURST_M1 is unused. @N:CL159 : coreaxi.v(1163) | Input ARLOCK_M1 is unused. @N:CL159 : coreaxi.v(1164) | Input ARCACHE_M1 is unused. @N:CL159 : coreaxi.v(1165) | Input ARPROT_M1 is unused. @N:CL159 : coreaxi.v(1166) | Input ARVALID_M1 is unused. @N:CL159 : coreaxi.v(1174) | Input RREADY_M1 is unused. @N:CL159 : coreaxi.v(1178) | Input AWID_M2 is unused. @N:CL159 : coreaxi.v(1179) | Input AWADDR_M2 is unused. @N:CL159 : coreaxi.v(1180) | Input AWLEN_M2 is unused. @N:CL159 : coreaxi.v(1181) | Input AWSIZE_M2 is unused. @N:CL159 : coreaxi.v(1182) | Input AWBURST_M2 is unused. @N:CL159 : coreaxi.v(1183) | Input AWLOCK_M2 is unused. @N:CL159 : coreaxi.v(1184) | Input AWCACHE_M2 is unused. @N:CL159 : coreaxi.v(1185) | Input AWPROT_M2 is unused. @N:CL159 : coreaxi.v(1186) | Input AWVALID_M2 is unused. @N:CL159 : coreaxi.v(1189) | Input WID_M2 is unused. @N:CL159 : coreaxi.v(1190) | Input WDATA_M2 is unused. @N:CL159 : coreaxi.v(1191) | Input WSTRB_M2 is unused. @N:CL159 : coreaxi.v(1192) | Input WLAST_M2 is unused. @N:CL159 : coreaxi.v(1193) | Input WVALID_M2 is unused. @N:CL159 : coreaxi.v(1199) | Input BREADY_M2 is unused. @N:CL159 : coreaxi.v(1201) | Input ARID_M2 is unused. @N:CL159 : coreaxi.v(1202) | Input ARADDR_M2 is unused. @N:CL159 : coreaxi.v(1203) | Input ARLEN_M2 is unused. @N:CL159 : coreaxi.v(1204) | Input ARSIZE_M2 is unused. @N:CL159 : coreaxi.v(1205) | Input ARBURST_M2 is unused. @N:CL159 : coreaxi.v(1206) | Input ARLOCK_M2 is unused. @N:CL159 : coreaxi.v(1207) | Input ARCACHE_M2 is unused. @N:CL159 : coreaxi.v(1208) | Input ARPROT_M2 is unused. @N:CL159 : coreaxi.v(1209) | Input ARVALID_M2 is unused. @N:CL159 : coreaxi.v(1217) | Input RREADY_M2 is unused. @N:CL159 : coreaxi.v(1221) | Input AWID_M3 is unused. @N:CL159 : coreaxi.v(1222) | Input AWADDR_M3 is unused. @N:CL159 : coreaxi.v(1223) | Input AWLEN_M3 is unused. @N:CL159 : coreaxi.v(1224) | Input AWSIZE_M3 is unused. @N:CL159 : coreaxi.v(1225) | Input AWBURST_M3 is unused. @N:CL159 : coreaxi.v(1226) | Input AWLOCK_M3 is unused. @N:CL159 : coreaxi.v(1227) | Input AWCACHE_M3 is unused. @N:CL159 : coreaxi.v(1228) | Input AWPROT_M3 is unused. @N:CL159 : coreaxi.v(1229) | Input AWVALID_M3 is unused. @N:CL159 : coreaxi.v(1232) | Input WID_M3 is unused. @N:CL159 : coreaxi.v(1233) | Input WDATA_M3 is unused. @N:CL159 : coreaxi.v(1234) | Input WSTRB_M3 is unused. @N:CL159 : coreaxi.v(1235) | Input WLAST_M3 is unused. @N:CL159 : coreaxi.v(1236) | Input WVALID_M3 is unused. @N:CL159 : coreaxi.v(1242) | Input BREADY_M3 is unused. @N:CL159 : coreaxi.v(1244) | Input ARID_M3 is unused. @N:CL159 : coreaxi.v(1245) | Input ARADDR_M3 is unused. @N:CL159 : coreaxi.v(1246) | Input ARLEN_M3 is unused. @N:CL159 : coreaxi.v(1247) | Input ARSIZE_M3 is unused. @N:CL159 : coreaxi.v(1248) | Input ARBURST_M3 is unused. @N:CL159 : coreaxi.v(1249) | Input ARLOCK_M3 is unused. @N:CL159 : coreaxi.v(1250) | Input ARCACHE_M3 is unused. @N:CL159 : coreaxi.v(1251) | Input ARPROT_M3 is unused. @N:CL159 : coreaxi.v(1252) | Input ARVALID_M3 is unused. @N:CL159 : coreaxi.v(1260) | Input RREADY_M3 is unused. @N:CL159 : coreaxi.v(1316) | Input AWREADY_S1 is unused. @N:CL159 : coreaxi.v(1323) | Input WREADY_S1 is unused. @N:CL159 : coreaxi.v(1325) | Input BID_S1 is unused. @N:CL159 : coreaxi.v(1326) | Input BRESP_S1 is unused. @N:CL159 : coreaxi.v(1327) | Input BVALID_S1 is unused. @N:CL159 : coreaxi.v(1339) | Input ARREADY_S1 is unused. @N:CL159 : coreaxi.v(1341) | Input RID_S1 is unused. @N:CL159 : coreaxi.v(1342) | Input RDATA_S1 is unused. @N:CL159 : coreaxi.v(1343) | Input RRESP_S1 is unused. @N:CL159 : coreaxi.v(1344) | Input RLAST_S1 is unused. @N:CL159 : coreaxi.v(1345) | Input RVALID_S1 is unused. @N:CL159 : coreaxi.v(1359) | Input AWREADY_S2 is unused. @N:CL159 : coreaxi.v(1366) | Input WREADY_S2 is unused. @N:CL159 : coreaxi.v(1368) | Input BID_S2 is unused. @N:CL159 : coreaxi.v(1369) | Input BRESP_S2 is unused. @N:CL159 : coreaxi.v(1370) | Input BVALID_S2 is unused. @N:CL159 : coreaxi.v(1382) | Input ARREADY_S2 is unused. @N:CL159 : coreaxi.v(1384) | Input RID_S2 is unused. @N:CL159 : coreaxi.v(1385) | Input RDATA_S2 is unused. @N:CL159 : coreaxi.v(1386) | Input RRESP_S2 is unused. @N:CL159 : coreaxi.v(1387) | Input RLAST_S2 is unused. @N:CL159 : coreaxi.v(1388) | Input RVALID_S2 is unused. @N:CL159 : coreaxi.v(1402) | Input AWREADY_S3 is unused. @N:CL159 : coreaxi.v(1409) | Input WREADY_S3 is unused. @N:CL159 : coreaxi.v(1411) | Input BID_S3 is unused. @N:CL159 : coreaxi.v(1412) | Input BRESP_S3 is unused. @N:CL159 : coreaxi.v(1413) | Input BVALID_S3 is unused. @N:CL159 : coreaxi.v(1425) | Input ARREADY_S3 is unused. @N:CL159 : coreaxi.v(1427) | Input RID_S3 is unused. @N:CL159 : coreaxi.v(1428) | Input RDATA_S3 is unused. @N:CL159 : coreaxi.v(1429) | Input RRESP_S3 is unused. @N:CL159 : coreaxi.v(1430) | Input RLAST_S3 is unused. @N:CL159 : coreaxi.v(1431) | Input RVALID_S3 is unused. @N:CL159 : coreaxi.v(1445) | Input AWREADY_S4 is unused. @N:CL159 : coreaxi.v(1452) | Input WREADY_S4 is unused. @N:CL159 : coreaxi.v(1454) | Input BID_S4 is unused. @N:CL159 : coreaxi.v(1455) | Input BRESP_S4 is unused. @N:CL159 : coreaxi.v(1456) | Input BVALID_S4 is unused. @N:CL159 : coreaxi.v(1468) | Input ARREADY_S4 is unused. @N:CL159 : coreaxi.v(1470) | Input RID_S4 is unused. @N:CL159 : coreaxi.v(1471) | Input RDATA_S4 is unused. @N:CL159 : coreaxi.v(1472) | Input RRESP_S4 is unused. @N:CL159 : coreaxi.v(1473) | Input RLAST_S4 is unused. @N:CL159 : coreaxi.v(1474) | Input RVALID_S4 is unused. @N:CL159 : coreaxi.v(1488) | Input AWREADY_S5 is unused. @N:CL159 : coreaxi.v(1495) | Input WREADY_S5 is unused. @N:CL159 : coreaxi.v(1497) | Input BID_S5 is unused. @N:CL159 : coreaxi.v(1498) | Input BRESP_S5 is unused. @N:CL159 : coreaxi.v(1499) | Input BVALID_S5 is unused. @N:CL159 : coreaxi.v(1511) | Input ARREADY_S5 is unused. @N:CL159 : coreaxi.v(1513) | Input RID_S5 is unused. @N:CL159 : coreaxi.v(1514) | Input RDATA_S5 is unused. @N:CL159 : coreaxi.v(1515) | Input RRESP_S5 is unused. @N:CL159 : coreaxi.v(1516) | Input RLAST_S5 is unused. @N:CL159 : coreaxi.v(1517) | Input RVALID_S5 is unused. @N:CL159 : coreaxi.v(1531) | Input AWREADY_S6 is unused. @N:CL159 : coreaxi.v(1538) | Input WREADY_S6 is unused. @N:CL159 : coreaxi.v(1540) | Input BID_S6 is unused. @N:CL159 : coreaxi.v(1541) | Input BRESP_S6 is unused. @N:CL159 : coreaxi.v(1542) | Input BVALID_S6 is unused. @N:CL159 : coreaxi.v(1554) | Input ARREADY_S6 is unused. @N:CL159 : coreaxi.v(1556) | Input RID_S6 is unused. @N:CL159 : coreaxi.v(1557) | Input RDATA_S6 is unused. @N:CL159 : coreaxi.v(1558) | Input RRESP_S6 is unused. @N:CL159 : coreaxi.v(1559) | Input RLAST_S6 is unused. @N:CL159 : coreaxi.v(1560) | Input RVALID_S6 is unused. @N:CL159 : coreaxi.v(1574) | Input AWREADY_S7 is unused. @N:CL159 : coreaxi.v(1581) | Input WREADY_S7 is unused. @N:CL159 : coreaxi.v(1583) | Input BID_S7 is unused. @N:CL159 : coreaxi.v(1584) | Input BRESP_S7 is unused. @N:CL159 : coreaxi.v(1585) | Input BVALID_S7 is unused. @N:CL159 : coreaxi.v(1597) | Input ARREADY_S7 is unused. @N:CL159 : coreaxi.v(1599) | Input RID_S7 is unused. @N:CL159 : coreaxi.v(1600) | Input RDATA_S7 is unused. @N:CL159 : coreaxi.v(1601) | Input RRESP_S7 is unused. @N:CL159 : coreaxi.v(1602) | Input RLAST_S7 is unused. @N:CL159 : coreaxi.v(1603) | Input RVALID_S7 is unused. @N:CL159 : coreaxi.v(1617) | Input AWREADY_S8 is unused. @N:CL159 : coreaxi.v(1624) | Input WREADY_S8 is unused. @N:CL159 : coreaxi.v(1626) | Input BID_S8 is unused. @N:CL159 : coreaxi.v(1627) | Input BRESP_S8 is unused. @N:CL159 : coreaxi.v(1628) | Input BVALID_S8 is unused. @N:CL159 : coreaxi.v(1640) | Input ARREADY_S8 is unused. @N:CL159 : coreaxi.v(1642) | Input RID_S8 is unused. @N:CL159 : coreaxi.v(1643) | Input RDATA_S8 is unused. @N:CL159 : coreaxi.v(1644) | Input RRESP_S8 is unused. @N:CL159 : coreaxi.v(1645) | Input RLAST_S8 is unused. @N:CL159 : coreaxi.v(1646) | Input RVALID_S8 is unused. @N:CL159 : coreaxi.v(1660) | Input AWREADY_S9 is unused. @N:CL159 : coreaxi.v(1667) | Input WREADY_S9 is unused. @N:CL159 : coreaxi.v(1669) | Input BID_S9 is unused. @N:CL159 : coreaxi.v(1670) | Input BRESP_S9 is unused. @N:CL159 : coreaxi.v(1671) | Input BVALID_S9 is unused. @N:CL159 : coreaxi.v(1683) | Input ARREADY_S9 is unused. @N:CL159 : coreaxi.v(1685) | Input RID_S9 is unused. @N:CL159 : coreaxi.v(1686) | Input RDATA_S9 is unused. @N:CL159 : coreaxi.v(1687) | Input RRESP_S9 is unused. @N:CL159 : coreaxi.v(1688) | Input RLAST_S9 is unused. @N:CL159 : coreaxi.v(1689) | Input RVALID_S9 is unused. @N:CL159 : coreaxi.v(1703) | Input AWREADY_S10 is unused. @N:CL159 : coreaxi.v(1710) | Input WREADY_S10 is unused. @N:CL159 : coreaxi.v(1712) | Input BID_S10 is unused. @N:CL159 : coreaxi.v(1713) | Input BRESP_S10 is unused. @N:CL159 : coreaxi.v(1714) | Input BVALID_S10 is unused. @N:CL159 : coreaxi.v(1726) | Input ARREADY_S10 is unused. @N:CL159 : coreaxi.v(1728) | Input RID_S10 is unused. @N:CL159 : coreaxi.v(1729) | Input RDATA_S10 is unused. @N:CL159 : coreaxi.v(1730) | Input RRESP_S10 is unused. @N:CL159 : coreaxi.v(1731) | Input RLAST_S10 is unused. @N:CL159 : coreaxi.v(1732) | Input RVALID_S10 is unused. @N:CL159 : coreaxi.v(1746) | Input AWREADY_S11 is unused. @N:CL159 : coreaxi.v(1753) | Input WREADY_S11 is unused. @N:CL159 : coreaxi.v(1755) | Input BID_S11 is unused. @N:CL159 : coreaxi.v(1756) | Input BRESP_S11 is unused. @N:CL159 : coreaxi.v(1757) | Input BVALID_S11 is unused. @N:CL159 : coreaxi.v(1769) | Input ARREADY_S11 is unused. @N:CL159 : coreaxi.v(1771) | Input RID_S11 is unused. @N:CL159 : coreaxi.v(1772) | Input RDATA_S11 is unused. @N:CL159 : coreaxi.v(1773) | Input RRESP_S11 is unused. @N:CL159 : coreaxi.v(1774) | Input RLAST_S11 is unused. @N:CL159 : coreaxi.v(1775) | Input RVALID_S11 is unused. @N:CL159 : coreaxi.v(1789) | Input AWREADY_S12 is unused. @N:CL159 : coreaxi.v(1796) | Input WREADY_S12 is unused. @N:CL159 : coreaxi.v(1798) | Input BID_S12 is unused. @N:CL159 : coreaxi.v(1799) | Input BRESP_S12 is unused. @N:CL159 : coreaxi.v(1800) | Input BVALID_S12 is unused. @N:CL159 : coreaxi.v(1812) | Input ARREADY_S12 is unused. @N:CL159 : coreaxi.v(1814) | Input RID_S12 is unused. @N:CL159 : coreaxi.v(1815) | Input RDATA_S12 is unused. @N:CL159 : coreaxi.v(1816) | Input RRESP_S12 is unused. @N:CL159 : coreaxi.v(1817) | Input RLAST_S12 is unused. @N:CL159 : coreaxi.v(1818) | Input RVALID_S12 is unused. @N:CL159 : coreaxi.v(1832) | Input AWREADY_S13 is unused. @N:CL159 : coreaxi.v(1839) | Input WREADY_S13 is unused. @N:CL159 : coreaxi.v(1841) | Input BID_S13 is unused. @N:CL159 : coreaxi.v(1842) | Input BRESP_S13 is unused. @N:CL159 : coreaxi.v(1843) | Input BVALID_S13 is unused. @N:CL159 : coreaxi.v(1855) | Input ARREADY_S13 is unused. @N:CL159 : coreaxi.v(1857) | Input RID_S13 is unused. @N:CL159 : coreaxi.v(1858) | Input RDATA_S13 is unused. @N:CL159 : coreaxi.v(1859) | Input RRESP_S13 is unused. @N:CL159 : coreaxi.v(1860) | Input RLAST_S13 is unused. @N:CL159 : coreaxi.v(1861) | Input RVALID_S13 is unused. @N:CL159 : coreaxi.v(1875) | Input AWREADY_S14 is unused. @N:CL159 : coreaxi.v(1882) | Input WREADY_S14 is unused. @N:CL159 : coreaxi.v(1884) | Input BID_S14 is unused. @N:CL159 : coreaxi.v(1885) | Input BRESP_S14 is unused. @N:CL159 : coreaxi.v(1886) | Input BVALID_S14 is unused. @N:CL159 : coreaxi.v(1898) | Input ARREADY_S14 is unused. @N:CL159 : coreaxi.v(1900) | Input RID_S14 is unused. @N:CL159 : coreaxi.v(1901) | Input RDATA_S14 is unused. @N:CL159 : coreaxi.v(1902) | Input RRESP_S14 is unused. @N:CL159 : coreaxi.v(1903) | Input RLAST_S14 is unused. @N:CL159 : coreaxi.v(1904) | Input RVALID_S14 is unused. @N:CL159 : coreaxi.v(1918) | Input AWREADY_S15 is unused. @N:CL159 : coreaxi.v(1925) | Input WREADY_S15 is unused. @N:CL159 : coreaxi.v(1927) | Input BID_S15 is unused. @N:CL159 : coreaxi.v(1928) | Input BRESP_S15 is unused. @N:CL159 : coreaxi.v(1929) | Input BVALID_S15 is unused. @N:CL159 : coreaxi.v(1941) | Input ARREADY_S15 is unused. @N:CL159 : coreaxi.v(1943) | Input RID_S15 is unused. @N:CL159 : coreaxi.v(1944) | Input RDATA_S15 is unused. @N:CL159 : coreaxi.v(1945) | Input RRESP_S15 is unused. @N:CL159 : coreaxi.v(1946) | Input RLAST_S15 is unused. @N:CL159 : coreaxi.v(1947) | Input RVALID_S15 is unused. @N:CL159 : coreaxi.v(1961) | Input AWREADY_S16 is unused. @N:CL159 : coreaxi.v(1968) | Input WREADY_S16 is unused. @N:CL159 : coreaxi.v(1970) | Input BID_S16 is unused. @N:CL159 : coreaxi.v(1971) | Input BRESP_S16 is unused. @N:CL159 : coreaxi.v(1972) | Input BVALID_S16 is unused. @N:CL159 : coreaxi.v(1984) | Input ARREADY_S16 is unused. @N:CL159 : coreaxi.v(1986) | Input RID_S16 is unused. @N:CL159 : coreaxi.v(1987) | Input RDATA_S16 is unused. @N:CL159 : coreaxi.v(1988) | Input RRESP_S16 is unused. @N:CL159 : coreaxi.v(1989) | Input RLAST_S16 is unused. @N:CL159 : coreaxi.v(1990) | Input RVALID_S16 is unused. @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. @N:CL201 : AXI_IF.v(222) | Trying to extract state machine for register axi_fsm_read_state. Extracted state machine for register axi_fsm_read_state State machine has 3 reachable states with original encodings of: 001 010 100 @N:CL201 : AXI_IF.v(95) | Trying to extract state machine for register axi_fsm_current_state. Extracted state machine for register axi_fsm_current_state State machine has 5 reachable states with original encodings of: 001 010 011 100 101 @W:CL260 : AXI_IF.v(222) | Pruning register bit 1 of ARSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL279 : AXI_IF.v(95) | Pruning register bits 7 to 1 of WSTRB[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL260 : AXI_IF.v(95) | Pruning register bit 1 of AWSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL159 : AXI_IF.v(52) | Input BID is unused. @N:CL159 : AXI_IF.v(53) | Input BRESP is unused. @N:CL159 : AXI_IF.v(66) | Input RID is unused. @N:CL159 : AXI_IF.v(67) | Input RDATA is unused. @N:CL159 : AXI_IF.v(68) | Input RRESP is unused. At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 109MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 12 09:32:59 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode @N:NF107 : SF2_MDDR_Demo.v(9) | Selected library: work cell: SF2_MDDR_Demo view verilog as top level @N:NF107 : SF2_MDDR_Demo.v(9) | Selected library: work cell: SF2_MDDR_Demo view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 83MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 12 09:33:00 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 12 09:33:00 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode @N:NF107 : SF2_MDDR_Demo.v(9) | Selected library: work cell: SF2_MDDR_Demo view verilog as top level @N:NF107 : SF2_MDDR_Demo.v(9) | Selected library: work cell: SF2_MDDR_Demo view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Sep 12 09:33:02 2017 ###########################################################] Pre-mapping Report # Tue Sep 12 09:33:02 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\designer\SF2_MDDR_Demo\synthesis.fdc Linked File: SF2_MDDR_Demo_scck.rpt Printing clock summary report in "C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\synthesis\SF2_MDDR_Demo_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 141MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 141MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 141MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 141MB) @W:BN132 : axi_if.v(222) | Removing sequential instance MDDR_Demo_top_0.AXI_IF_0.ARBURST_1[0] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.ARSIZE_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : axi_if.v(95) | Removing sequential instance MDDR_Demo_top_0.AXI_IF_0.AWBURST_1[0] because it is equivalent to instance MDDR_Demo_top_0.AXI_IF_0.AWSIZE_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1089) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_4 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_4 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_5 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_5 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_6 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_6 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_7 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_7 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_8 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_8 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_9 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_9 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1331) | Tristate driver ARADDR_S1_10 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARADDR_S1_10 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : uart_if_fsm.v(102) | Removing sequential instance start_read (in view: work.UART_IF_FSM(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. syn_allowed_resources : blockrams=109 set on top level netlist SF2_MDDR_Demo Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 162MB peak: 163MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 40.0 MHz 25.000 generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 153 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 160.0 MHz 6.250 generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 429 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 31 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB 40.0 MHz 25.000 declared default_clkgroup 109 ======================================================================================================================================================================================================================================== Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\synthesis\SF2_MDDR_Demo.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 163MB) Encoding state machine axi_fsm_current_state[4:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog)) original code -> new code 001 -> 00001 010 -> 00010 011 -> 00100 100 -> 01000 101 -> 10000 Encoding state machine axi_fsm_read_state[2:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog)) original code -> new code 001 -> 00 010 -> 01 100 -> 10 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(110) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog)); safe FSM implementation is not required. Encoding state machine fsm[11:0] (in view: work.UART_IF_FSM(verilog)) original code -> new code 000000 -> 000000000001 000001 -> 000000000010 000010 -> 000000000100 000100 -> 000000001000 000101 -> 000000010000 000111 -> 000000100000 001000 -> 000001000000 001010 -> 000010000000 001011 -> 000100000000 001100 -> 001000000000 001101 -> 010000000000 001110 -> 100000000000 @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[16] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[17] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[18] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[19] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[20] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[21] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[22] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[23] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[24] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[25] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[26] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[27] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[28] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[29] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[30] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[31] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[11] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\synthesis\SF2_MDDR_Demo_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 160MB peak: 163MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 67MB peak: 163MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Sep 12 09:33:03 2017 ###########################################################] Map & Optimize Report # Tue Sep 12 09:33:03 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 148MB) @N:MO111 : coreaxi.v(1991) | Tristate driver RREADY_S16 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net RREADY_S16 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1983) | Tristate driver ARVALID_S16 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARVALID_S16 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1982) | Tristate driver ARPROT_S16_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARPROT_S16_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1982) | Tristate driver ARPROT_S16_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARPROT_S16_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1982) | Tristate driver ARPROT_S16_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARPROT_S16_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1981) | Tristate driver ARCACHE_S16_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARCACHE_S16_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1981) | Tristate driver ARCACHE_S16_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARCACHE_S16_2 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1981) | Tristate driver ARCACHE_S16_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARCACHE_S16_3 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1981) | Tristate driver ARCACHE_S16_4 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARCACHE_S16_4 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @N:MO111 : coreaxi.v(1980) | Tristate driver ARLOCK_S16_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) on net ARLOCK_S16_1 (in view: work.MDDR_Demo_sb_COREAXI_0_COREAXI_Z3(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(884) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1581) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif3_core because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif2_core. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1549) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif2_core because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif1_core. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1517) | Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif1_core because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif0_core. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 150MB) Encoding state machine axi_fsm_current_state[4:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog)) original code -> new code 001 -> 00001 010 -> 00010 011 -> 00100 100 -> 01000 101 -> 10000 Encoding state machine axi_fsm_read_state[2:0] (in view: work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog)) original code -> new code 001 -> 00 010 -> 01 100 -> 10 @N:MO231 : axi_if.v(95) | Found counter in view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z1(verilog) instance WDATA_int[63:0] Encoding state machine state[2:0] (in view: work.CoreConfigP_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[16] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[17] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[18] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[19] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[20] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[21] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[22] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[23] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[24] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[25] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[26] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[27] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[28] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[29] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[30] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[31] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[11] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[31] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[30] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[29] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[28] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[27] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[26] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[25] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[24] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[23] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[22] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[21] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[20] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[19] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[14] (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:BN132 : coreconfigp.v(546) | Removing instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z6(verilog) instance count_ddr[13:0] Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(110) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_32s_32s(verilog)); safe FSM implementation is not required. Encoding state machine fsm[11:0] (in view: work.UART_IF_FSM(verilog)) original code -> new code 000000 -> 000000000001 000001 -> 000000000010 000010 -> 000000000100 000100 -> 000000001000 000101 -> 000000010000 000111 -> 000000100000 001000 -> 000001000000 001010 -> 000010000000 001011 -> 000100000000 001100 -> 001000000000 001101 -> 010000000000 001110 -> 100000000000 @N:MO231 : uart_if_fsm.v(102) | Found counter in view:work.UART_IF_FSM(verilog) instance RAM_WADDR[7:0] @N:MO231 : uart_if_fsm.v(102) | Found counter in view:work.UART_IF_FSM(verilog) instance cnt_1k[9:0] Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 150MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.DDR_READY_int (in view: work.SF2_MDDR_Demo(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 150MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 150MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 150MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 150MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 150MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 150MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 150MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 150MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s -2.16ns 675 / 659 2 0h:00m:01s -2.16ns 631 / 659 3 0h:00m:02s -2.16ns 631 / 659 4 0h:00m:02s -1.65ns 632 / 659 5 0h:00m:02s -1.65ns 632 / 659 @N:FP130 : | Promoting Net INIT_DONE_c on CLKINT I_261 @N:FP130 : | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT I_262 @N:FP130 : | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT I_263 @N:FP130 : | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_264 @N:FP130 : | Promoting Net MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_265 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 150MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 150MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 2 non-gated/non-generated clock tree(s) driving 97 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 572 clock pin(s) of sequential element(s) 0 instances converted, 572 sequential instances remain driven by gated/generated clocks ================================================================================================ Non-Gated/Non-Generated Clocks ================================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0003 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_075 75 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST ClockId0004 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 22 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[13] ================================================================================================================================================================================================================================= =================================================================================================================== Gated/Generated Clocks =================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST CCC 422 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[63] No gated clock conversion method for cell cell:ACG4.SLE ClockId0002 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CCC_0.CCC_INST CCC 150 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ============================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 117MB peak: 150MB) Writing Analyst data base C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\synthesis\synwork\SF2_MDDR_Demo_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 143MB peak: 150MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\synthesis\SF2_MDDR_Demo.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 145MB peak: 150MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 145MB peak: 150MB) @W:MT246 : mddr_demo_sb_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB with period 25.00ns @N:MT615 : | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 with period 25.00ns @N:MT615 : | Found clock MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 with period 6.25ns ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Sep 12 09:33:07 2017 # Top view: SF2_MDDR_Demo Requested Frequency: 40.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\designer\SF2_MDDR_Demo\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -0.812 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 40.0 MHz 35.4 MHz 25.000 28.247 -0.812 generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 160.0 MHz 141.6 MHz 6.250 7.062 1.829 generated (from MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 428.6 MHz 20.000 2.333 17.667 declared default_clkgroup MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB 40.0 MHz 100.3 MHz 25.000 9.970 7.515 declared default_clkgroup ===================================================================================================================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.667 | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | 5.000 False | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB | 25.000 18.216 | No paths - | 12.500 10.490 | 12.500 7.515 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | 25.000 False | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 5.000 False | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB | 25.000 False | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | 25.000 13.935 | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 | 6.250 -0.812 | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | 6.250 3.566 | No paths - | No paths - | No paths - MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 | 6.250 1.829 | No paths - | No paths - | No paths - ==================================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RLAST MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 3.844 -0.812 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RVALID MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 3.847 -0.715 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_WREADY AXI_IF_0_BIF_1_WREADY 3.547 -0.639 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_AWREADY_HREADYOUT0 AXI_IF_0_BIF_1_AWREADY 3.980 -0.425 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RDATA_HRDATA01[31] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[31] 4.508 0.478 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RDATA_HRDATA01[41] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[41] 4.064 0.922 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RDATA_HRDATA01[29] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[29] 4.037 0.949 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RDATA_HRDATA01[43] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[43] 4.033 0.953 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RDATA_HRDATA01[33] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[33] 4.029 0.957 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 MSS_075 F_RDATA_HRDATA01[30] MDDR_Demo_top_0_AMBA_MASTER_0_RDATA_M0[30] 4.026 0.960 ================================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- UART_IF_0.UART_IF_FSM_0.RAM_WADDR[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[1] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[2] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[3] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[4] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[5] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[6] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[7] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE EN RAM_WADDRe 5.957 -0.812 UART_IF_0.UART_IF_FSM_0.AXI_address[31] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE D AXI_address_9[31] 6.028 -0.675 UART_IF_0.UART_IF_FSM_0.AXI_address[30] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 SLE D AXI_address_9[30] 6.028 -0.661 =============================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.250 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.957 - Propagation time: 6.768 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.812 Number of logic level(s): 2 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_RLAST Ending point: UART_IF_0.UART_IF_FSM_0.RAM_WADDR[0] / EN The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] on pin CLK_BASE The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_RLAST Out 3.844 3.844 - MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 Net - - 0.982 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 C In - 4.826 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 Y Out 0.194 5.019 - N_61 Net - - 0.622 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 D In - 5.641 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 Y Out 0.284 5.925 - RAM_WADDRe Net - - 0.843 - 8 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[0] SLE EN In - 6.768 - ================================================================================================================================================= Total path delay (propagation time + setup) of 7.062 is 4.615(65.4%) logic and 2.447(34.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 6.250 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.957 - Propagation time: 6.768 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.812 Number of logic level(s): 2 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_RLAST Ending point: UART_IF_0.UART_IF_FSM_0.RAM_WADDR[7] / EN The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] on pin CLK_BASE The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_RLAST Out 3.844 3.844 - MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 Net - - 0.982 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 C In - 4.826 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 Y Out 0.194 5.019 - N_61 Net - - 0.622 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 D In - 5.641 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 Y Out 0.284 5.925 - RAM_WADDRe Net - - 0.843 - 8 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[7] SLE EN In - 6.768 - ================================================================================================================================================= Total path delay (propagation time + setup) of 7.062 is 4.615(65.4%) logic and 2.447(34.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 6.250 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.957 - Propagation time: 6.768 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.812 Number of logic level(s): 2 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_RLAST Ending point: UART_IF_0.UART_IF_FSM_0.RAM_WADDR[6] / EN The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] on pin CLK_BASE The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_RLAST Out 3.844 3.844 - MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 Net - - 0.982 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 C In - 4.826 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 Y Out 0.194 5.019 - N_61 Net - - 0.622 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 D In - 5.641 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 Y Out 0.284 5.925 - RAM_WADDRe Net - - 0.843 - 8 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[6] SLE EN In - 6.768 - ================================================================================================================================================= Total path delay (propagation time + setup) of 7.062 is 4.615(65.4%) logic and 2.447(34.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 6.250 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.957 - Propagation time: 6.768 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.812 Number of logic level(s): 2 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_RLAST Ending point: UART_IF_0.UART_IF_FSM_0.RAM_WADDR[5] / EN The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] on pin CLK_BASE The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_RLAST Out 3.844 3.844 - MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 Net - - 0.982 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 C In - 4.826 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 Y Out 0.194 5.019 - N_61 Net - - 0.622 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 D In - 5.641 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 Y Out 0.284 5.925 - RAM_WADDRe Net - - 0.843 - 8 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[5] SLE EN In - 6.768 - ================================================================================================================================================= Total path delay (propagation time + setup) of 7.062 is 4.615(65.4%) logic and 2.447(34.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 6.250 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.957 - Propagation time: 6.768 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.812 Number of logic level(s): 2 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST / F_RLAST Ending point: UART_IF_0.UART_IF_FSM_0.RAM_WADDR[4] / EN The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 [rising] on pin CLK_BASE The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_RLAST Out 3.844 3.844 - MDDR_Demo_top_0_AMBA_MASTER_0_RLAST_M0 Net - - 0.982 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 C In - 4.826 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2[10] CFG3 Y Out 0.194 5.019 - N_61 Net - - 0.622 - 4 UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 D In - 5.641 - UART_IF_0.UART_IF_FSM_0.fsm_ns_i_i_o2_RNI008U1[10] CFG4 Y Out 0.284 5.925 - RAM_WADDRe Net - - 0.843 - 8 UART_IF_0.UART_IF_FSM_0.RAM_WADDR[4] SLE EN In - 6.768 - ================================================================================================================================================= Total path delay (propagation time + setup) of 7.062 is 4.615(65.4%) logic and 2.447(34.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q axi_fsm_current_state[0] 0.094 1.829 UART_IF_0.UART_IF_FSM_0.fsm[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q fsm[0] 0.094 1.865 UART_IF_0.UART_IF_FSM_0.WRITE MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q UART_IF_0_WRITE 0.094 1.883 MDDR_Demo_top_0.AXI_IF_0.BREADY MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q MDDR_Demo_top_0_BREADY 0.094 2.230 UART_IF_0.UART_IF_FSM_0.fsm[7] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q fsm[7] 0.094 2.471 MDDR_Demo_top_0.AXI_IF_0.RREADY MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q MDDR_Demo_top_0_RREADY 0.094 2.630 UART_IF_0.UART_IF_FSM_0.cnt_1k[4] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q cnt_1k[4] 0.094 2.641 MDDR_Demo_top_0.AXI_IF_0.AWLEN[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q AXI_IF_0_BIF_1_AWLEN[0] 0.094 2.644 UART_IF_0.UART_IF_FSM_0.cnt_1k[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q cnt_1k[0] 0.076 2.693 UART_IF_0.UART_IF_FSM_0.cnt_1k[5] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE Q cnt_1k[5] 0.076 2.713 ============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.AXI_IF_0.WDATA_int[63] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D WDATA_int_s[63] 6.028 1.829 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[62] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D WDATA_int_s[62] 6.028 1.843 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[61] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D WDATA_int_s[61] 6.028 1.857 UART_IF_0.UART_IF_FSM_0.AXI_data_in[63] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D AXI_data_in_6[63] 6.028 1.865 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[60] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D WDATA_int_s[60] 6.028 1.871 UART_IF_0.UART_IF_FSM_0.AXI_data_in[62] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D AXI_data_in_6[62] 6.028 1.879 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[59] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D WDATA_int_s[59] 6.028 1.885 UART_IF_0.UART_IF_FSM_0.AXI_data_in[61] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D AXI_data_in_6[61] 6.028 1.893 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[58] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D WDATA_int_s[58] 6.028 1.900 UART_IF_0.UART_IF_FSM_0.AXI_data_in[60] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 SLE D AXI_data_in_6[60] 6.028 1.908 ============================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.250 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.028 - Propagation time: 4.199 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.829 Number of logic level(s): 64 Starting point: MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[0] / Q Ending point: MDDR_Demo_top_0.AXI_IF_0.WDATA_int[63] / D The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ MDDR_Demo_top_0.AXI_IF_0.axi_fsm_current_state[0] SLE Q Out 0.094 0.094 - axi_fsm_current_state[0] Net - - 0.759 - 7 MDDR_Demo_top_0.AXI_IF_0.AWBURST_0_sqmuxa_0_a3_0_a2 CFG2 A In - 0.853 - MDDR_Demo_top_0.AXI_IF_0.AWBURST_0_sqmuxa_0_a3_0_a2 CFG2 Y Out 0.076 0.929 - AWBURST_0_sqmuxa Net - - 1.195 - 76 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIP0CP1[1] ARI1 B In - 2.124 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIP0CP1[1] ARI1 FCO Out 0.174 2.298 - WDATA_int_cry[1] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNII2992[2] ARI1 FCI In - 2.298 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNII2992[2] ARI1 FCO Out 0.014 2.313 - WDATA_int_cry[2] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNID66P2[3] ARI1 FCI In - 2.313 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNID66P2[3] ARI1 FCO Out 0.014 2.327 - WDATA_int_cry[3] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAC393[4] ARI1 FCI In - 2.327 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAC393[4] ARI1 FCO Out 0.014 2.341 - WDATA_int_cry[4] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9K0P3[5] ARI1 FCI In - 2.341 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9K0P3[5] ARI1 FCO Out 0.014 2.355 - WDATA_int_cry[5] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAUT84[6] ARI1 FCI In - 2.355 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAUT84[6] ARI1 FCO Out 0.014 2.369 - WDATA_int_cry[6] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDARO4[7] ARI1 FCI In - 2.369 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDARO4[7] ARI1 FCO Out 0.014 2.384 - WDATA_int_cry[7] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIOO85[8] ARI1 FCI In - 2.384 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIOO85[8] ARI1 FCO Out 0.014 2.398 - WDATA_int_cry[8] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIP8MO5[9] ARI1 FCI In - 2.398 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIP8MO5[9] ARI1 FCO Out 0.014 2.412 - WDATA_int_cry[9] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIG9CI6[10] ARI1 FCI In - 2.412 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIG9CI6[10] ARI1 FCO Out 0.014 2.426 - WDATA_int_cry[10] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9C2C7[11] ARI1 FCI In - 2.426 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9C2C7[11] ARI1 FCO Out 0.014 2.440 - WDATA_int_cry[11] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI4HO58[12] ARI1 FCI In - 2.440 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI4HO58[12] ARI1 FCO Out 0.014 2.455 - WDATA_int_cry[12] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1OEV8[13] ARI1 FCI In - 2.455 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1OEV8[13] ARI1 FCO Out 0.014 2.469 - WDATA_int_cry[13] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI015P9[14] ARI1 FCI In - 2.469 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI015P9[14] ARI1 FCO Out 0.014 2.483 - WDATA_int_cry[14] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1CRIA[15] ARI1 FCI In - 2.483 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1CRIA[15] ARI1 FCO Out 0.014 2.497 - WDATA_int_cry[15] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI4PHCB[16] ARI1 FCI In - 2.497 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI4PHCB[16] ARI1 FCO Out 0.014 2.511 - WDATA_int_cry[16] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9886C[17] ARI1 FCI In - 2.511 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9886C[17] ARI1 FCO Out 0.014 2.526 - WDATA_int_cry[17] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIGPUVC[18] ARI1 FCI In - 2.526 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIGPUVC[18] ARI1 FCO Out 0.014 2.540 - WDATA_int_cry[18] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIPCLPD[19] ARI1 FCI In - 2.540 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIPCLPD[19] ARI1 FCO Out 0.014 2.554 - WDATA_int_cry[19] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIHDJE[20] ARI1 FCI In - 2.554 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIHDJE[20] ARI1 FCO Out 0.014 2.568 - WDATA_int_cry[20] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDO5DF[21] ARI1 FCI In - 2.568 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDO5DF[21] ARI1 FCO Out 0.014 2.582 - WDATA_int_cry[21] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIA1U6G[22] ARI1 FCI In - 2.582 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIA1U6G[22] ARI1 FCO Out 0.014 2.597 - WDATA_int_cry[22] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9CM0H[23] ARI1 FCI In - 2.597 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9CM0H[23] ARI1 FCO Out 0.014 2.611 - WDATA_int_cry[23] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAPEQH[24] ARI1 FCI In - 2.611 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAPEQH[24] ARI1 FCO Out 0.014 2.625 - WDATA_int_cry[24] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNID87KI[25] ARI1 FCI In - 2.625 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNID87KI[25] ARI1 FCO Out 0.014 2.639 - WDATA_int_cry[25] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIPVDJ[26] ARI1 FCI In - 2.639 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIPVDJ[26] ARI1 FCO Out 0.014 2.653 - WDATA_int_cry[26] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIPCO7K[27] ARI1 FCI In - 2.653 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIPCO7K[27] ARI1 FCO Out 0.014 2.668 - WDATA_int_cry[27] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI22H1L[28] ARI1 FCI In - 2.668 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI22H1L[28] ARI1 FCO Out 0.014 2.682 - WDATA_int_cry[28] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDP9RL[29] ARI1 FCI In - 2.682 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDP9RL[29] ARI1 FCO Out 0.014 2.696 - WDATA_int_cry[29] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI824LM[30] ARI1 FCI In - 2.696 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI824LM[30] ARI1 FCO Out 0.014 2.710 - WDATA_int_cry[30] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI5DUEN[31] ARI1 FCI In - 2.710 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI5DUEN[31] ARI1 FCO Out 0.014 2.724 - WDATA_int_cry[31] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI4QO8O[32] ARI1 FCI In - 2.724 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI4QO8O[32] ARI1 FCO Out 0.014 2.739 - WDATA_int_cry[32] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI59J2P[33] ARI1 FCI In - 2.739 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI59J2P[33] ARI1 FCO Out 0.014 2.753 - WDATA_int_cry[33] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI8QDSP[34] ARI1 FCI In - 2.753 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI8QDSP[34] ARI1 FCO Out 0.014 2.767 - WDATA_int_cry[34] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDD8MQ[35] ARI1 FCI In - 2.767 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIDD8MQ[35] ARI1 FCO Out 0.014 2.781 - WDATA_int_cry[35] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIK23GR[36] ARI1 FCI In - 2.781 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIK23GR[36] ARI1 FCO Out 0.014 2.795 - WDATA_int_cry[36] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNITPT9S[37] ARI1 FCI In - 2.795 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNITPT9S[37] ARI1 FCO Out 0.014 2.810 - WDATA_int_cry[37] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI8JO3T[38] ARI1 FCI In - 2.810 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI8JO3T[38] ARI1 FCO Out 0.014 2.824 - WDATA_int_cry[38] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNILEJTT[39] ARI1 FCI In - 2.824 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNILEJTT[39] ARI1 FCO Out 0.014 2.838 - WDATA_int_cry[39] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIRFNU[40] ARI1 FCI In - 2.838 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIRFNU[40] ARI1 FCO Out 0.014 2.852 - WDATA_int_cry[40] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIHACHV[41] ARI1 FCI In - 2.852 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIHACHV[41] ARI1 FCO Out 0.014 2.866 - WDATA_int_cry[41] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIR8B01[42] ARI1 FCI In - 2.866 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIIR8B01[42] ARI1 FCO Out 0.014 2.881 - WDATA_int_cry[42] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNILE5511[43] ARI1 FCI In - 2.881 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNILE5511[43] ARI1 FCO Out 0.014 2.895 - WDATA_int_cry[43] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIQ32V11[44] ARI1 FCI In - 2.895 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIQ32V11[44] ARI1 FCO Out 0.014 2.909 - WDATA_int_cry[44] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1RUO21[45] ARI1 FCI In - 2.909 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1RUO21[45] ARI1 FCO Out 0.014 2.923 - WDATA_int_cry[45] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAKRI31[46] ARI1 FCI In - 2.923 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAKRI31[46] ARI1 FCO Out 0.014 2.937 - WDATA_int_cry[46] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNILFOC41[47] ARI1 FCI In - 2.937 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNILFOC41[47] ARI1 FCO Out 0.014 2.952 - WDATA_int_cry[47] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI2DL651[48] ARI1 FCI In - 2.952 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI2DL651[48] ARI1 FCO Out 0.014 2.966 - WDATA_int_cry[48] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIHCI061[49] ARI1 FCI In - 2.966 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIHCI061[49] ARI1 FCO Out 0.014 2.980 - WDATA_int_cry[49] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIGTGQ61[50] ARI1 FCI In - 2.980 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIGTGQ61[50] ARI1 FCO Out 0.014 2.994 - WDATA_int_cry[50] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIHGFK71[51] ARI1 FCI In - 2.994 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIHGFK71[51] ARI1 FCO Out 0.014 3.008 - WDATA_int_cry[51] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIK5EE81[52] ARI1 FCI In - 3.008 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIK5EE81[52] ARI1 FCO Out 0.014 3.023 - WDATA_int_cry[52] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIPSC891[53] ARI1 FCI In - 3.023 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIPSC891[53] ARI1 FCO Out 0.014 3.037 - WDATA_int_cry[53] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI0MB2A1[54] ARI1 FCI In - 3.037 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI0MB2A1[54] ARI1 FCO Out 0.014 3.051 - WDATA_int_cry[54] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9HASA1[55] ARI1 FCI In - 3.051 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI9HASA1[55] ARI1 FCO Out 0.014 3.065 - WDATA_int_cry[55] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIKE9MB1[56] ARI1 FCI In - 3.065 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIKE9MB1[56] ARI1 FCO Out 0.014 3.079 - WDATA_int_cry[56] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1E8GC1[57] ARI1 FCI In - 3.079 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1E8GC1[57] ARI1 FCO Out 0.014 3.094 - WDATA_int_cry[57] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIGF7AD1[58] ARI1 FCI In - 3.094 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIGF7AD1[58] ARI1 FCO Out 0.014 3.108 - WDATA_int_cry[58] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1J64E1[59] ARI1 FCI In - 3.108 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI1J64E1[59] ARI1 FCO Out 0.014 3.122 - WDATA_int_cry[59] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI287UE1[60] ARI1 FCI In - 3.122 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI287UE1[60] ARI1 FCO Out 0.014 3.136 - WDATA_int_cry[60] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI5V7OF1[61] ARI1 FCI In - 3.136 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNI5V7OF1[61] ARI1 FCO Out 0.014 3.150 - WDATA_int_cry[61] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAO8IG1[62] ARI1 FCI In - 3.150 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNIAO8IG1[62] ARI1 FCO Out 0.014 3.165 - WDATA_int_cry[62] Net - - 0.000 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNO[63] ARI1 FCI In - 3.165 - MDDR_Demo_top_0.AXI_IF_0.WDATA_int_RNO[63] ARI1 S Out 0.063 3.228 - WDATA_int_s[63] Net - - 0.971 - 1 MDDR_Demo_top_0.AXI_IF_0.WDATA_int[63] SLE D In - 4.199 - ================================================================================================================== Total path delay (propagation time + setup) of 4.421 is 1.496(33.8%) logic and 2.925(66.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[0] 0.094 17.667 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[1] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[1] 0.094 17.732 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[2] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[2] 0.094 17.746 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[3] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[3] 0.094 17.760 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[4] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[4] 0.094 17.774 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[5] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[5] 0.094 17.789 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[6] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[6] 0.094 17.803 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[7] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[7] 0.094 17.817 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[8] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[8] 0.094 17.831 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[9] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[9] 0.094 17.845 ============================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[13] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[13] 19.778 17.667 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[12] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[12] 19.778 17.681 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[11] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[11] 19.778 17.695 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[10] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[10] 19.778 17.709 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[9] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[9] 19.778 17.724 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[8] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[8] 19.778 17.738 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[7] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[7] 19.778 17.752 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[6] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[6] 19.778 17.766 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[5] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[5] 19.778 17.780 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[4] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[4] 19.778 17.794 ================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 2.111 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.667 Number of logic level(s): 14 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[0] / Q Ending point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[13] / D The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.094 0.094 - count_ddr[0] Net - - 0.637 - 3 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_s_260 ARI1 B In - 0.732 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_s_260 ARI1 FCO Out 0.174 0.906 - count_ddr_s_260_FCO Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCI In - 0.906 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCO Out 0.014 0.920 - count_ddr_cry[1] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCI In - 0.920 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCO Out 0.014 0.935 - count_ddr_cry[2] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCI In - 0.935 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCO Out 0.014 0.949 - count_ddr_cry[3] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCI In - 0.949 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCO Out 0.014 0.963 - count_ddr_cry[4] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCI In - 0.963 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCO Out 0.014 0.977 - count_ddr_cry[5] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCI In - 0.977 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCO Out 0.014 0.991 - count_ddr_cry[6] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCI In - 0.991 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCO Out 0.014 1.006 - count_ddr_cry[7] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCI In - 1.006 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCO Out 0.014 1.020 - count_ddr_cry[8] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCI In - 1.020 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCO Out 0.014 1.034 - count_ddr_cry[9] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCI In - 1.034 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCO Out 0.014 1.048 - count_ddr_cry[10] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCI In - 1.048 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCO Out 0.014 1.062 - count_ddr_cry[11] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCI In - 1.062 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCO Out 0.014 1.077 - count_ddr_cry[12] Net - - 0.000 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_s[13] ARI1 FCI In - 1.077 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr_s[13] ARI1 S Out 0.063 1.140 - count_ddr_s[13] Net - - 0.971 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.count_ddr[13] SLE D In - 2.111 - ======================================================================================================================================== Total path delay (propagation time + setup) of 2.333 is 0.725(31.1%) logic and 1.609(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.psel MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 7.515 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[1] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 10.490 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.paddr[15] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[15] 0.094 11.144 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.paddr[13] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[13] 0.094 11.241 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 11.284 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.paddr[12] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[12] 0.094 11.322 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.MDDR_PENABLE MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE Q CORECONFIGP_0_MDDR_APBmslave_PENABLE 0.094 11.434 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB MSS_075 MDDR_FABRIC_PRDATA[1] CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] 4.666 18.216 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB MSS_075 MDDR_FABRIC_PREADY CORECONFIGP_0_MDDR_APBmslave_PREADY 4.525 18.239 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB MSS_075 MDDR_FABRIC_PRDATA[0] CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] 4.721 18.254 ===================================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 12.278 7.515 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 12.278 7.779 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 12.278 7.872 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 12.278 8.066 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 12.278 8.066 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[16] 12.278 8.125 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 12.278 8.159 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 12.278 8.159 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[7] 12.278 8.159 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8] MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[8] 12.278 8.159 ======================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.500 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.278 - Propagation time: 4.763 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.515 Number of logic level(s): 5 Starting point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.psel / Q Ending point: MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] / D The start point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB [falling] on pin CLK The end point is clocked by MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------- MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.676 - 4 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.MDDR_PSEL CFG4 D In - 0.770 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.MDDR_PSEL CFG4 Y Out 0.250 1.021 - CORECONFIGP_0_MDDR_APBmslave_PSELx Net - - 0.994 - 20 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_R_SDIF3_PSEL_1 CFG3 B In - 2.014 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.un1_R_SDIF3_PSEL_1 CFG3 Y Out 0.129 2.143 - un1_R_SDIF3_PSEL_1 Net - - 0.648 - 5 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.int_prdata_4_sqmuxa CFG4 D In - 2.791 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.int_prdata_4_sqmuxa CFG4 Y Out 0.236 3.027 - int_prdata_4_sqmuxa Net - - 0.812 - 17 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_0_iv_RNO[5] CFG2 A In - 3.838 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_0_iv_RNO[5] CFG2 Y Out 0.067 3.906 - soft_reset_reg_m[5] Net - - 0.483 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_0_iv[5] CFG4 D In - 4.389 - MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.prdata_0_iv[5] CFG4 Y Out 0.236 4.625 - prdata[5] Net - - 0.138 - 1 MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] SLE D In - 4.763 - ============================================================================================================================================= Total path delay (propagation time + setup) of 4.985 is 1.235(24.8%) logic and 3.750(75.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(13) | Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(16) | Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(17) | Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(18) | Timing constraint (through [get_nets { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 145MB peak: 150MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 145MB peak: 150MB) --------------------------------------- Resource Usage Report for SF2_MDDR_Demo Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 8 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use CFG1 6 uses CFG2 61 uses CFG3 105 uses CFG4 232 uses Carry cells: ARI1 193 uses - used for arithmetic functions Sequential Cells: SLE 659 uses DSP Blocks: 0 of 84 (0%) I/O ports: 54 I/O primitives: 52 BIBUF 20 uses INBUF 2 uses OUTBUF 28 uses OUTBUF_DIFF 1 use TRIBUFF 1 use Global Clock Buffers: 8 of 8 (100%) RAM/ROM usage summary Total Block RAMs (RAM1K18) : 4 of 109 (3%) Total LUTs: 597 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 144; LUTs = 144; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 659 + 0 + 144 + 0 = 803; Total number of LUTs after P&R: 597 + 0 + 144 + 0 = 741; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 36MB peak: 150MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Sep 12 09:33:07 2017 ###########################################################]