@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif3_core because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif2_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif2_core because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif1_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Removing sequential instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif1_core because it is equivalent to instance MDDR_Demo_sb_0.CORERESETP_0.release_sdif0_core. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit paddr[16] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[31] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[30] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[29] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[28] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[27] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[26] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[25] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[24] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[23] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[22] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[21] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[20] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit FIC_2_APB_M_PRDATA[19] (in view view:work.CoreConfigP_Z5(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Removing instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] because it is equivalent to instance MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"c:\users\athuldeep.n\desktop\urgent_sar_fix\68492_sf2_lpddr\m2s_dg0568_liberov11p8_sp1_df\sf2_mddr_demo_df\libero_project\sf2_mddr_demo\component\work\mddr_demo_sb\ccc_0\mddr_demo_sb_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT447 :"c:/users/athuldeep.n/desktop/urgent_sar_fix/68492_sf2_lpddr/m2s_dg0568_liberov11p8_sp1_df/sf2_mddr_demo_df/libero_project/sf2_mddr_demo/designer/sf2_mddr_demo/synthesis.fdc":13:0:13:0|Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/users/athuldeep.n/desktop/urgent_sar_fix/68492_sf2_lpddr/m2s_dg0568_liberov11p8_sp1_df/sf2_mddr_demo_df/libero_project/sf2_mddr_demo/designer/sf2_mddr_demo/synthesis.fdc":14:0:14:0|Timing constraint (from [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.MSS_HPMS_READY_int MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/users/athuldeep.n/desktop/urgent_sar_fix/68492_sf2_lpddr/m2s_dg0568_liberov11p8_sp1_df/sf2_mddr_demo_df/libero_project/sf2_mddr_demo/designer/sf2_mddr_demo/synthesis.fdc":16:0:16:0|Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.MDDR_Demo_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/users/athuldeep.n/desktop/urgent_sar_fix/68492_sf2_lpddr/m2s_dg0568_liberov11p8_sp1_df/sf2_mddr_demo_df/libero_project/sf2_mddr_demo/designer/sf2_mddr_demo/synthesis.fdc":17:0:17:0|Timing constraint (through [get_pins { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"c:/users/athuldeep.n/desktop/urgent_sar_fix/68492_sf2_lpddr/m2s_dg0568_liberov11p8_sp1_df/sf2_mddr_demo_df/libero_project/sf2_mddr_demo/designer/sf2_mddr_demo/synthesis.fdc":18:0:18:0|Timing constraint (through [get_nets { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
