@W: CL190 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Optimizing register bit AWBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Optimizing register bit AWSIZE[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":222:0:222:5|Optimizing register bit ARBURST[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Pruning register bit 1 of AWBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Pruning register bit 2 of AWSIZE[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":222:0:222:5|Pruning register bit 1 of ARBURST[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG775 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Found Component CoreAPB3 in library COREAPB3_LIB
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CG1283 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\MDDR_Demo_sb.v":1081:0:1081:8|Ignoring localparam NUM_SLAVE_SLOT on the instance and using locally defined value
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|Removing wire AWID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|Removing wire AWADDR_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|Removing wire AWLEN_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|Removing wire AWSIZE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|Removing wire AWBURST_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|Removing wire AWLOCK_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|Removing wire AWCACHE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|Removing wire AWPROT_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|Removing wire AWVALID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|Removing wire WID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|Removing wire WDATA_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|Removing wire WSTRB_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|Removing wire WLAST_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|Removing wire WVALID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|Removing wire BREADY_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|Removing wire ARID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|Removing wire ARADDR_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|Removing wire ARLEN_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|Removing wire ARSIZE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|Removing wire ARBURST_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|Removing wire ARLOCK_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|Removing wire ARCACHE_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|Removing wire ARPROT_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|Removing wire ARVALID_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|Removing wire RREADY_S1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|Removing wire AWID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|Removing wire AWADDR_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|Removing wire AWLEN_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|Removing wire AWSIZE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|Removing wire AWBURST_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|Removing wire AWLOCK_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|Removing wire AWCACHE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|Removing wire AWPROT_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|Removing wire AWVALID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|Removing wire WID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|Removing wire WDATA_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|Removing wire WSTRB_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|Removing wire WLAST_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|Removing wire WVALID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|Removing wire BREADY_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|Removing wire ARID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|Removing wire ARADDR_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|Removing wire ARLEN_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|Removing wire ARSIZE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|Removing wire ARBURST_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|Removing wire ARLOCK_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|Removing wire ARCACHE_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|Removing wire ARPROT_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|Removing wire ARVALID_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|Removing wire RREADY_S2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|Removing wire AWID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|Removing wire AWADDR_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|Removing wire AWLEN_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|Removing wire AWSIZE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|Removing wire AWBURST_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|Removing wire AWLOCK_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|Removing wire AWCACHE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|Removing wire AWPROT_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|Removing wire AWVALID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|Removing wire WID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|Removing wire WDATA_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|Removing wire WSTRB_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|Removing wire WLAST_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|Removing wire WVALID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|Removing wire BREADY_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|Removing wire ARID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|Removing wire ARADDR_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|Removing wire ARLEN_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|Removing wire ARSIZE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|Removing wire ARBURST_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|Removing wire ARLOCK_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|Removing wire ARCACHE_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|Removing wire ARPROT_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|Removing wire ARVALID_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|Removing wire RREADY_S3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|Removing wire AWID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|Removing wire AWADDR_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|Removing wire AWLEN_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|Removing wire AWSIZE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|Removing wire AWBURST_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|Removing wire AWLOCK_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|Removing wire AWCACHE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|Removing wire AWPROT_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|Removing wire AWVALID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|Removing wire WID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|Removing wire WDATA_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|Removing wire WSTRB_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|Removing wire WLAST_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|Removing wire WVALID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|Removing wire BREADY_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|Removing wire ARID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|Removing wire ARADDR_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|Removing wire ARLEN_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|Removing wire ARSIZE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|Removing wire ARBURST_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|Removing wire ARLOCK_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|Removing wire ARCACHE_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|Removing wire ARPROT_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|Removing wire ARVALID_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|Removing wire RREADY_S4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:58:1479:64|Removing wire AWID_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:23:1480:31|Removing wire AWADDR_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:40|Removing wire AWLEN_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1482:33:1482:41|Removing wire AWSIZE_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:33:1483:42|Removing wire AWBURST_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|Removing wire AWLOCK_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:42|Removing wire AWCACHE_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|Removing wire AWPROT_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|Removing wire AWVALID_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1490:58:1490:63|Removing wire WID_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1491:33:1491:40|Removing wire WDATA_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:33:1492:40|Removing wire WSTRB_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:40|Removing wire WLAST_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|Removing wire WVALID_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:41|Removing wire BREADY_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1502:58:1502:64|Removing wire ARID_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:23:1503:31|Removing wire ARADDR_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:40|Removing wire ARLEN_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|Removing wire ARSIZE_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:42|Removing wire ARBURST_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:41|Removing wire ARLOCK_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|Removing wire ARCACHE_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1509:33:1509:41|Removing wire ARPROT_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:33:1510:42|Removing wire ARVALID_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:41|Removing wire RREADY_S5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:58:1522:64|Removing wire AWID_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:23:1523:31|Removing wire AWADDR_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:40|Removing wire AWLEN_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1525:33:1525:41|Removing wire AWSIZE_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:33:1526:42|Removing wire AWBURST_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|Removing wire AWLOCK_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:42|Removing wire AWCACHE_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|Removing wire AWPROT_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|Removing wire AWVALID_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1533:58:1533:63|Removing wire WID_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1534:33:1534:40|Removing wire WDATA_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1535:33:1535:40|Removing wire WSTRB_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1536:33:1536:40|Removing wire WLAST_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1537:33:1537:41|Removing wire WVALID_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1543:33:1543:41|Removing wire BREADY_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1545:58:1545:64|Removing wire ARID_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1546:23:1546:31|Removing wire ARADDR_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1547:33:1547:40|Removing wire ARLEN_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1548:33:1548:41|Removing wire ARSIZE_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1549:33:1549:42|Removing wire ARBURST_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1550:33:1550:41|Removing wire ARLOCK_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1551:33:1551:42|Removing wire ARCACHE_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1552:33:1552:41|Removing wire ARPROT_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1553:33:1553:42|Removing wire ARVALID_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1561:33:1561:41|Removing wire RREADY_S6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1565:58:1565:64|Removing wire AWID_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1566:23:1566:31|Removing wire AWADDR_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1567:33:1567:40|Removing wire AWLEN_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1568:33:1568:41|Removing wire AWSIZE_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1569:33:1569:42|Removing wire AWBURST_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1570:33:1570:41|Removing wire AWLOCK_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1571:33:1571:42|Removing wire AWCACHE_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1572:33:1572:41|Removing wire AWPROT_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1573:33:1573:42|Removing wire AWVALID_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1576:58:1576:63|Removing wire WID_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1577:33:1577:40|Removing wire WDATA_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1578:33:1578:40|Removing wire WSTRB_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1579:33:1579:40|Removing wire WLAST_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1580:33:1580:41|Removing wire WVALID_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1586:33:1586:41|Removing wire BREADY_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1588:58:1588:64|Removing wire ARID_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1589:23:1589:31|Removing wire ARADDR_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1590:33:1590:40|Removing wire ARLEN_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1591:33:1591:41|Removing wire ARSIZE_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1592:33:1592:42|Removing wire ARBURST_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1593:33:1593:41|Removing wire ARLOCK_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1594:33:1594:42|Removing wire ARCACHE_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1595:33:1595:41|Removing wire ARPROT_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1596:33:1596:42|Removing wire ARVALID_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1604:33:1604:41|Removing wire RREADY_S7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1608:58:1608:64|Removing wire AWID_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1609:23:1609:31|Removing wire AWADDR_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1610:33:1610:40|Removing wire AWLEN_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1611:33:1611:41|Removing wire AWSIZE_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1612:33:1612:42|Removing wire AWBURST_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1613:33:1613:41|Removing wire AWLOCK_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1614:33:1614:42|Removing wire AWCACHE_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1615:33:1615:41|Removing wire AWPROT_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1616:33:1616:42|Removing wire AWVALID_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1619:58:1619:63|Removing wire WID_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1620:33:1620:40|Removing wire WDATA_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1621:33:1621:40|Removing wire WSTRB_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1622:33:1622:40|Removing wire WLAST_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1623:33:1623:41|Removing wire WVALID_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1629:33:1629:41|Removing wire BREADY_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1631:58:1631:64|Removing wire ARID_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1632:23:1632:31|Removing wire ARADDR_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1633:33:1633:40|Removing wire ARLEN_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1634:33:1634:41|Removing wire ARSIZE_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1635:33:1635:42|Removing wire ARBURST_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1636:33:1636:41|Removing wire ARLOCK_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1637:33:1637:42|Removing wire ARCACHE_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1638:33:1638:41|Removing wire ARPROT_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1639:33:1639:42|Removing wire ARVALID_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1647:33:1647:41|Removing wire RREADY_S8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1651:58:1651:64|Removing wire AWID_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1652:23:1652:31|Removing wire AWADDR_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1653:33:1653:40|Removing wire AWLEN_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1654:33:1654:41|Removing wire AWSIZE_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1655:33:1655:42|Removing wire AWBURST_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1656:33:1656:41|Removing wire AWLOCK_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1657:33:1657:42|Removing wire AWCACHE_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1658:33:1658:41|Removing wire AWPROT_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1659:33:1659:42|Removing wire AWVALID_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1662:58:1662:63|Removing wire WID_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1663:33:1663:40|Removing wire WDATA_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1664:33:1664:40|Removing wire WSTRB_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1665:33:1665:40|Removing wire WLAST_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1666:33:1666:41|Removing wire WVALID_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1672:33:1672:41|Removing wire BREADY_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1674:58:1674:64|Removing wire ARID_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1675:23:1675:31|Removing wire ARADDR_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1676:33:1676:40|Removing wire ARLEN_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1677:33:1677:41|Removing wire ARSIZE_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1678:33:1678:42|Removing wire ARBURST_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1679:33:1679:41|Removing wire ARLOCK_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1680:33:1680:42|Removing wire ARCACHE_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1681:33:1681:41|Removing wire ARPROT_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1682:33:1682:42|Removing wire ARVALID_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1690:33:1690:41|Removing wire RREADY_S9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1694:58:1694:65|Removing wire AWID_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1695:23:1695:32|Removing wire AWADDR_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1696:33:1696:41|Removing wire AWLEN_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1697:33:1697:42|Removing wire AWSIZE_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1698:33:1698:43|Removing wire AWBURST_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1699:33:1699:42|Removing wire AWLOCK_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1700:33:1700:43|Removing wire AWCACHE_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1701:33:1701:42|Removing wire AWPROT_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1702:33:1702:43|Removing wire AWVALID_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1705:58:1705:64|Removing wire WID_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1706:33:1706:41|Removing wire WDATA_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1707:33:1707:41|Removing wire WSTRB_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1708:33:1708:41|Removing wire WLAST_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1709:33:1709:42|Removing wire WVALID_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1715:33:1715:42|Removing wire BREADY_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1717:58:1717:65|Removing wire ARID_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1718:23:1718:32|Removing wire ARADDR_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1719:33:1719:41|Removing wire ARLEN_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1720:33:1720:42|Removing wire ARSIZE_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1721:33:1721:43|Removing wire ARBURST_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1722:33:1722:42|Removing wire ARLOCK_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1723:33:1723:43|Removing wire ARCACHE_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1724:33:1724:42|Removing wire ARPROT_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1725:33:1725:43|Removing wire ARVALID_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1733:33:1733:42|Removing wire RREADY_S10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1737:58:1737:65|Removing wire AWID_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1738:23:1738:32|Removing wire AWADDR_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1739:33:1739:41|Removing wire AWLEN_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1740:33:1740:42|Removing wire AWSIZE_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1741:33:1741:43|Removing wire AWBURST_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1742:33:1742:42|Removing wire AWLOCK_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1743:33:1743:43|Removing wire AWCACHE_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1744:33:1744:42|Removing wire AWPROT_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1745:33:1745:43|Removing wire AWVALID_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1748:58:1748:64|Removing wire WID_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1749:33:1749:41|Removing wire WDATA_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1750:33:1750:41|Removing wire WSTRB_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1751:33:1751:41|Removing wire WLAST_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1752:33:1752:42|Removing wire WVALID_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1758:33:1758:42|Removing wire BREADY_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1760:58:1760:65|Removing wire ARID_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1761:23:1761:32|Removing wire ARADDR_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1762:33:1762:41|Removing wire ARLEN_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1763:33:1763:42|Removing wire ARSIZE_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1764:33:1764:43|Removing wire ARBURST_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1765:33:1765:42|Removing wire ARLOCK_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1766:33:1766:43|Removing wire ARCACHE_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1767:33:1767:42|Removing wire ARPROT_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1768:33:1768:43|Removing wire ARVALID_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1776:33:1776:42|Removing wire RREADY_S11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1780:58:1780:65|Removing wire AWID_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1781:23:1781:32|Removing wire AWADDR_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1782:33:1782:41|Removing wire AWLEN_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1783:33:1783:42|Removing wire AWSIZE_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1784:33:1784:43|Removing wire AWBURST_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1785:33:1785:42|Removing wire AWLOCK_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1786:33:1786:43|Removing wire AWCACHE_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1787:33:1787:42|Removing wire AWPROT_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1788:33:1788:43|Removing wire AWVALID_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1791:58:1791:64|Removing wire WID_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1792:33:1792:41|Removing wire WDATA_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1793:33:1793:41|Removing wire WSTRB_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1794:33:1794:41|Removing wire WLAST_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1795:33:1795:42|Removing wire WVALID_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1801:33:1801:42|Removing wire BREADY_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1803:58:1803:65|Removing wire ARID_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1804:23:1804:32|Removing wire ARADDR_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1805:33:1805:41|Removing wire ARLEN_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1806:33:1806:42|Removing wire ARSIZE_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1807:33:1807:43|Removing wire ARBURST_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1808:33:1808:42|Removing wire ARLOCK_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1809:33:1809:43|Removing wire ARCACHE_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1810:33:1810:42|Removing wire ARPROT_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1811:33:1811:43|Removing wire ARVALID_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1819:33:1819:42|Removing wire RREADY_S12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1823:58:1823:65|Removing wire AWID_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1824:23:1824:32|Removing wire AWADDR_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1825:33:1825:41|Removing wire AWLEN_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1826:33:1826:42|Removing wire AWSIZE_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1827:33:1827:43|Removing wire AWBURST_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1828:33:1828:42|Removing wire AWLOCK_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1829:33:1829:43|Removing wire AWCACHE_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1830:33:1830:42|Removing wire AWPROT_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1831:33:1831:43|Removing wire AWVALID_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1834:58:1834:64|Removing wire WID_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1835:33:1835:41|Removing wire WDATA_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1836:33:1836:41|Removing wire WSTRB_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1837:33:1837:41|Removing wire WLAST_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1838:33:1838:42|Removing wire WVALID_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1844:33:1844:42|Removing wire BREADY_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1846:58:1846:65|Removing wire ARID_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1847:23:1847:32|Removing wire ARADDR_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1848:33:1848:41|Removing wire ARLEN_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1849:33:1849:42|Removing wire ARSIZE_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1850:33:1850:43|Removing wire ARBURST_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1851:33:1851:42|Removing wire ARLOCK_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1852:33:1852:43|Removing wire ARCACHE_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1853:33:1853:42|Removing wire ARPROT_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1854:33:1854:43|Removing wire ARVALID_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1862:33:1862:42|Removing wire RREADY_S13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1866:58:1866:65|Removing wire AWID_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1867:23:1867:32|Removing wire AWADDR_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1868:33:1868:41|Removing wire AWLEN_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1869:33:1869:42|Removing wire AWSIZE_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1870:33:1870:43|Removing wire AWBURST_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1871:33:1871:42|Removing wire AWLOCK_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1872:33:1872:43|Removing wire AWCACHE_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1873:33:1873:42|Removing wire AWPROT_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1874:33:1874:43|Removing wire AWVALID_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1877:58:1877:64|Removing wire WID_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1878:33:1878:41|Removing wire WDATA_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1879:33:1879:41|Removing wire WSTRB_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1880:33:1880:41|Removing wire WLAST_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1881:33:1881:42|Removing wire WVALID_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1887:33:1887:42|Removing wire BREADY_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1889:58:1889:65|Removing wire ARID_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1890:23:1890:32|Removing wire ARADDR_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1891:33:1891:41|Removing wire ARLEN_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1892:33:1892:42|Removing wire ARSIZE_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1893:33:1893:43|Removing wire ARBURST_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1894:33:1894:42|Removing wire ARLOCK_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1895:33:1895:43|Removing wire ARCACHE_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1896:33:1896:42|Removing wire ARPROT_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1897:33:1897:43|Removing wire ARVALID_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1905:33:1905:42|Removing wire RREADY_S14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1909:58:1909:65|Removing wire AWID_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1910:23:1910:32|Removing wire AWADDR_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1911:33:1911:41|Removing wire AWLEN_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1912:33:1912:42|Removing wire AWSIZE_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1913:33:1913:43|Removing wire AWBURST_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1914:33:1914:42|Removing wire AWLOCK_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1915:33:1915:43|Removing wire AWCACHE_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1916:33:1916:42|Removing wire AWPROT_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1917:33:1917:43|Removing wire AWVALID_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1920:58:1920:64|Removing wire WID_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1921:33:1921:41|Removing wire WDATA_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1922:33:1922:41|Removing wire WSTRB_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1923:33:1923:41|Removing wire WLAST_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1924:33:1924:42|Removing wire WVALID_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1930:33:1930:42|Removing wire BREADY_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1932:58:1932:65|Removing wire ARID_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1933:23:1933:32|Removing wire ARADDR_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1934:33:1934:41|Removing wire ARLEN_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1935:33:1935:42|Removing wire ARSIZE_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1936:33:1936:43|Removing wire ARBURST_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1937:33:1937:42|Removing wire ARLOCK_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1938:33:1938:43|Removing wire ARCACHE_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1939:33:1939:42|Removing wire ARPROT_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1940:33:1940:43|Removing wire ARVALID_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1948:33:1948:42|Removing wire RREADY_S15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1952:58:1952:65|Removing wire AWID_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1953:23:1953:32|Removing wire AWADDR_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1954:33:1954:41|Removing wire AWLEN_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1955:33:1955:42|Removing wire AWSIZE_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1956:33:1956:43|Removing wire AWBURST_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1957:33:1957:42|Removing wire AWLOCK_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1958:33:1958:43|Removing wire AWCACHE_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1959:33:1959:42|Removing wire AWPROT_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1960:33:1960:43|Removing wire AWVALID_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1963:58:1963:64|Removing wire WID_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1964:33:1964:41|Removing wire WDATA_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1965:33:1965:41|Removing wire WSTRB_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1966:33:1966:41|Removing wire WLAST_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1967:33:1967:42|Removing wire WVALID_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1973:33:1973:42|Removing wire BREADY_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1975:58:1975:65|Removing wire ARID_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1976:23:1976:32|Removing wire ARADDR_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1977:33:1977:41|Removing wire ARLEN_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1978:33:1978:42|Removing wire ARSIZE_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1979:33:1979:43|Removing wire ARBURST_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1980:33:1980:42|Removing wire ARLOCK_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1981:33:1981:43|Removing wire ARCACHE_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1982:33:1982:42|Removing wire ARPROT_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1983:33:1983:43|Removing wire ARVALID_S16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1996:33:1996:43|Removing wire AWREADY_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1997:33:1997:43|Removing wire AWREADY_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1998:33:1998:43|Removing wire AWREADY_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1999:33:1999:43|Removing wire AWREADY_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2000:33:2000:42|Removing wire WREADY_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2001:33:2001:42|Removing wire WREADY_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2002:33:2002:42|Removing wire WREADY_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2003:33:2003:42|Removing wire WREADY_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2004:33:2004:43|Removing wire ARREADY_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2005:33:2005:43|Removing wire ARREADY_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2006:33:2006:43|Removing wire ARREADY_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2007:33:2007:43|Removing wire ARREADY_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2009:33:2009:42|Removing wire BREADY_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2010:33:2010:42|Removing wire BREADY_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2011:33:2011:42|Removing wire BREADY_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2012:33:2012:42|Removing wire BREADY_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2013:33:2013:42|Removing wire RREADY_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2014:33:2014:42|Removing wire RREADY_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2015:33:2015:42|Removing wire RREADY_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2016:33:2016:42|Removing wire RREADY_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2019:39:2019:48|Removing wire BVALID_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2020:39:2020:48|Removing wire BVALID_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2021:39:2021:48|Removing wire BVALID_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2022:39:2022:48|Removing wire BVALID_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2025:56:2025:63|Removing wire AWID_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2026:21:2026:30|Removing wire AWADDR_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2027:31:2027:39|Removing wire AWLEN_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2028:31:2028:40|Removing wire AWSIZE_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2029:31:2029:41|Removing wire AWBURST_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2030:31:2030:40|Removing wire AWLOCK_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2031:31:2031:41|Removing wire AWCACHE_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2032:31:2032:40|Removing wire AWPROT_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2033:31:2033:41|Removing wire AWVALID_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2036:56:2036:62|Removing wire WID_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2037:31:2037:39|Removing wire WDATA_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2038:31:2038:39|Removing wire WSTRB_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2039:31:2039:39|Removing wire WLAST_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2040:31:2040:40|Removing wire WVALID_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2042:31:2042:40|Removing wire BREADY_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2044:56:2044:63|Removing wire ARID_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2045:21:2045:30|Removing wire ARADDR_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2046:31:2046:39|Removing wire ARLEN_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2047:31:2047:40|Removing wire ARSIZE_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2048:31:2048:41|Removing wire ARBURST_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2049:31:2049:40|Removing wire ARLOCK_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2050:31:2050:41|Removing wire ARCACHE_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2051:31:2051:40|Removing wire ARPROT_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2052:31:2052:41|Removing wire ARVALID_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2055:32:2055:41|Removing wire RREADY_IS0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2057:56:2057:63|Removing wire AWID_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2058:21:2058:30|Removing wire AWADDR_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2059:31:2059:39|Removing wire AWLEN_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2060:31:2060:40|Removing wire AWSIZE_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2061:31:2061:41|Removing wire AWBURST_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2062:31:2062:40|Removing wire AWLOCK_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2063:31:2063:41|Removing wire AWCACHE_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2064:31:2064:40|Removing wire AWPROT_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2065:31:2065:41|Removing wire AWVALID_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2068:56:2068:62|Removing wire WID_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2069:31:2069:39|Removing wire WDATA_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2070:31:2070:39|Removing wire WSTRB_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2071:31:2071:39|Removing wire WLAST_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2072:31:2072:40|Removing wire WVALID_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2074:31:2074:40|Removing wire BREADY_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2076:56:2076:63|Removing wire ARID_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2077:21:2077:30|Removing wire ARADDR_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2078:31:2078:39|Removing wire ARLEN_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2079:31:2079:40|Removing wire ARSIZE_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2080:31:2080:41|Removing wire ARBURST_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2081:31:2081:40|Removing wire ARLOCK_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2082:31:2082:41|Removing wire ARCACHE_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2083:31:2083:40|Removing wire ARPROT_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2084:31:2084:41|Removing wire ARVALID_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2087:32:2087:41|Removing wire RREADY_IS1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2089:56:2089:63|Removing wire AWID_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2090:21:2090:30|Removing wire AWADDR_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2091:31:2091:39|Removing wire AWLEN_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2092:31:2092:40|Removing wire AWSIZE_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2093:31:2093:41|Removing wire AWBURST_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2094:31:2094:40|Removing wire AWLOCK_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2095:31:2095:41|Removing wire AWCACHE_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2096:31:2096:40|Removing wire AWPROT_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2097:31:2097:41|Removing wire AWVALID_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2100:56:2100:62|Removing wire WID_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2101:31:2101:39|Removing wire WDATA_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2102:31:2102:39|Removing wire WSTRB_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2103:31:2103:39|Removing wire WLAST_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2104:31:2104:40|Removing wire WVALID_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2106:31:2106:40|Removing wire BREADY_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2108:56:2108:63|Removing wire ARID_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2109:21:2109:30|Removing wire ARADDR_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2110:31:2110:39|Removing wire ARLEN_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2111:31:2111:40|Removing wire ARSIZE_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2112:31:2112:41|Removing wire ARBURST_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2113:31:2113:40|Removing wire ARLOCK_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2114:31:2114:41|Removing wire ARCACHE_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2115:31:2115:40|Removing wire ARPROT_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2116:31:2116:41|Removing wire ARVALID_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2119:32:2119:41|Removing wire RREADY_IS2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2121:56:2121:63|Removing wire AWID_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2122:21:2122:30|Removing wire AWADDR_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2123:31:2123:39|Removing wire AWLEN_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2124:31:2124:40|Removing wire AWSIZE_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2125:31:2125:41|Removing wire AWBURST_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2126:31:2126:40|Removing wire AWLOCK_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2127:31:2127:41|Removing wire AWCACHE_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2128:31:2128:40|Removing wire AWPROT_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2129:31:2129:41|Removing wire AWVALID_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2132:56:2132:62|Removing wire WID_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2133:31:2133:39|Removing wire WDATA_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2134:31:2134:39|Removing wire WSTRB_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2135:31:2135:39|Removing wire WLAST_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2136:31:2136:40|Removing wire WVALID_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2138:31:2138:40|Removing wire BREADY_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2140:56:2140:63|Removing wire ARID_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2141:21:2141:30|Removing wire ARADDR_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2142:31:2142:39|Removing wire ARLEN_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2143:31:2143:40|Removing wire ARSIZE_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2144:31:2144:41|Removing wire ARBURST_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2145:31:2145:40|Removing wire ARLOCK_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2146:31:2146:41|Removing wire ARCACHE_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2147:31:2147:40|Removing wire ARPROT_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2148:31:2148:41|Removing wire ARVALID_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2151:32:2151:41|Removing wire RREADY_IS3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2153:56:2153:63|Removing wire AWID_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2154:21:2154:30|Removing wire AWADDR_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2155:31:2155:39|Removing wire AWLEN_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2156:31:2156:40|Removing wire AWSIZE_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2157:31:2157:41|Removing wire AWBURST_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2158:31:2158:40|Removing wire AWLOCK_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2159:31:2159:41|Removing wire AWCACHE_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2160:31:2160:40|Removing wire AWPROT_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2161:31:2161:41|Removing wire AWVALID_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2164:56:2164:62|Removing wire WID_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2165:31:2165:39|Removing wire WDATA_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2166:31:2166:39|Removing wire WSTRB_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2167:31:2167:39|Removing wire WLAST_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2168:31:2168:40|Removing wire WVALID_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2170:31:2170:40|Removing wire BREADY_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2172:56:2172:63|Removing wire ARID_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2173:21:2173:30|Removing wire ARADDR_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2174:31:2174:39|Removing wire ARLEN_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2175:31:2175:40|Removing wire ARSIZE_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2176:31:2176:41|Removing wire ARBURST_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2177:31:2177:40|Removing wire ARLOCK_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2178:31:2178:41|Removing wire ARCACHE_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2179:31:2179:40|Removing wire ARPROT_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2180:31:2180:41|Removing wire ARVALID_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2183:32:2183:41|Removing wire RREADY_IS4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2185:56:2185:63|Removing wire AWID_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2186:21:2186:30|Removing wire AWADDR_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2187:31:2187:39|Removing wire AWLEN_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2188:31:2188:40|Removing wire AWSIZE_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2189:31:2189:41|Removing wire AWBURST_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2190:31:2190:40|Removing wire AWLOCK_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2191:31:2191:41|Removing wire AWCACHE_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2192:31:2192:40|Removing wire AWPROT_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2193:31:2193:41|Removing wire AWVALID_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2196:56:2196:62|Removing wire WID_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2197:31:2197:39|Removing wire WDATA_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2198:31:2198:39|Removing wire WSTRB_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2199:31:2199:39|Removing wire WLAST_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2200:31:2200:40|Removing wire WVALID_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2202:31:2202:40|Removing wire BREADY_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2204:56:2204:63|Removing wire ARID_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2205:21:2205:30|Removing wire ARADDR_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2206:31:2206:39|Removing wire ARLEN_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2207:31:2207:40|Removing wire ARSIZE_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2208:31:2208:41|Removing wire ARBURST_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2209:31:2209:40|Removing wire ARLOCK_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2210:31:2210:41|Removing wire ARCACHE_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2211:31:2211:40|Removing wire ARPROT_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2212:31:2212:41|Removing wire ARVALID_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2215:32:2215:41|Removing wire RREADY_IS5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2217:56:2217:63|Removing wire AWID_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2218:21:2218:30|Removing wire AWADDR_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2219:31:2219:39|Removing wire AWLEN_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2220:31:2220:40|Removing wire AWSIZE_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2221:31:2221:41|Removing wire AWBURST_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2222:31:2222:40|Removing wire AWLOCK_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2223:31:2223:41|Removing wire AWCACHE_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2224:31:2224:40|Removing wire AWPROT_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2225:31:2225:41|Removing wire AWVALID_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2228:56:2228:62|Removing wire WID_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2229:31:2229:39|Removing wire WDATA_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2230:31:2230:39|Removing wire WSTRB_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2231:31:2231:39|Removing wire WLAST_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2232:31:2232:40|Removing wire WVALID_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2234:31:2234:40|Removing wire BREADY_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2236:56:2236:63|Removing wire ARID_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2237:21:2237:30|Removing wire ARADDR_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2238:31:2238:39|Removing wire ARLEN_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2239:31:2239:40|Removing wire ARSIZE_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2240:31:2240:41|Removing wire ARBURST_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2241:31:2241:40|Removing wire ARLOCK_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2242:31:2242:41|Removing wire ARCACHE_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2243:31:2243:40|Removing wire ARPROT_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2244:31:2244:41|Removing wire ARVALID_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2247:32:2247:41|Removing wire RREADY_IS6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2249:56:2249:63|Removing wire AWID_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2250:21:2250:30|Removing wire AWADDR_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2251:31:2251:39|Removing wire AWLEN_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2252:31:2252:40|Removing wire AWSIZE_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2253:31:2253:41|Removing wire AWBURST_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2254:31:2254:40|Removing wire AWLOCK_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2255:31:2255:41|Removing wire AWCACHE_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2256:31:2256:40|Removing wire AWPROT_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2257:31:2257:41|Removing wire AWVALID_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2260:56:2260:62|Removing wire WID_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2261:31:2261:39|Removing wire WDATA_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2262:31:2262:39|Removing wire WSTRB_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2263:31:2263:39|Removing wire WLAST_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2264:31:2264:40|Removing wire WVALID_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2266:31:2266:40|Removing wire BREADY_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2268:56:2268:63|Removing wire ARID_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2269:21:2269:30|Removing wire ARADDR_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2270:31:2270:39|Removing wire ARLEN_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2271:31:2271:40|Removing wire ARSIZE_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2272:31:2272:41|Removing wire ARBURST_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2273:31:2273:40|Removing wire ARLOCK_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2274:31:2274:41|Removing wire ARCACHE_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2275:31:2275:40|Removing wire ARPROT_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2276:31:2276:41|Removing wire ARVALID_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2279:32:2279:41|Removing wire RREADY_IS7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2281:56:2281:63|Removing wire AWID_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2282:21:2282:30|Removing wire AWADDR_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2283:31:2283:39|Removing wire AWLEN_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2284:31:2284:40|Removing wire AWSIZE_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2285:31:2285:41|Removing wire AWBURST_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2286:31:2286:40|Removing wire AWLOCK_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2287:31:2287:41|Removing wire AWCACHE_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2288:31:2288:40|Removing wire AWPROT_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2289:31:2289:41|Removing wire AWVALID_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2292:56:2292:62|Removing wire WID_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2293:31:2293:39|Removing wire WDATA_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2294:31:2294:39|Removing wire WSTRB_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2295:31:2295:39|Removing wire WLAST_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2296:31:2296:40|Removing wire WVALID_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2298:31:2298:40|Removing wire BREADY_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2300:56:2300:63|Removing wire ARID_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2301:21:2301:30|Removing wire ARADDR_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2302:31:2302:39|Removing wire ARLEN_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2303:31:2303:40|Removing wire ARSIZE_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2304:31:2304:41|Removing wire ARBURST_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2305:31:2305:40|Removing wire ARLOCK_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2306:31:2306:41|Removing wire ARCACHE_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2307:31:2307:40|Removing wire ARPROT_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2308:31:2308:41|Removing wire ARVALID_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2311:32:2311:41|Removing wire RREADY_IS8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2313:56:2313:63|Removing wire AWID_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2314:21:2314:30|Removing wire AWADDR_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2315:31:2315:39|Removing wire AWLEN_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2316:31:2316:40|Removing wire AWSIZE_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2317:31:2317:41|Removing wire AWBURST_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2318:31:2318:40|Removing wire AWLOCK_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2319:31:2319:41|Removing wire AWCACHE_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2320:31:2320:40|Removing wire AWPROT_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2321:31:2321:41|Removing wire AWVALID_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2324:56:2324:62|Removing wire WID_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2325:31:2325:39|Removing wire WDATA_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2326:31:2326:39|Removing wire WSTRB_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2327:31:2327:39|Removing wire WLAST_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2328:31:2328:40|Removing wire WVALID_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2330:31:2330:40|Removing wire BREADY_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2332:56:2332:63|Removing wire ARID_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2333:21:2333:30|Removing wire ARADDR_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2334:31:2334:39|Removing wire ARLEN_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2335:31:2335:40|Removing wire ARSIZE_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2336:31:2336:41|Removing wire ARBURST_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2337:31:2337:40|Removing wire ARLOCK_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2338:31:2338:41|Removing wire ARCACHE_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2339:31:2339:40|Removing wire ARPROT_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2340:31:2340:41|Removing wire ARVALID_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2343:32:2343:41|Removing wire RREADY_IS9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2345:56:2345:64|Removing wire AWID_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2346:21:2346:31|Removing wire AWADDR_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2347:31:2347:40|Removing wire AWLEN_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2348:31:2348:41|Removing wire AWSIZE_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2349:31:2349:42|Removing wire AWBURST_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2350:31:2350:41|Removing wire AWLOCK_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2351:31:2351:42|Removing wire AWCACHE_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2352:31:2352:41|Removing wire AWPROT_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2353:31:2353:42|Removing wire AWVALID_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2356:56:2356:63|Removing wire WID_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2357:31:2357:40|Removing wire WDATA_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2358:31:2358:40|Removing wire WSTRB_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2359:31:2359:40|Removing wire WLAST_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2360:31:2360:41|Removing wire WVALID_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2362:31:2362:41|Removing wire BREADY_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2364:56:2364:64|Removing wire ARID_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2365:21:2365:31|Removing wire ARADDR_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2366:31:2366:40|Removing wire ARLEN_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2367:31:2367:41|Removing wire ARSIZE_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2368:31:2368:42|Removing wire ARBURST_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2369:31:2369:41|Removing wire ARLOCK_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2370:31:2370:42|Removing wire ARCACHE_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2371:31:2371:41|Removing wire ARPROT_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2372:31:2372:42|Removing wire ARVALID_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2375:32:2375:42|Removing wire RREADY_IS10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2377:56:2377:64|Removing wire AWID_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2378:21:2378:31|Removing wire AWADDR_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2379:31:2379:40|Removing wire AWLEN_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2380:31:2380:41|Removing wire AWSIZE_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2381:31:2381:42|Removing wire AWBURST_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2382:31:2382:41|Removing wire AWLOCK_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2383:31:2383:42|Removing wire AWCACHE_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2384:31:2384:41|Removing wire AWPROT_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2385:31:2385:42|Removing wire AWVALID_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2388:56:2388:63|Removing wire WID_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2389:31:2389:40|Removing wire WDATA_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2390:31:2390:40|Removing wire WSTRB_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2391:31:2391:40|Removing wire WLAST_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2392:31:2392:41|Removing wire WVALID_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2394:31:2394:41|Removing wire BREADY_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2396:56:2396:64|Removing wire ARID_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2397:21:2397:31|Removing wire ARADDR_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2398:31:2398:40|Removing wire ARLEN_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2399:31:2399:41|Removing wire ARSIZE_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2400:31:2400:42|Removing wire ARBURST_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2401:31:2401:41|Removing wire ARLOCK_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2402:31:2402:42|Removing wire ARCACHE_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2403:31:2403:41|Removing wire ARPROT_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2404:31:2404:42|Removing wire ARVALID_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2407:32:2407:42|Removing wire RREADY_IS11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2409:56:2409:64|Removing wire AWID_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2410:21:2410:31|Removing wire AWADDR_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2411:31:2411:40|Removing wire AWLEN_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2412:31:2412:41|Removing wire AWSIZE_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2413:31:2413:42|Removing wire AWBURST_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2414:31:2414:41|Removing wire AWLOCK_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2415:31:2415:42|Removing wire AWCACHE_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2416:31:2416:41|Removing wire AWPROT_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2417:31:2417:42|Removing wire AWVALID_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2420:56:2420:63|Removing wire WID_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2421:31:2421:40|Removing wire WDATA_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2422:31:2422:40|Removing wire WSTRB_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2423:31:2423:40|Removing wire WLAST_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2424:31:2424:41|Removing wire WVALID_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2426:31:2426:41|Removing wire BREADY_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2428:56:2428:64|Removing wire ARID_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2429:21:2429:31|Removing wire ARADDR_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2430:31:2430:40|Removing wire ARLEN_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2431:31:2431:41|Removing wire ARSIZE_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2432:31:2432:42|Removing wire ARBURST_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2433:31:2433:41|Removing wire ARLOCK_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2434:31:2434:42|Removing wire ARCACHE_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2435:31:2435:41|Removing wire ARPROT_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2436:31:2436:42|Removing wire ARVALID_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2439:32:2439:42|Removing wire RREADY_IS12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2441:56:2441:64|Removing wire AWID_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2442:21:2442:31|Removing wire AWADDR_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2443:31:2443:40|Removing wire AWLEN_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2444:31:2444:41|Removing wire AWSIZE_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2445:31:2445:42|Removing wire AWBURST_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2446:31:2446:41|Removing wire AWLOCK_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2447:31:2447:42|Removing wire AWCACHE_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2448:31:2448:41|Removing wire AWPROT_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2449:31:2449:42|Removing wire AWVALID_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2452:56:2452:63|Removing wire WID_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2453:31:2453:40|Removing wire WDATA_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2454:31:2454:40|Removing wire WSTRB_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2455:31:2455:40|Removing wire WLAST_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2456:31:2456:41|Removing wire WVALID_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2458:31:2458:41|Removing wire BREADY_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2460:56:2460:64|Removing wire ARID_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2461:21:2461:31|Removing wire ARADDR_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2462:31:2462:40|Removing wire ARLEN_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2463:31:2463:41|Removing wire ARSIZE_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2464:31:2464:42|Removing wire ARBURST_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2465:31:2465:41|Removing wire ARLOCK_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2466:31:2466:42|Removing wire ARCACHE_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2467:31:2467:41|Removing wire ARPROT_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2468:31:2468:42|Removing wire ARVALID_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2471:32:2471:42|Removing wire RREADY_IS13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2473:56:2473:64|Removing wire AWID_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2474:21:2474:31|Removing wire AWADDR_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2475:31:2475:40|Removing wire AWLEN_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2476:31:2476:41|Removing wire AWSIZE_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2477:31:2477:42|Removing wire AWBURST_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2478:31:2478:41|Removing wire AWLOCK_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2479:31:2479:42|Removing wire AWCACHE_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2480:31:2480:41|Removing wire AWPROT_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2481:31:2481:42|Removing wire AWVALID_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2484:56:2484:63|Removing wire WID_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2485:31:2485:40|Removing wire WDATA_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2486:31:2486:40|Removing wire WSTRB_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2487:31:2487:40|Removing wire WLAST_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2488:31:2488:41|Removing wire WVALID_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2490:31:2490:41|Removing wire BREADY_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2492:56:2492:64|Removing wire ARID_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2493:21:2493:31|Removing wire ARADDR_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2494:31:2494:40|Removing wire ARLEN_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2495:31:2495:41|Removing wire ARSIZE_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2496:31:2496:42|Removing wire ARBURST_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2497:31:2497:41|Removing wire ARLOCK_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2498:31:2498:42|Removing wire ARCACHE_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2499:31:2499:41|Removing wire ARPROT_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2500:31:2500:42|Removing wire ARVALID_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2503:32:2503:42|Removing wire RREADY_IS14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2505:56:2505:64|Removing wire AWID_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2506:21:2506:31|Removing wire AWADDR_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2507:31:2507:40|Removing wire AWLEN_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2508:31:2508:41|Removing wire AWSIZE_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2509:31:2509:42|Removing wire AWBURST_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2510:31:2510:41|Removing wire AWLOCK_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2511:31:2511:42|Removing wire AWCACHE_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2512:31:2512:41|Removing wire AWPROT_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2513:31:2513:42|Removing wire AWVALID_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2516:56:2516:63|Removing wire WID_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2517:31:2517:40|Removing wire WDATA_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2518:31:2518:40|Removing wire WSTRB_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2519:31:2519:40|Removing wire WLAST_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2520:31:2520:41|Removing wire WVALID_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2522:31:2522:41|Removing wire BREADY_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2524:56:2524:64|Removing wire ARID_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2525:21:2525:31|Removing wire ARADDR_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2526:31:2526:40|Removing wire ARLEN_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2527:31:2527:41|Removing wire ARSIZE_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2528:31:2528:42|Removing wire ARBURST_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2529:31:2529:41|Removing wire ARLOCK_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2530:31:2530:42|Removing wire ARCACHE_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2531:31:2531:41|Removing wire ARPROT_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2532:31:2532:42|Removing wire ARVALID_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2535:32:2535:42|Removing wire RREADY_IS15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2537:56:2537:64|Removing wire AWID_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2538:21:2538:31|Removing wire AWADDR_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2539:31:2539:40|Removing wire AWLEN_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2540:31:2540:41|Removing wire AWSIZE_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2541:31:2541:42|Removing wire AWBURST_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2542:31:2542:41|Removing wire AWLOCK_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2543:31:2543:42|Removing wire AWCACHE_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2544:31:2544:41|Removing wire AWPROT_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2545:31:2545:42|Removing wire AWVALID_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2548:56:2548:63|Removing wire WID_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2549:31:2549:40|Removing wire WDATA_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2550:31:2550:40|Removing wire WSTRB_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2551:31:2551:40|Removing wire WLAST_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2552:31:2552:41|Removing wire WVALID_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2554:31:2554:41|Removing wire BREADY_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2556:56:2556:64|Removing wire ARID_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2557:21:2557:31|Removing wire ARADDR_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2558:31:2558:40|Removing wire ARLEN_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2559:31:2559:41|Removing wire ARSIZE_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2560:31:2560:42|Removing wire ARBURST_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2561:31:2561:41|Removing wire ARLOCK_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2562:31:2562:42|Removing wire ARCACHE_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2563:31:2563:41|Removing wire ARPROT_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2564:31:2564:42|Removing wire ARVALID_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2567:32:2567:42|Removing wire RREADY_IS16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2572:39:2572:46|Removing wire AWID_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2573:22:2573:31|Removing wire AWADDR_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2574:32:2574:40|Removing wire AWLEN_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2575:32:2575:41|Removing wire AWSIZE_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2576:32:2576:42|Removing wire AWBURST_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2577:32:2577:41|Removing wire AWLOCK_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2578:32:2578:42|Removing wire AWCACHE_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2579:32:2579:41|Removing wire AWPROT_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2580:32:2580:42|Removing wire AWVALID_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2582:39:2582:45|Removing wire WID_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2583:32:2583:40|Removing wire WDATA_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2584:32:2584:40|Removing wire WSTRB_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2585:32:2585:40|Removing wire WLAST_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2586:32:2586:41|Removing wire WVALID_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2588:39:2588:46|Removing wire ARID_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2589:21:2589:30|Removing wire ARADDR_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2590:31:2590:39|Removing wire ARLEN_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2591:31:2591:40|Removing wire ARSIZE_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2592:31:2592:41|Removing wire ARBURST_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2593:31:2593:40|Removing wire ARLOCK_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2594:31:2594:41|Removing wire ARCACHE_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2595:31:2595:40|Removing wire ARPROT_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2596:31:2596:41|Removing wire ARVALID_MI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2598:31:2598:39|Removing wire BRESP_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2599:39:2599:45|Removing wire BID_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2601:39:2601:45|Removing wire RID_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2602:30:2602:38|Removing wire RDATA_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2603:30:2603:38|Removing wire RRESP_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2604:30:2604:39|Removing wire RVALID_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2605:30:2605:38|Removing wire RLAST_IM0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2610:39:2610:46|Removing wire AWID_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2611:22:2611:31|Removing wire AWADDR_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2612:32:2612:40|Removing wire AWLEN_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2613:32:2613:41|Removing wire AWSIZE_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2614:32:2614:42|Removing wire AWBURST_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2615:32:2615:41|Removing wire AWLOCK_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2616:32:2616:42|Removing wire AWCACHE_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2617:32:2617:41|Removing wire AWPROT_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2618:32:2618:42|Removing wire AWVALID_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2620:39:2620:45|Removing wire WID_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2621:32:2621:40|Removing wire WDATA_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2622:32:2622:40|Removing wire WSTRB_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2623:32:2623:40|Removing wire WLAST_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2624:32:2624:41|Removing wire WVALID_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2626:39:2626:46|Removing wire ARID_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2627:21:2627:30|Removing wire ARADDR_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2628:31:2628:39|Removing wire ARLEN_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2629:31:2629:40|Removing wire ARSIZE_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2630:31:2630:41|Removing wire ARBURST_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2631:31:2631:40|Removing wire ARLOCK_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2632:31:2632:41|Removing wire ARCACHE_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2633:31:2633:40|Removing wire ARPROT_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2634:31:2634:41|Removing wire ARVALID_MI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2636:31:2636:39|Removing wire BRESP_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2637:39:2637:45|Removing wire BID_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2639:39:2639:45|Removing wire RID_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2640:30:2640:38|Removing wire RDATA_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2641:30:2641:38|Removing wire RRESP_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2642:30:2642:39|Removing wire RVALID_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2643:30:2643:38|Removing wire RLAST_IM1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2647:39:2647:46|Removing wire AWID_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2648:22:2648:31|Removing wire AWADDR_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2649:32:2649:40|Removing wire AWLEN_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2650:32:2650:41|Removing wire AWSIZE_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2651:32:2651:42|Removing wire AWBURST_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2652:32:2652:41|Removing wire AWLOCK_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2653:32:2653:42|Removing wire AWCACHE_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2654:32:2654:41|Removing wire AWPROT_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2655:32:2655:42|Removing wire AWVALID_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2657:39:2657:45|Removing wire WID_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2658:32:2658:40|Removing wire WDATA_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2659:32:2659:40|Removing wire WSTRB_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2660:32:2660:40|Removing wire WLAST_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2661:32:2661:41|Removing wire WVALID_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2663:39:2663:46|Removing wire ARID_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2664:21:2664:30|Removing wire ARADDR_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2665:31:2665:39|Removing wire ARLEN_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2666:31:2666:40|Removing wire ARSIZE_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2667:31:2667:41|Removing wire ARBURST_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2668:31:2668:40|Removing wire ARLOCK_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2669:31:2669:41|Removing wire ARCACHE_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2670:31:2670:40|Removing wire ARPROT_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2671:31:2671:41|Removing wire ARVALID_MI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2673:31:2673:39|Removing wire BRESP_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2674:39:2674:45|Removing wire BID_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2676:39:2676:45|Removing wire RID_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2677:30:2677:38|Removing wire RDATA_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2678:30:2678:38|Removing wire RRESP_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2679:30:2679:39|Removing wire RVALID_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2680:30:2680:38|Removing wire RLAST_IM2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2684:39:2684:46|Removing wire AWID_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2685:22:2685:31|Removing wire AWADDR_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2686:32:2686:40|Removing wire AWLEN_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2687:32:2687:41|Removing wire AWSIZE_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2688:32:2688:42|Removing wire AWBURST_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2689:32:2689:41|Removing wire AWLOCK_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2690:32:2690:42|Removing wire AWCACHE_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2691:32:2691:41|Removing wire AWPROT_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2692:32:2692:42|Removing wire AWVALID_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2694:39:2694:45|Removing wire WID_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2695:32:2695:40|Removing wire WDATA_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2696:32:2696:40|Removing wire WSTRB_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2697:32:2697:40|Removing wire WLAST_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2698:32:2698:41|Removing wire WVALID_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2700:39:2700:46|Removing wire ARID_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2701:21:2701:30|Removing wire ARADDR_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2702:31:2702:39|Removing wire ARLEN_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2703:31:2703:40|Removing wire ARSIZE_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2704:31:2704:41|Removing wire ARBURST_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2705:31:2705:40|Removing wire ARLOCK_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2706:31:2706:41|Removing wire ARCACHE_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2707:31:2707:40|Removing wire ARPROT_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2708:31:2708:41|Removing wire ARVALID_MI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2710:31:2710:39|Removing wire BRESP_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2711:39:2711:45|Removing wire BID_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2713:39:2713:45|Removing wire RID_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2714:30:2714:38|Removing wire RDATA_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2715:30:2715:38|Removing wire RRESP_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2716:30:2716:39|Removing wire RVALID_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":2717:30:2717:38|Removing wire RLAST_IM3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3263:31:3263:41|Removing wire AWREADY_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3264:31:3264:41|Removing wire AWREADY_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3265:31:3265:41|Removing wire AWREADY_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3266:31:3266:41|Removing wire AWREADY_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3267:31:3267:41|Removing wire AWREADY_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3268:31:3268:41|Removing wire AWREADY_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3269:31:3269:41|Removing wire AWREADY_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3270:31:3270:41|Removing wire AWREADY_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3271:31:3271:41|Removing wire AWREADY_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3272:31:3272:41|Removing wire AWREADY_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3273:31:3273:42|Removing wire AWREADY_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3274:31:3274:42|Removing wire AWREADY_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3275:31:3275:42|Removing wire AWREADY_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3276:31:3276:42|Removing wire AWREADY_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3277:31:3277:42|Removing wire AWREADY_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3278:31:3278:42|Removing wire AWREADY_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3279:31:3279:42|Removing wire AWREADY_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3281:31:3281:40|Removing wire WREADY_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3282:31:3282:40|Removing wire WREADY_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3283:31:3283:40|Removing wire WREADY_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3284:31:3284:40|Removing wire WREADY_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3285:31:3285:40|Removing wire WREADY_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3286:31:3286:40|Removing wire WREADY_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3287:31:3287:40|Removing wire WREADY_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3288:31:3288:40|Removing wire WREADY_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3289:31:3289:40|Removing wire WREADY_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3290:31:3290:40|Removing wire WREADY_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3291:31:3291:41|Removing wire WREADY_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3292:31:3292:41|Removing wire WREADY_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3293:31:3293:41|Removing wire WREADY_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3294:31:3294:41|Removing wire WREADY_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3295:31:3295:41|Removing wire WREADY_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3296:31:3296:41|Removing wire WREADY_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3297:31:3297:41|Removing wire WREADY_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3299:31:3299:41|Removing wire ARREADY_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3300:31:3300:41|Removing wire ARREADY_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3301:31:3301:41|Removing wire ARREADY_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3302:31:3302:41|Removing wire ARREADY_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3303:31:3303:41|Removing wire ARREADY_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3304:31:3304:41|Removing wire ARREADY_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3305:31:3305:41|Removing wire ARREADY_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3306:31:3306:41|Removing wire ARREADY_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3307:31:3307:41|Removing wire ARREADY_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3308:31:3308:41|Removing wire ARREADY_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3309:31:3309:42|Removing wire ARREADY_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3310:31:3310:42|Removing wire ARREADY_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3311:31:3311:42|Removing wire ARREADY_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3312:31:3312:42|Removing wire ARREADY_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3313:31:3313:42|Removing wire ARREADY_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3314:31:3314:42|Removing wire ARREADY_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3315:31:3315:42|Removing wire ARREADY_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3388:55:3388:61|Removing wire BID_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3389:30:3389:38|Removing wire BRESP_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3390:30:3390:39|Removing wire BVALID_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3391:55:3391:61|Removing wire RID_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3392:30:3392:38|Removing wire RDATA_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3393:30:3393:38|Removing wire RRESP_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3394:30:3394:38|Removing wire RLAST_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3395:30:3395:39|Removing wire RVALID_SI0, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3397:55:3397:61|Removing wire BID_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3398:30:3398:38|Removing wire BRESP_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3399:30:3399:39|Removing wire BVALID_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3400:55:3400:61|Removing wire RID_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3401:30:3401:38|Removing wire RDATA_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3402:30:3402:38|Removing wire RRESP_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3403:30:3403:38|Removing wire RLAST_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3404:30:3404:39|Removing wire RVALID_SI1, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3406:55:3406:61|Removing wire BID_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3407:30:3407:38|Removing wire BRESP_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3408:30:3408:39|Removing wire BVALID_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3409:55:3409:61|Removing wire RID_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3410:30:3410:38|Removing wire RDATA_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3411:30:3411:38|Removing wire RRESP_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3412:30:3412:38|Removing wire RLAST_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3413:30:3413:39|Removing wire RVALID_SI2, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3415:55:3415:61|Removing wire BID_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3416:30:3416:38|Removing wire BRESP_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3417:30:3417:39|Removing wire BVALID_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3418:55:3418:61|Removing wire RID_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3419:30:3419:38|Removing wire RDATA_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3420:30:3420:38|Removing wire RRESP_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3421:30:3421:38|Removing wire RLAST_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3422:30:3422:39|Removing wire RVALID_SI3, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3424:55:3424:61|Removing wire BID_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3425:30:3425:38|Removing wire BRESP_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3426:30:3426:39|Removing wire BVALID_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3427:55:3427:61|Removing wire RID_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3428:30:3428:38|Removing wire RDATA_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3429:30:3429:38|Removing wire RRESP_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3430:30:3430:38|Removing wire RLAST_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3431:30:3431:39|Removing wire RVALID_SI4, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3433:55:3433:61|Removing wire BID_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3434:30:3434:38|Removing wire BRESP_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3435:30:3435:39|Removing wire BVALID_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3436:55:3436:61|Removing wire RID_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3437:30:3437:38|Removing wire RDATA_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3438:30:3438:38|Removing wire RRESP_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3439:30:3439:38|Removing wire RLAST_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3440:30:3440:39|Removing wire RVALID_SI5, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3442:55:3442:61|Removing wire BID_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3443:30:3443:38|Removing wire BRESP_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3444:30:3444:39|Removing wire BVALID_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3445:55:3445:61|Removing wire RID_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3446:30:3446:38|Removing wire RDATA_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3447:30:3447:38|Removing wire RRESP_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3448:30:3448:38|Removing wire RLAST_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3449:30:3449:39|Removing wire RVALID_SI6, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3451:55:3451:61|Removing wire BID_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3452:30:3452:38|Removing wire BRESP_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3453:30:3453:39|Removing wire BVALID_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3454:55:3454:61|Removing wire RID_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3455:30:3455:38|Removing wire RDATA_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3456:30:3456:38|Removing wire RRESP_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3457:30:3457:38|Removing wire RLAST_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3458:30:3458:39|Removing wire RVALID_SI7, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3460:55:3460:61|Removing wire BID_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3461:30:3461:38|Removing wire BRESP_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3462:30:3462:39|Removing wire BVALID_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3463:55:3463:61|Removing wire RID_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3464:30:3464:38|Removing wire RDATA_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3465:30:3465:38|Removing wire RRESP_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3466:30:3466:38|Removing wire RLAST_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3467:30:3467:39|Removing wire RVALID_SI8, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3469:55:3469:61|Removing wire BID_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3470:30:3470:38|Removing wire BRESP_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3471:30:3471:39|Removing wire BVALID_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3472:55:3472:61|Removing wire RID_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3473:30:3473:38|Removing wire RDATA_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3474:30:3474:38|Removing wire RRESP_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3475:30:3475:38|Removing wire RLAST_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3476:30:3476:39|Removing wire RVALID_SI9, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3478:55:3478:62|Removing wire BID_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3479:30:3479:39|Removing wire BRESP_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3480:30:3480:40|Removing wire BVALID_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3481:55:3481:62|Removing wire RID_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3482:30:3482:39|Removing wire RDATA_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3483:30:3483:39|Removing wire RRESP_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3484:30:3484:39|Removing wire RLAST_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3485:30:3485:40|Removing wire RVALID_SI10, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3487:55:3487:62|Removing wire BID_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3488:30:3488:39|Removing wire BRESP_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3489:30:3489:40|Removing wire BVALID_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3490:55:3490:62|Removing wire RID_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3491:30:3491:39|Removing wire RDATA_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3492:30:3492:39|Removing wire RRESP_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3493:30:3493:39|Removing wire RLAST_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3494:30:3494:40|Removing wire RVALID_SI11, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3496:55:3496:62|Removing wire BID_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3497:30:3497:39|Removing wire BRESP_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3498:30:3498:40|Removing wire BVALID_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3499:55:3499:62|Removing wire RID_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3500:30:3500:39|Removing wire RDATA_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3501:30:3501:39|Removing wire RRESP_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3502:30:3502:39|Removing wire RLAST_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3503:30:3503:40|Removing wire RVALID_SI12, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3505:55:3505:62|Removing wire BID_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3506:30:3506:39|Removing wire BRESP_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3507:30:3507:40|Removing wire BVALID_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3508:55:3508:62|Removing wire RID_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3509:30:3509:39|Removing wire RDATA_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3510:30:3510:39|Removing wire RRESP_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3511:30:3511:39|Removing wire RLAST_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3512:30:3512:40|Removing wire RVALID_SI13, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3514:55:3514:62|Removing wire BID_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3515:30:3515:39|Removing wire BRESP_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3516:30:3516:40|Removing wire BVALID_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3517:55:3517:62|Removing wire RID_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3518:30:3518:39|Removing wire RDATA_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3519:30:3519:39|Removing wire RRESP_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3520:30:3520:39|Removing wire RLAST_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3521:30:3521:40|Removing wire RVALID_SI14, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3523:55:3523:62|Removing wire BID_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3524:30:3524:39|Removing wire BRESP_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3525:30:3525:40|Removing wire BVALID_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3526:55:3526:62|Removing wire RID_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3527:30:3527:39|Removing wire RDATA_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3528:30:3528:39|Removing wire RRESP_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3529:30:3529:39|Removing wire RLAST_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3530:30:3530:40|Removing wire RVALID_SI15, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3532:55:3532:62|Removing wire BID_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3533:30:3533:39|Removing wire BRESP_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3534:30:3534:40|Removing wire BVALID_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3535:55:3535:62|Removing wire RID_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3536:30:3536:39|Removing wire RDATA_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3537:30:3537:39|Removing wire RRESP_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3538:30:3538:39|Removing wire RLAST_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3539:30:3539:40|Removing wire RVALID_SI16, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3542:55:3542:60|Removing wire BID_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3543:30:3543:37|Removing wire BRESP_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3544:30:3544:38|Removing wire BVALID_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3545:55:3545:60|Removing wire RID_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3546:30:3546:37|Removing wire RDATA_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3547:30:3547:37|Removing wire RRESP_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3548:30:3548:37|Removing wire RLAST_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3549:30:3549:38|Removing wire RVALID_IM, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3551:30:3551:38|Removing wire m0_rd_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3552:30:3552:38|Removing wire m1_rd_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3553:30:3553:38|Removing wire m2_rd_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3554:30:3554:38|Removing wire m3_rd_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3555:30:3555:38|Removing wire m0_wr_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3556:30:3556:38|Removing wire m1_wr_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3557:30:3557:38|Removing wire m2_wr_end, as there is no assignment to it.
@W: CG360 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":3558:30:3558:38|Removing wire m3_wr_end, as there is no assignment to it.
@W: CL207 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CG296 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":74:8:74:12|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":78:50:78:60|Referenced variable user_option is not in sensitivity list.
@W: CG290 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":84:50:84:61|Referenced variable user_address is not in sensitivity list.
@W: CG290 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":90:50:90:59|Referenced variable user_data1 is not in sensitivity list.
@W: CG290 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":96:50:96:59|Referenced variable user_data2 is not in sensitivity list.
@W: CG290 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":104:50:104:58|Referenced variable ram_rdata is not in sensitivity list.
@W: CG133 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":63:4:63:6|Object SEL is declared but not assigned. Either assign a value or remove the declaration.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v":102:0:102:5|Pruning register bits 3 to 1 of RLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v":102:0:102:5|Pruning register bits 3 to 1 of WLEN[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":49:24:49:28|Input port bits 31 to 13 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":49:24:49:28|Input port bits 1 to 0 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":310:57:310:62|Input port bits 5 to 4 of BID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":326:57:326:62|Input port bits 5 to 4 of RID_S0[5:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1144:33:1144:42|*Output AWREADY_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1151:33:1151:41|*Output WREADY_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1153:33:1153:38|*Output BID_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1154:33:1154:40|*Output BRESP_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1155:33:1155:41|*Output BVALID_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1167:33:1167:42|*Output ARREADY_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1169:33:1169:38|*Output RID_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1170:33:1170:40|*Output RDATA_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1171:33:1171:40|*Output RRESP_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1172:33:1172:40|*Output RLAST_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1173:33:1173:41|*Output RVALID_M1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1187:33:1187:42|*Output AWREADY_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1194:33:1194:41|*Output WREADY_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1196:33:1196:38|*Output BID_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1197:33:1197:40|*Output BRESP_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1198:33:1198:41|*Output BVALID_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1210:33:1210:42|*Output ARREADY_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1212:33:1212:38|*Output RID_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1213:33:1213:40|*Output RDATA_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1214:33:1214:40|*Output RRESP_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1215:33:1215:40|*Output RLAST_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1216:33:1216:41|*Output RVALID_M2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1230:33:1230:42|*Output AWREADY_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1237:33:1237:41|*Output WREADY_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1239:33:1239:38|*Output BID_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1240:33:1240:40|*Output BRESP_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1241:33:1241:41|*Output BVALID_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1253:33:1253:42|*Output ARREADY_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1255:33:1255:38|*Output RID_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1256:33:1256:40|*Output RDATA_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1257:33:1257:40|*Output RRESP_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1258:33:1258:40|*Output RLAST_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1259:33:1259:41|*Output RVALID_M3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1307:58:1307:64|*Output AWID_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1308:23:1308:31|*Output AWADDR_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1309:33:1309:40|*Output AWLEN_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1310:33:1310:41|*Output AWSIZE_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1311:33:1311:42|*Output AWBURST_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1312:33:1312:41|*Output AWLOCK_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1313:33:1313:42|*Output AWCACHE_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1314:33:1314:41|*Output AWPROT_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1315:33:1315:42|*Output AWVALID_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1318:58:1318:63|*Output WID_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1319:33:1319:40|*Output WDATA_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1320:33:1320:40|*Output WSTRB_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1321:33:1321:40|*Output WLAST_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1322:33:1322:41|*Output WVALID_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1328:33:1328:41|*Output BREADY_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1330:58:1330:64|*Output ARID_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1331:23:1331:31|*Output ARADDR_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1332:33:1332:40|*Output ARLEN_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1333:33:1333:41|*Output ARSIZE_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1334:33:1334:42|*Output ARBURST_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1335:33:1335:41|*Output ARLOCK_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1336:33:1336:42|*Output ARCACHE_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1337:33:1337:41|*Output ARPROT_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1338:33:1338:42|*Output ARVALID_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1346:33:1346:41|*Output RREADY_S1 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1350:58:1350:64|*Output AWID_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1351:23:1351:31|*Output AWADDR_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1352:33:1352:40|*Output AWLEN_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1353:33:1353:41|*Output AWSIZE_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1354:33:1354:42|*Output AWBURST_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1355:33:1355:41|*Output AWLOCK_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1356:33:1356:42|*Output AWCACHE_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1357:33:1357:41|*Output AWPROT_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1358:33:1358:42|*Output AWVALID_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1361:58:1361:63|*Output WID_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1362:33:1362:40|*Output WDATA_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1363:33:1363:40|*Output WSTRB_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1364:33:1364:40|*Output WLAST_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1365:33:1365:41|*Output WVALID_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1371:33:1371:41|*Output BREADY_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1373:58:1373:64|*Output ARID_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1374:23:1374:31|*Output ARADDR_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1375:33:1375:40|*Output ARLEN_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1376:33:1376:41|*Output ARSIZE_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1377:33:1377:42|*Output ARBURST_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1378:33:1378:41|*Output ARLOCK_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1379:33:1379:42|*Output ARCACHE_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1380:33:1380:41|*Output ARPROT_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1381:33:1381:42|*Output ARVALID_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1389:33:1389:41|*Output RREADY_S2 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1393:58:1393:64|*Output AWID_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1394:23:1394:31|*Output AWADDR_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1395:33:1395:40|*Output AWLEN_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1396:33:1396:41|*Output AWSIZE_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1397:33:1397:42|*Output AWBURST_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1398:33:1398:41|*Output AWLOCK_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1399:33:1399:42|*Output AWCACHE_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1400:33:1400:41|*Output AWPROT_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1401:33:1401:42|*Output AWVALID_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1404:58:1404:63|*Output WID_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1405:33:1405:40|*Output WDATA_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1406:33:1406:40|*Output WSTRB_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1407:33:1407:40|*Output WLAST_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1408:33:1408:41|*Output WVALID_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1414:33:1414:41|*Output BREADY_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1416:58:1416:64|*Output ARID_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1417:23:1417:31|*Output ARADDR_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1418:33:1418:40|*Output ARLEN_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1419:33:1419:41|*Output ARSIZE_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1420:33:1420:42|*Output ARBURST_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1421:33:1421:41|*Output ARLOCK_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1422:33:1422:42|*Output ARCACHE_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1423:33:1423:41|*Output ARPROT_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1424:33:1424:42|*Output ARVALID_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1432:33:1432:41|*Output RREADY_S3 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1436:58:1436:64|*Output AWID_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1437:23:1437:31|*Output AWADDR_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1438:33:1438:40|*Output AWLEN_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1439:33:1439:41|*Output AWSIZE_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1440:33:1440:42|*Output AWBURST_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1441:33:1441:41|*Output AWLOCK_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1442:33:1442:42|*Output AWCACHE_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1443:33:1443:41|*Output AWPROT_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1444:33:1444:42|*Output AWVALID_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1447:58:1447:63|*Output WID_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1448:33:1448:40|*Output WDATA_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1449:33:1449:40|*Output WSTRB_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1450:33:1450:40|*Output WLAST_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1451:33:1451:41|*Output WVALID_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1457:33:1457:41|*Output BREADY_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1459:58:1459:64|*Output ARID_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1460:23:1460:31|*Output ARADDR_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1461:33:1461:40|*Output ARLEN_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1462:33:1462:41|*Output ARSIZE_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1463:33:1463:42|*Output ARBURST_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1464:33:1464:41|*Output ARLOCK_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1465:33:1465:42|*Output ARCACHE_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1466:33:1466:41|*Output ARPROT_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1467:33:1467:42|*Output ARVALID_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1475:33:1475:41|*Output RREADY_S4 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1479:58:1479:64|*Output AWID_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1480:23:1480:31|*Output AWADDR_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1481:33:1481:40|*Output AWLEN_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1482:33:1482:41|*Output AWSIZE_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1483:33:1483:42|*Output AWBURST_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1484:33:1484:41|*Output AWLOCK_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1485:33:1485:42|*Output AWCACHE_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1486:33:1486:41|*Output AWPROT_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1487:33:1487:42|*Output AWVALID_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1490:58:1490:63|*Output WID_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1491:33:1491:40|*Output WDATA_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1492:33:1492:40|*Output WSTRB_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1493:33:1493:40|*Output WLAST_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1494:33:1494:41|*Output WVALID_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1500:33:1500:41|*Output BREADY_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1502:58:1502:64|*Output ARID_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1503:23:1503:31|*Output ARADDR_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1504:33:1504:40|*Output ARLEN_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1505:33:1505:41|*Output ARSIZE_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1506:33:1506:42|*Output ARBURST_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1507:33:1507:41|*Output ARLOCK_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1508:33:1508:42|*Output ARCACHE_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1509:33:1509:41|*Output ARPROT_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1510:33:1510:42|*Output ARVALID_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1518:33:1518:41|*Output RREADY_S5 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1522:58:1522:64|*Output AWID_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1523:23:1523:31|*Output AWADDR_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1524:33:1524:40|*Output AWLEN_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1525:33:1525:41|*Output AWSIZE_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1526:33:1526:42|*Output AWBURST_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1527:33:1527:41|*Output AWLOCK_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1528:33:1528:42|*Output AWCACHE_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1529:33:1529:41|*Output AWPROT_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1530:33:1530:42|*Output AWVALID_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1533:58:1533:63|*Output WID_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1534:33:1534:40|*Output WDATA_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1535:33:1535:40|*Output WSTRB_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1536:33:1536:40|*Output WLAST_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1537:33:1537:41|*Output WVALID_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1543:33:1543:41|*Output BREADY_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1545:58:1545:64|*Output ARID_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1546:23:1546:31|*Output ARADDR_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1547:33:1547:40|*Output ARLEN_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1548:33:1548:41|*Output ARSIZE_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1549:33:1549:42|*Output ARBURST_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1550:33:1550:41|*Output ARLOCK_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1551:33:1551:42|*Output ARCACHE_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1552:33:1552:41|*Output ARPROT_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1553:33:1553:42|*Output ARVALID_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1561:33:1561:41|*Output RREADY_S6 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1565:58:1565:64|*Output AWID_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1566:23:1566:31|*Output AWADDR_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1567:33:1567:40|*Output AWLEN_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1568:33:1568:41|*Output AWSIZE_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1569:33:1569:42|*Output AWBURST_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1570:33:1570:41|*Output AWLOCK_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1571:33:1571:42|*Output AWCACHE_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1572:33:1572:41|*Output AWPROT_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1573:33:1573:42|*Output AWVALID_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1576:58:1576:63|*Output WID_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1577:33:1577:40|*Output WDATA_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1578:33:1578:40|*Output WSTRB_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1579:33:1579:40|*Output WLAST_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1580:33:1580:41|*Output WVALID_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1586:33:1586:41|*Output BREADY_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1588:58:1588:64|*Output ARID_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1589:23:1589:31|*Output ARADDR_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1590:33:1590:40|*Output ARLEN_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1591:33:1591:41|*Output ARSIZE_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1592:33:1592:42|*Output ARBURST_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1593:33:1593:41|*Output ARLOCK_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1594:33:1594:42|*Output ARCACHE_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1595:33:1595:41|*Output ARPROT_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1596:33:1596:42|*Output ARVALID_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1604:33:1604:41|*Output RREADY_S7 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1608:58:1608:64|*Output AWID_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1609:23:1609:31|*Output AWADDR_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1610:33:1610:40|*Output AWLEN_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1611:33:1611:41|*Output AWSIZE_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1612:33:1612:42|*Output AWBURST_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1613:33:1613:41|*Output AWLOCK_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1614:33:1614:42|*Output AWCACHE_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1615:33:1615:41|*Output AWPROT_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1616:33:1616:42|*Output AWVALID_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1619:58:1619:63|*Output WID_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1620:33:1620:40|*Output WDATA_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1621:33:1621:40|*Output WSTRB_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1622:33:1622:40|*Output WLAST_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1623:33:1623:41|*Output WVALID_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1629:33:1629:41|*Output BREADY_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1631:58:1631:64|*Output ARID_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1632:23:1632:31|*Output ARADDR_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1633:33:1633:40|*Output ARLEN_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1634:33:1634:41|*Output ARSIZE_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1635:33:1635:42|*Output ARBURST_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1636:33:1636:41|*Output ARLOCK_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1637:33:1637:42|*Output ARCACHE_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1638:33:1638:41|*Output ARPROT_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1639:33:1639:42|*Output ARVALID_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1647:33:1647:41|*Output RREADY_S8 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1651:58:1651:64|*Output AWID_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1652:23:1652:31|*Output AWADDR_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1653:33:1653:40|*Output AWLEN_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1654:33:1654:41|*Output AWSIZE_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1655:33:1655:42|*Output AWBURST_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1656:33:1656:41|*Output AWLOCK_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1657:33:1657:42|*Output AWCACHE_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1658:33:1658:41|*Output AWPROT_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1659:33:1659:42|*Output AWVALID_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1662:58:1662:63|*Output WID_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1663:33:1663:40|*Output WDATA_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1664:33:1664:40|*Output WSTRB_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1665:33:1665:40|*Output WLAST_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1666:33:1666:41|*Output WVALID_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1672:33:1672:41|*Output BREADY_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1674:58:1674:64|*Output ARID_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1675:23:1675:31|*Output ARADDR_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1676:33:1676:40|*Output ARLEN_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1677:33:1677:41|*Output ARSIZE_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1678:33:1678:42|*Output ARBURST_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1679:33:1679:41|*Output ARLOCK_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1680:33:1680:42|*Output ARCACHE_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1681:33:1681:41|*Output ARPROT_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1682:33:1682:42|*Output ARVALID_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1690:33:1690:41|*Output RREADY_S9 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1694:58:1694:65|*Output AWID_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1695:23:1695:32|*Output AWADDR_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1696:33:1696:41|*Output AWLEN_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1697:33:1697:42|*Output AWSIZE_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1698:33:1698:43|*Output AWBURST_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1699:33:1699:42|*Output AWLOCK_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1700:33:1700:43|*Output AWCACHE_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1701:33:1701:42|*Output AWPROT_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1702:33:1702:43|*Output AWVALID_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1705:58:1705:64|*Output WID_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1706:33:1706:41|*Output WDATA_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1707:33:1707:41|*Output WSTRB_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1708:33:1708:41|*Output WLAST_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1709:33:1709:42|*Output WVALID_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1715:33:1715:42|*Output BREADY_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1717:58:1717:65|*Output ARID_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1718:23:1718:32|*Output ARADDR_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1719:33:1719:41|*Output ARLEN_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1720:33:1720:42|*Output ARSIZE_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1721:33:1721:43|*Output ARBURST_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1722:33:1722:42|*Output ARLOCK_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1723:33:1723:43|*Output ARCACHE_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1724:33:1724:42|*Output ARPROT_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1725:33:1725:43|*Output ARVALID_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1733:33:1733:42|*Output RREADY_S10 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1737:58:1737:65|*Output AWID_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1738:23:1738:32|*Output AWADDR_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1739:33:1739:41|*Output AWLEN_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1740:33:1740:42|*Output AWSIZE_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1741:33:1741:43|*Output AWBURST_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1742:33:1742:42|*Output AWLOCK_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1743:33:1743:43|*Output AWCACHE_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1744:33:1744:42|*Output AWPROT_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1745:33:1745:43|*Output AWVALID_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1748:58:1748:64|*Output WID_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1749:33:1749:41|*Output WDATA_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1750:33:1750:41|*Output WSTRB_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1751:33:1751:41|*Output WLAST_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1752:33:1752:42|*Output WVALID_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1758:33:1758:42|*Output BREADY_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1760:58:1760:65|*Output ARID_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1761:23:1761:32|*Output ARADDR_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1762:33:1762:41|*Output ARLEN_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1763:33:1763:42|*Output ARSIZE_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1764:33:1764:43|*Output ARBURST_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1765:33:1765:42|*Output ARLOCK_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1766:33:1766:43|*Output ARCACHE_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1767:33:1767:42|*Output ARPROT_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1768:33:1768:43|*Output ARVALID_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1776:33:1776:42|*Output RREADY_S11 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1780:58:1780:65|*Output AWID_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1781:23:1781:32|*Output AWADDR_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1782:33:1782:41|*Output AWLEN_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1783:33:1783:42|*Output AWSIZE_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1784:33:1784:43|*Output AWBURST_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1785:33:1785:42|*Output AWLOCK_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1786:33:1786:43|*Output AWCACHE_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1787:33:1787:42|*Output AWPROT_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1788:33:1788:43|*Output AWVALID_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1791:58:1791:64|*Output WID_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1792:33:1792:41|*Output WDATA_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1793:33:1793:41|*Output WSTRB_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1794:33:1794:41|*Output WLAST_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1795:33:1795:42|*Output WVALID_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1801:33:1801:42|*Output BREADY_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1803:58:1803:65|*Output ARID_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1804:23:1804:32|*Output ARADDR_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1805:33:1805:41|*Output ARLEN_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1806:33:1806:42|*Output ARSIZE_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1807:33:1807:43|*Output ARBURST_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1808:33:1808:42|*Output ARLOCK_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1809:33:1809:43|*Output ARCACHE_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1810:33:1810:42|*Output ARPROT_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1811:33:1811:43|*Output ARVALID_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1819:33:1819:42|*Output RREADY_S12 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1823:58:1823:65|*Output AWID_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1824:23:1824:32|*Output AWADDR_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1825:33:1825:41|*Output AWLEN_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1826:33:1826:42|*Output AWSIZE_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1827:33:1827:43|*Output AWBURST_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1828:33:1828:42|*Output AWLOCK_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1829:33:1829:43|*Output AWCACHE_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1830:33:1830:42|*Output AWPROT_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1831:33:1831:43|*Output AWVALID_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1834:58:1834:64|*Output WID_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1835:33:1835:41|*Output WDATA_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1836:33:1836:41|*Output WSTRB_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1837:33:1837:41|*Output WLAST_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1838:33:1838:42|*Output WVALID_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1844:33:1844:42|*Output BREADY_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1846:58:1846:65|*Output ARID_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1847:23:1847:32|*Output ARADDR_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1848:33:1848:41|*Output ARLEN_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1849:33:1849:42|*Output ARSIZE_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1850:33:1850:43|*Output ARBURST_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1851:33:1851:42|*Output ARLOCK_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1852:33:1852:43|*Output ARCACHE_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1853:33:1853:42|*Output ARPROT_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1854:33:1854:43|*Output ARVALID_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1862:33:1862:42|*Output RREADY_S13 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1866:58:1866:65|*Output AWID_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1867:23:1867:32|*Output AWADDR_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1868:33:1868:41|*Output AWLEN_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1869:33:1869:42|*Output AWSIZE_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1870:33:1870:43|*Output AWBURST_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1871:33:1871:42|*Output AWLOCK_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1872:33:1872:43|*Output AWCACHE_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1873:33:1873:42|*Output AWPROT_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1874:33:1874:43|*Output AWVALID_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1877:58:1877:64|*Output WID_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1878:33:1878:41|*Output WDATA_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1879:33:1879:41|*Output WSTRB_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1880:33:1880:41|*Output WLAST_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1881:33:1881:42|*Output WVALID_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1887:33:1887:42|*Output BREADY_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1889:58:1889:65|*Output ARID_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1890:23:1890:32|*Output ARADDR_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1891:33:1891:41|*Output ARLEN_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1892:33:1892:42|*Output ARSIZE_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1893:33:1893:43|*Output ARBURST_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1894:33:1894:42|*Output ARLOCK_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1895:33:1895:43|*Output ARCACHE_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1896:33:1896:42|*Output ARPROT_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1897:33:1897:43|*Output ARVALID_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1905:33:1905:42|*Output RREADY_S14 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1909:58:1909:65|*Output AWID_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1910:23:1910:32|*Output AWADDR_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1911:33:1911:41|*Output AWLEN_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1912:33:1912:42|*Output AWSIZE_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1913:33:1913:43|*Output AWBURST_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1914:33:1914:42|*Output AWLOCK_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1915:33:1915:43|*Output AWCACHE_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1916:33:1916:42|*Output AWPROT_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1917:33:1917:43|*Output AWVALID_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1920:58:1920:64|*Output WID_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1921:33:1921:41|*Output WDATA_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1922:33:1922:41|*Output WSTRB_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1923:33:1923:41|*Output WLAST_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1924:33:1924:42|*Output WVALID_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1930:33:1930:42|*Output BREADY_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1932:58:1932:65|*Output ARID_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1933:23:1933:32|*Output ARADDR_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1934:33:1934:41|*Output ARLEN_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1935:33:1935:42|*Output ARSIZE_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1936:33:1936:43|*Output ARBURST_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1937:33:1937:42|*Output ARLOCK_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1938:33:1938:43|*Output ARCACHE_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1939:33:1939:42|*Output ARPROT_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1940:33:1940:43|*Output ARVALID_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1948:33:1948:42|*Output RREADY_S15 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1952:58:1952:65|*Output AWID_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1953:23:1953:32|*Output AWADDR_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1954:33:1954:41|*Output AWLEN_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1955:33:1955:42|*Output AWSIZE_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1956:33:1956:43|*Output AWBURST_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1957:33:1957:42|*Output AWLOCK_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1958:33:1958:43|*Output AWCACHE_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1959:33:1959:42|*Output AWPROT_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1960:33:1960:43|*Output AWVALID_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1963:58:1963:64|*Output WID_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1964:33:1964:41|*Output WDATA_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1965:33:1965:41|*Output WSTRB_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1966:33:1966:41|*Output WLAST_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1967:33:1967:42|*Output WVALID_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1973:33:1973:42|*Output BREADY_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1975:58:1975:65|*Output ARID_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1976:23:1976:32|*Output ARADDR_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1977:33:1977:41|*Output ARLEN_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1978:33:1978:42|*Output ARSIZE_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1979:33:1979:43|*Output ARBURST_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1980:33:1980:42|*Output ARLOCK_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1981:33:1981:43|*Output ARCACHE_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1982:33:1982:42|*Output ARPROT_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1983:33:1983:43|*Output ARVALID_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1991:33:1991:42|*Output RREADY_S16 has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":222:0:222:5|Pruning register bit 1 of ARSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Pruning register bits 7 to 1 of WSTRB[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Pruning register bit 1 of AWSIZE[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.

