@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":21:7:21:12|Synthesizing module AXI_IF in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":727:7:727:9|Synthesizing module CCC in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\CCC_0\MDDR_Demo_sb_CCC_0_FCCC.v":5:7:5:29|Synthesizing module MDDR_Demo_sb_CCC_0_FCCC in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3 in library COREAPB3_LIB.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":29:7:29:36|Synthesizing module MDDR_Demo_sb_COREAXI_0_COREAXI in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":30:7:30:21|Synthesizing module axi_feedthrough in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v":5:7:5:31|Synthesizing module MDDR_Demo_sb_FABOSC_0_OSC in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":274:7:274:12|Synthesizing module OUTBUF in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS_syn.v":5:7:5:13|Synthesizing module MSS_075 in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS.v":9:7:9:22|Synthesizing module MDDR_Demo_sb_MSS in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":718:7:718:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\MDDR_Demo_sb.v":9:7:9:18|Synthesizing module MDDR_Demo_sb in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo\MDDR_Demo.v":9:7:9:15|Synthesizing module MDDR_Demo in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_top\MDDR_Demo_top.v":9:7:9:19|Synthesizing module MDDR_Demo_top in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":22:7:22:20|Synthesizing module DATAHANDLE_FSM in library work.
@N: CG364 :"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v":382:7:382:13|Synthesizing module RAM1K18 in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\UART_IF\TPSRAM_0\UART_IF_TPSRAM_0_TPSRAM.v":5:7:5:29|Synthesizing module UART_IF_TPSRAM_0_TPSRAM in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v":20:7:20:17|Synthesizing module UART_IF_FSM in library work.
@N: CG179 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v":237:35:237:45|Removing redundant assignment.
@N: CG179 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v":244:15:244:20|Removing redundant assignment.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\UART_IF\UART_IF.v":9:7:9:13|Synthesizing module UART_IF in library work.
@N: CG364 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\SF2_MDDR_Demo\SF2_MDDR_Demo.v":9:7:9:19|Synthesizing module SF2_MDDR_Demo in library work.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\UART_IF_FSM.v":102:0:102:5|Trying to extract state machine for register fsm.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":110:0:110:5|Trying to extract state machine for register fsm.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\DATA_HANDLE_FSM.v":48:12:48:18|Input PENABLE is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":71:24:71:35|Input SDIF1_PREADY is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":72:24:72:36|Input SDIF1_PSLVERR is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":243:32:243:35|Input ACLK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v":244:32:244:38|Input ARESETN is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1135:33:1135:39|Input AWID_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1136:23:1136:31|Input AWADDR_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1137:33:1137:40|Input AWLEN_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1138:33:1138:41|Input AWSIZE_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1139:33:1139:42|Input AWBURST_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1140:33:1140:41|Input AWLOCK_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1141:33:1141:42|Input AWCACHE_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1142:33:1142:41|Input AWPROT_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1143:33:1143:42|Input AWVALID_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1146:33:1146:38|Input WID_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1147:33:1147:40|Input WDATA_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1148:33:1148:40|Input WSTRB_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1149:33:1149:40|Input WLAST_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1150:33:1150:41|Input WVALID_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1156:33:1156:41|Input BREADY_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1158:33:1158:39|Input ARID_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1159:23:1159:31|Input ARADDR_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1160:33:1160:40|Input ARLEN_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1161:33:1161:41|Input ARSIZE_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1162:33:1162:42|Input ARBURST_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1163:33:1163:41|Input ARLOCK_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1164:33:1164:42|Input ARCACHE_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1165:33:1165:41|Input ARPROT_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1166:33:1166:42|Input ARVALID_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1174:33:1174:41|Input RREADY_M1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1178:33:1178:39|Input AWID_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1179:23:1179:31|Input AWADDR_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1180:33:1180:40|Input AWLEN_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1181:33:1181:41|Input AWSIZE_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1182:33:1182:42|Input AWBURST_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1183:33:1183:41|Input AWLOCK_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1184:33:1184:42|Input AWCACHE_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1185:33:1185:41|Input AWPROT_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1186:33:1186:42|Input AWVALID_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1189:33:1189:38|Input WID_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1190:33:1190:40|Input WDATA_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1191:33:1191:40|Input WSTRB_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1192:33:1192:40|Input WLAST_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1193:33:1193:41|Input WVALID_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1199:33:1199:41|Input BREADY_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1201:33:1201:39|Input ARID_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1202:23:1202:31|Input ARADDR_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1203:33:1203:40|Input ARLEN_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1204:33:1204:41|Input ARSIZE_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1205:33:1205:42|Input ARBURST_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1206:33:1206:41|Input ARLOCK_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1207:33:1207:42|Input ARCACHE_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1208:33:1208:41|Input ARPROT_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1209:33:1209:42|Input ARVALID_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1217:33:1217:41|Input RREADY_M2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1221:33:1221:39|Input AWID_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1222:23:1222:31|Input AWADDR_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1223:33:1223:40|Input AWLEN_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1224:33:1224:41|Input AWSIZE_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1225:33:1225:42|Input AWBURST_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1226:33:1226:41|Input AWLOCK_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1227:33:1227:42|Input AWCACHE_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1228:33:1228:41|Input AWPROT_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1229:33:1229:42|Input AWVALID_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1232:33:1232:38|Input WID_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1233:33:1233:40|Input WDATA_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1234:33:1234:40|Input WSTRB_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1235:33:1235:40|Input WLAST_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1236:33:1236:41|Input WVALID_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1242:33:1242:41|Input BREADY_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1244:33:1244:39|Input ARID_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1245:23:1245:31|Input ARADDR_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1246:33:1246:40|Input ARLEN_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1247:33:1247:41|Input ARSIZE_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1248:33:1248:42|Input ARBURST_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1249:33:1249:41|Input ARLOCK_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1250:33:1250:42|Input ARCACHE_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1251:33:1251:41|Input ARPROT_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1252:33:1252:42|Input ARVALID_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1260:33:1260:41|Input RREADY_M3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1316:33:1316:42|Input AWREADY_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1323:33:1323:41|Input WREADY_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1325:58:1325:63|Input BID_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1326:33:1326:40|Input BRESP_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1327:33:1327:41|Input BVALID_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1339:33:1339:42|Input ARREADY_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1341:58:1341:63|Input RID_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1342:33:1342:40|Input RDATA_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1343:33:1343:40|Input RRESP_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1344:33:1344:40|Input RLAST_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1345:33:1345:41|Input RVALID_S1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1359:33:1359:42|Input AWREADY_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1366:33:1366:41|Input WREADY_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1368:58:1368:63|Input BID_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1369:33:1369:40|Input BRESP_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1370:33:1370:41|Input BVALID_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1382:33:1382:42|Input ARREADY_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1384:58:1384:63|Input RID_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1385:33:1385:40|Input RDATA_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1386:33:1386:40|Input RRESP_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1387:33:1387:40|Input RLAST_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1388:33:1388:41|Input RVALID_S2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1402:33:1402:42|Input AWREADY_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1409:33:1409:41|Input WREADY_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1411:58:1411:63|Input BID_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1412:33:1412:40|Input BRESP_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1413:33:1413:41|Input BVALID_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1425:33:1425:42|Input ARREADY_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1427:58:1427:63|Input RID_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1428:33:1428:40|Input RDATA_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1429:33:1429:40|Input RRESP_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1430:33:1430:40|Input RLAST_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1431:33:1431:41|Input RVALID_S3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1445:33:1445:42|Input AWREADY_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1452:33:1452:41|Input WREADY_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1454:58:1454:63|Input BID_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1455:33:1455:40|Input BRESP_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1456:33:1456:41|Input BVALID_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1468:33:1468:42|Input ARREADY_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1470:58:1470:63|Input RID_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1471:33:1471:40|Input RDATA_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1472:33:1472:40|Input RRESP_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1473:33:1473:40|Input RLAST_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1474:33:1474:41|Input RVALID_S4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1488:33:1488:42|Input AWREADY_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1495:33:1495:41|Input WREADY_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1497:58:1497:63|Input BID_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1498:33:1498:40|Input BRESP_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1499:33:1499:41|Input BVALID_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1511:33:1511:42|Input ARREADY_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1513:58:1513:63|Input RID_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1514:33:1514:40|Input RDATA_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1515:33:1515:40|Input RRESP_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1516:33:1516:40|Input RLAST_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1517:33:1517:41|Input RVALID_S5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1531:33:1531:42|Input AWREADY_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1538:33:1538:41|Input WREADY_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1540:58:1540:63|Input BID_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1541:33:1541:40|Input BRESP_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1542:33:1542:41|Input BVALID_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1554:33:1554:42|Input ARREADY_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1556:58:1556:63|Input RID_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1557:33:1557:40|Input RDATA_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1558:33:1558:40|Input RRESP_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1559:33:1559:40|Input RLAST_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1560:33:1560:41|Input RVALID_S6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1574:33:1574:42|Input AWREADY_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1581:33:1581:41|Input WREADY_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1583:58:1583:63|Input BID_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1584:33:1584:40|Input BRESP_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1585:33:1585:41|Input BVALID_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1597:33:1597:42|Input ARREADY_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1599:58:1599:63|Input RID_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1600:33:1600:40|Input RDATA_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1601:33:1601:40|Input RRESP_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1602:33:1602:40|Input RLAST_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1603:33:1603:41|Input RVALID_S7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1617:33:1617:42|Input AWREADY_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1624:33:1624:41|Input WREADY_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1626:58:1626:63|Input BID_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1627:33:1627:40|Input BRESP_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1628:33:1628:41|Input BVALID_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1640:33:1640:42|Input ARREADY_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1642:58:1642:63|Input RID_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1643:33:1643:40|Input RDATA_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1644:33:1644:40|Input RRESP_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1645:33:1645:40|Input RLAST_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1646:33:1646:41|Input RVALID_S8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1660:33:1660:42|Input AWREADY_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1667:33:1667:41|Input WREADY_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1669:58:1669:63|Input BID_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1670:33:1670:40|Input BRESP_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1671:33:1671:41|Input BVALID_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1683:33:1683:42|Input ARREADY_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1685:58:1685:63|Input RID_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1686:33:1686:40|Input RDATA_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1687:33:1687:40|Input RRESP_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1688:33:1688:40|Input RLAST_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1689:33:1689:41|Input RVALID_S9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1703:33:1703:43|Input AWREADY_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1710:33:1710:42|Input WREADY_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1712:58:1712:64|Input BID_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1713:33:1713:41|Input BRESP_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1714:33:1714:42|Input BVALID_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1726:33:1726:43|Input ARREADY_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1728:58:1728:64|Input RID_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1729:33:1729:41|Input RDATA_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1730:33:1730:41|Input RRESP_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1731:33:1731:41|Input RLAST_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1732:33:1732:42|Input RVALID_S10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1746:33:1746:43|Input AWREADY_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1753:33:1753:42|Input WREADY_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1755:58:1755:64|Input BID_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1756:33:1756:41|Input BRESP_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1757:33:1757:42|Input BVALID_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1769:33:1769:43|Input ARREADY_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1771:58:1771:64|Input RID_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1772:33:1772:41|Input RDATA_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1773:33:1773:41|Input RRESP_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1774:33:1774:41|Input RLAST_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1775:33:1775:42|Input RVALID_S11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1789:33:1789:43|Input AWREADY_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1796:33:1796:42|Input WREADY_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1798:58:1798:64|Input BID_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1799:33:1799:41|Input BRESP_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1800:33:1800:42|Input BVALID_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1812:33:1812:43|Input ARREADY_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1814:58:1814:64|Input RID_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1815:33:1815:41|Input RDATA_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1816:33:1816:41|Input RRESP_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1817:33:1817:41|Input RLAST_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1818:33:1818:42|Input RVALID_S12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1832:33:1832:43|Input AWREADY_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1839:33:1839:42|Input WREADY_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1841:58:1841:64|Input BID_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1842:33:1842:41|Input BRESP_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1843:33:1843:42|Input BVALID_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1855:33:1855:43|Input ARREADY_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1857:58:1857:64|Input RID_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1858:33:1858:41|Input RDATA_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1859:33:1859:41|Input RRESP_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1860:33:1860:41|Input RLAST_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1861:33:1861:42|Input RVALID_S13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1875:33:1875:43|Input AWREADY_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1882:33:1882:42|Input WREADY_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1884:58:1884:64|Input BID_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1885:33:1885:41|Input BRESP_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1886:33:1886:42|Input BVALID_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1898:33:1898:43|Input ARREADY_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1900:58:1900:64|Input RID_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1901:33:1901:41|Input RDATA_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1902:33:1902:41|Input RRESP_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1903:33:1903:41|Input RLAST_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1904:33:1904:42|Input RVALID_S14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1918:33:1918:43|Input AWREADY_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1925:33:1925:42|Input WREADY_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1927:58:1927:64|Input BID_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1928:33:1928:41|Input BRESP_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1929:33:1929:42|Input BVALID_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1941:33:1941:43|Input ARREADY_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1943:58:1943:64|Input RID_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1944:33:1944:41|Input RDATA_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1945:33:1945:41|Input RRESP_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1946:33:1946:41|Input RLAST_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1947:33:1947:42|Input RVALID_S15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1961:33:1961:43|Input AWREADY_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1968:33:1968:42|Input WREADY_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1970:58:1970:64|Input BID_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1971:33:1971:41|Input BRESP_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1972:33:1972:42|Input BVALID_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1984:33:1984:43|Input ARREADY_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1986:58:1986:64|Input RID_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1987:33:1987:41|Input RDATA_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1988:33:1988:41|Input RRESP_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1989:33:1989:41|Input RLAST_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v":1990:33:1990:42|Input RVALID_S16 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":72:36:72:40|Input IADDR is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":73:13:73:19|Input PRESETN is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":74:13:74:16|Input PCLK is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":105:18:105:25|Input PRDATAS1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":106:18:106:25|Input PRDATAS2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":107:18:107:25|Input PRDATAS3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":108:18:108:25|Input PRDATAS4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":109:18:109:25|Input PRDATAS5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":110:18:110:25|Input PRDATAS6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":111:18:111:25|Input PRDATAS7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":112:18:112:25|Input PRDATAS8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":113:18:113:25|Input PRDATAS9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":114:18:114:26|Input PRDATAS10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":115:18:115:26|Input PRDATAS11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":116:18:116:26|Input PRDATAS12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":117:18:117:26|Input PRDATAS13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":118:18:118:26|Input PRDATAS14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":119:18:119:26|Input PRDATAS15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":122:13:122:20|Input PREADYS1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":123:13:123:20|Input PREADYS2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":124:13:124:20|Input PREADYS3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":125:13:125:20|Input PREADYS4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":126:13:126:20|Input PREADYS5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":127:13:127:20|Input PREADYS6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":128:13:128:20|Input PREADYS7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":129:13:129:20|Input PREADYS8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":130:13:130:20|Input PREADYS9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":131:13:131:21|Input PREADYS10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":132:13:132:21|Input PREADYS11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":133:13:133:21|Input PREADYS12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":134:13:134:21|Input PREADYS13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":135:13:135:21|Input PREADYS14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":136:13:136:21|Input PREADYS15 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":139:13:139:21|Input PSLVERRS1 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":140:13:140:21|Input PSLVERRS2 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":141:13:141:21|Input PSLVERRS3 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":142:13:142:21|Input PSLVERRS4 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":143:13:143:21|Input PSLVERRS5 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":144:13:144:21|Input PSLVERRS6 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":145:13:145:21|Input PSLVERRS7 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":146:13:146:21|Input PSLVERRS8 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":147:13:147:21|Input PSLVERRS9 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":148:13:148:22|Input PSLVERRS10 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":149:13:149:22|Input PSLVERRS11 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":150:13:150:22|Input PSLVERRS12 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":151:13:151:22|Input PSLVERRS13 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":152:13:152:22|Input PSLVERRS14 is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":153:13:153:22|Input PSLVERRS15 is unused.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":222:0:222:5|Trying to extract state machine for register axi_fsm_read_state.
@N: CL201 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":95:0:95:5|Trying to extract state machine for register axi_fsm_current_state.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":52:22:52:24|Input BID is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":53:21:53:25|Input BRESP is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":66:26:66:28|Input RID is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":67:26:67:30|Input RDATA is unused.
@N: CL159 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\hdl\AXI_IF.v":68:26:68:30|Input RRESP is unused.
@N|Running in 64-bit mode
@N: NF107 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\SF2_MDDR_Demo\SF2_MDDR_Demo.v":9:7:9:19|Selected library: work cell: SF2_MDDR_Demo view verilog as top level
@N: NF107 :"C:\Users\athuldeep.n\Desktop\URGENT_SAR_FIX\68492_SF2_LPDDR\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Libero_project\SF2_MDDR_Demo\component\work\SF2_MDDR_Demo\SF2_MDDR_Demo.v":9:7:9:19|Selected library: work cell: SF2_MDDR_Demo view verilog as top level

