@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z4(verilog) because there are no references to its outputs 
@N: BN362 :"e:\libero_11p7_capture_tests\new_flow\sf2_mddr_demo\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance MDDR_Demo_sb_0.CORECONFIGP_0.paddr[14] in hierarchy view:work.MDDR_Demo(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net MDDR_Demo_sb_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT  I_36 
@N: FP130 |Promoting Net MDDR_Demo_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_37 
@N: FP130 |Promoting Net MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_38 
@N: FP130 |Promoting Net MDDR_Demo_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_39 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
