Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Tue Apr 6 18:47:32 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S090TS
Package: 484 FBGA
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 132.112 100.0%
Static Power 101.947 77.2%
Dynamic Power 30.165 22.8%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 27.717 1.200 23.097
Rail VDDI 1.8 76.460 1.800 42.478
Rail CCC_NW1_PLL_VDDA 9.000 3.300 2.727
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038
Rail VDDI 2.5 0.611 2.500 0.244

Breakdown by Clock

Power (mW) Percentage
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (clocks) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (register outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (combinational outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (clocks) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (register outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (combinational outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (clocks) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (register outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (combinational outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.000 0.0%
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
Input to Output 0.000 0.0%

Breakdown by Type

Power (mW) Percentage
Type Gate 9.000 6.8%
Type I/O 81.973 62.0%
Type Core Static 18.535 14.0%
Type Banks Static 0.614 0.5%
Type VPP Static 0.825 0.6%
Type Built-in Blocks 21.165 16.0%