//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Sep 12 09:22:27 2017
// Version: v11.8 SP1 11.8.1.12
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// UART_IF
module UART_IF(
    // Inputs
    AXI_RBUSY,
    AXI_WBUSY,
    BREADY,
    CLK,
    PADDR,
    PCLK,
    PENABLE,
    PRESETN,
    PSEL,
    PWDATA,
    PWRITE,
    RESET_N,
    RLAST,
    RREADY,
    RVALID,
    WD,
    WEN,
    // Outputs
    DATA_INPUT,
    PRDATA,
    PREADY,
    PSLVERR,
    READ,
    READ_ADDRESS,
    RLEN,
    WLEN,
    WRITE,
    WRITE_ADDRESS,
    start_read
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         AXI_RBUSY;
input         AXI_WBUSY;
input         BREADY;
input         CLK;
input  [31:0] PADDR;
input         PCLK;
input         PENABLE;
input         PRESETN;
input         PSEL;
input  [31:0] PWDATA;
input         PWRITE;
input         RESET_N;
input         RLAST;
input         RREADY;
input         RVALID;
input  [63:0] WD;
input         WEN;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [63:0] DATA_INPUT;
output [31:0] PRDATA;
output        PREADY;
output        PSLVERR;
output        READ;
output [31:0] READ_ADDRESS;
output [3:0]  RLEN;
output [3:0]  WLEN;
output        WRITE;
output [31:0] WRITE_ADDRESS;
output        start_read;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          AXI_RBUSY;
wire          AXI_WBUSY;
wire   [31:0] PADDR;
wire          PENABLE;
wire   [31:0] BIF_1_PRDATA;
wire          BIF_1_PREADY;
wire          PSEL;
wire          BIF_1_PSLVERR;
wire   [31:0] PWDATA;
wire          PWRITE;
wire          BREADY;
wire          CLK;
wire   [63:0] DATA_INPUT_net_0;
wire   [8:0]  DATAHANDLE_FSM_0_ram_raddr;
wire          DATAHANDLE_FSM_0_ram_ren;
wire          DATAHANDLE_FSM_0_start_axi;
wire   [31:0] DATAHANDLE_FSM_0_user_address;
wire   [31:0] DATAHANDLE_FSM_0_user_data1;
wire   [31:0] DATAHANDLE_FSM_0_user_data2;
wire   [7:0]  DATAHANDLE_FSM_0_user_option;
wire          PCLK;
wire          PRESETN;
wire          READ_net_0;
wire   [31:0] READ_ADDRESS_net_0;
wire          RESET_N;
wire          RLAST;
wire   [3:0]  RLEN_net_0;
wire          RREADY;
wire          RVALID;
wire          start_read_net_0;
wire   [31:0] TPSRAM_0_RD;
wire   [7:0]  UART_IF_FSM_0_RAM_WADDR;
wire   [63:0] WD;
wire          WEN;
wire   [3:0]  WLEN_net_0;
wire          WRITE_net_0;
wire   [31:0] WRITE_ADDRESS_net_0;
wire          start_read_net_1;
wire          READ_net_1;
wire          WRITE_net_1;
wire          BIF_1_PREADY_net_0;
wire          BIF_1_PSLVERR_net_0;
wire   [31:0] WRITE_ADDRESS_net_1;
wire   [63:0] DATA_INPUT_net_1;
wire   [3:0]  WLEN_net_1;
wire   [31:0] READ_ADDRESS_net_1;
wire   [3:0]  RLEN_net_1;
wire   [31:0] BIF_1_PRDATA_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign start_read_net_1    = start_read_net_0;
assign start_read          = start_read_net_1;
assign READ_net_1          = READ_net_0;
assign READ                = READ_net_1;
assign WRITE_net_1         = WRITE_net_0;
assign WRITE               = WRITE_net_1;
assign BIF_1_PREADY_net_0  = BIF_1_PREADY;
assign PREADY              = BIF_1_PREADY_net_0;
assign BIF_1_PSLVERR_net_0 = BIF_1_PSLVERR;
assign PSLVERR             = BIF_1_PSLVERR_net_0;
assign WRITE_ADDRESS_net_1 = WRITE_ADDRESS_net_0;
assign WRITE_ADDRESS[31:0] = WRITE_ADDRESS_net_1;
assign DATA_INPUT_net_1    = DATA_INPUT_net_0;
assign DATA_INPUT[63:0]    = DATA_INPUT_net_1;
assign WLEN_net_1          = WLEN_net_0;
assign WLEN[3:0]           = WLEN_net_1;
assign READ_ADDRESS_net_1  = READ_ADDRESS_net_0;
assign READ_ADDRESS[31:0]  = READ_ADDRESS_net_1;
assign RLEN_net_1          = RLEN_net_0;
assign RLEN[3:0]           = RLEN_net_1;
assign BIF_1_PRDATA_net_0  = BIF_1_PRDATA;
assign PRDATA[31:0]        = BIF_1_PRDATA_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------DATAHANDLE_FSM
DATAHANDLE_FSM #( 
        .ADDR_WIDTH ( 32 ),
        .DATA_WIDTH ( 32 ) )
DATAHANDLE_FSM_0(
        // Inputs
        .PCLK         ( PCLK ),
        .PENABLE      ( PENABLE ),
        .PSEL         ( PSEL ),
        .PRESETN      ( PRESETN ),
        .PWRITE       ( PWRITE ),
        .PADDR        ( PADDR ),
        .PWDATA       ( PWDATA ),
        .ram_rdata    ( TPSRAM_0_RD ),
        // Outputs
        .PREADY       ( BIF_1_PREADY ),
        .PSLVERR      ( BIF_1_PSLVERR ),
        .ram_ren      ( DATAHANDLE_FSM_0_ram_ren ),
        .start_axi    ( DATAHANDLE_FSM_0_start_axi ),
        .PRDATA       ( BIF_1_PRDATA ),
        .ram_raddr    ( DATAHANDLE_FSM_0_ram_raddr ),
        .user_option  ( DATAHANDLE_FSM_0_user_option ),
        .user_address ( DATAHANDLE_FSM_0_user_address ),
        .user_data1   ( DATAHANDLE_FSM_0_user_data1 ),
        .user_data2   ( DATAHANDLE_FSM_0_user_data2 ) 
        );

//--------UART_IF_TPSRAM_0_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
UART_IF_TPSRAM_0_TPSRAM TPSRAM_0(
        // Inputs
        .WEN   ( WEN ),
        .REN   ( DATAHANDLE_FSM_0_ram_ren ),
        .WCLK  ( CLK ),
        .RCLK  ( PCLK ),
        .WD    ( WD ),
        .WADDR ( UART_IF_FSM_0_RAM_WADDR ),
        .RADDR ( DATAHANDLE_FSM_0_ram_raddr ),
        // Outputs
        .RD    ( TPSRAM_0_RD ) 
        );

//--------UART_IF_FSM
UART_IF_FSM UART_IF_FSM_0(
        // Inputs
        .CLK           ( CLK ),
        .RESET_N       ( RESET_N ),
        .AXI_WBUSY     ( AXI_WBUSY ),
        .AXI_RBUSY     ( AXI_RBUSY ),
        .RVALID        ( RVALID ),
        .RLAST         ( RLAST ),
        .BREADY        ( BREADY ),
        .RREADY        ( RREADY ),
        .start         ( DATAHANDLE_FSM_0_start_axi ),
        .user_option   ( DATAHANDLE_FSM_0_user_option ),
        .user_address  ( DATAHANDLE_FSM_0_user_address ),
        .user_data1    ( DATAHANDLE_FSM_0_user_data1 ),
        .user_data2    ( DATAHANDLE_FSM_0_user_data2 ),
        // Outputs
        .WRITE         ( WRITE_net_0 ),
        .READ          ( READ_net_0 ),
        .start_read    ( start_read_net_0 ),
        .WRITE_ADDRESS ( WRITE_ADDRESS_net_0 ),
        .READ_ADDRESS  ( READ_ADDRESS_net_0 ),
        .DATA_INPUT    ( DATA_INPUT_net_0 ),
        .RAM_WADDR     ( UART_IF_FSM_0_RAM_WADDR ),
        .WLEN          ( WLEN_net_0 ),
        .RLEN          ( RLEN_net_0 ) 
        );


endmodule
