# Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Thu Apr 8 02:08:11 2021

Design | top
Family | SmartFusion2
Die | M2S090TS
Package | 484 FBGA
Temperature Range | 0 - 85 C
Voltage Range | 1.14 - 1.26 V
Speed Grade | -1
Design State | Post-Layout
Data source | Production
Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST
Scenario for Timing Analysis | timing_analysis

## Summary

Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions
--- | --- | --- | --- | ---
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | 25.000 | 40.000 | 3.785 | WORST
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 | 6.250 | 160.000 | 0.506 | WORST
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 | 50.000 | 14.428 | WORST
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB | 25.000 | 40.000 | 1.491 | BEST

| Worst Slack (ns) | Operating Conditions
--- | --- | ---
Input to Output |  |

## Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0

### SET Register to Register

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[18] | 8.458 | 15.373 | 15.906 | 31.279 | 1.169 | 9.627 | WORST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[11] | 8.634 | 15.514 | 16.082 | 31.596 | 0.852 | 9.486 | WORST
Path 3 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[9] | 8.509 | 15.585 | 15.957 | 31.542 | 0.906 | 9.415 | WORST
Path 4 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[8] | 8.485 | 15.648 | 15.933 | 31.581 | 0.867 | 9.352 | WORST
Path 5 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[15] | 8.358 | 15.680 | 15.806 | 31.486 | 0.962 | 9.320 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE |  |  |  |  |  |  |  |
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[18] |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 31.279 |  |
data arrival time |  |  |  | - |  | 15.906 |  |
slack |  |  |  |  |  | 15.373 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 5.044 | 5.044 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 5.502 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 5.680 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.625 | 6.305 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 6.621 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR |  | + | 0.402 | 7.023 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell |  | ADLIB:IP_INTERFACE | + | 0.209 | 7.232 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net |  | + | 0.216 | 7.448 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_ADDR[10] | cell |  | ADLIB:MSS_075_IP | + | 1.398 | 8.846 | 2 | f
UART_IF_0/DATAHANDLE_FSM_0/PRDATA9_0_a2_4:D | net | MDDR_Demo_top_0_AMBA_SLAVE_0_PADDR[10] |  | + | 0.629 | 9.475 |  | f
UART_IF_0/DATAHANDLE_FSM_0/PRDATA9_0_a2_4:Y | cell |  | ADLIB:CFG4 | + | 0.315 | 9.790 | 1 | r
UART_IF_0/DATAHANDLE_FSM_0/PRDATA9_0_a2:D | net | UART_IF_0/DATAHANDLE_FSM_0/PRDATA9_0_a2_4 |  | + | 1.061 | 10.851 |  | r
UART_IF_0/DATAHANDLE_FSM_0/PRDATA9_0_a2:Y | cell |  | ADLIB:CFG4 | + | 0.158 | 11.009 | 4 | r
UART_IF_0/DATAHANDLE_FSM_0/PRDATA11_0_a3:C | net | UART_IF_0/DATAHANDLE_FSM_0/N_57 |  | + | 0.645 | 11.654 |  | r
UART_IF_0/DATAHANDLE_FSM_0/PRDATA11_0_a3:Y | cell |  | ADLIB:CFG3 | + | 0.072 | 11.726 | 33 | r
UART_IF_0/DATAHANDLE_FSM_0/PRDATA_1[18]:B | net | UART_IF_0/DATAHANDLE_FSM_0/PRDATA11 |  | + | 1.497 | 13.223 |  | r
UART_IF_0/DATAHANDLE_FSM_0/PRDATA_1[18]:Y | cell |  | ADLIB:CFG3 | + | 0.158 | 13.381 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNO_17:C | net | UART_IF_0.DATAHANDLE_FSM_0.N_319 |  | + | 0.882 | 14.263 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNO_17:Y | cell |  | ADLIB:CFG4 | + | 0.202 | 14.465 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_13:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/AMBA_SLAVE_0_PRDATAS0_m[18] |  | + | 1.020 | 15.485 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_13:IPA | cell |  | ADLIB:IP_INTERFACE | + | 0.194 | 15.679 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[18] | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[18] |  | + | 0.227 | 15.906 |  | r
data arrival time |  |  |  |  |  | 15.906 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | Clock Constraint |  |  |  | 25.000 | 25.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 25.000 |  | r
| Clock generation |  |  | + | 5.044 | 30.044 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 30.502 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 30.680 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.625 | 31.305 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 31.621 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR |  | + | 0.402 | 32.023 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell |  | ADLIB:IP_INTERFACE | + | 0.209 | 32.232 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net |  | + | 0.216 | 32.448 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[18] | Library setup time |  | ADLIB:MSS_075_IP | - | 1.169 | 31.279 |  |
data required time |  |  |  |  |  | 31.279 |  |
Operating Conditions | WORST

### SET External Setup

No Path

### SET Clock to Output

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/INIT_DONE_int:CLK | INIT_DONE | 9.168 |  | 16.280 |  | 16.280 | WORST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MMUART_1_TXD | 6.004 |  | 13.452 |  | 13.452 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/INIT_DONE_int:CLK |  |  |  |  |  |  |  |
To: INIT_DONE |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | N/C |  |
data arrival time |  |  |  | - |  | 16.280 |  |
slack |  |  |  |  |  | N/C |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 5.044 | 5.044 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 5.502 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 5.680 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.621 | 6.301 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR | cell |  | ADLIB:RGB | + | 0.316 | 6.617 | 30 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/INIT_DONE_int:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 |  | + | 0.495 | 7.112 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/INIT_DONE_int:Q | cell |  | ADLIB:SLE | + | 0.108 | 7.220 | 4 | f
INIT_DONE_obuf/U0/U_IOOUTFF:A | net | MDDR_Demo_top_0.MDDR_Demo_0.MDDR_Demo_sb_0.CORERESETP_0.INIT_DONE_int |  | + | 6.022 | 13.242 |  | f
INIT_DONE_obuf/U0/U_IOOUTFF:Y | cell |  | ADLIB:IOOUTFF_BYPASS | + | 0.330 | 13.572 | 1 | f
INIT_DONE_obuf/U0/U_IOPAD:D | net | INIT_DONE_obuf/U0/DOUT |  | + | 0.042 | 13.614 |  | f
INIT_DONE_obuf/U0/U_IOPAD:PAD | cell |  | ADLIB:IOPAD_TRI | + | 2.666 | 16.280 | 0 | f
INIT_DONE | net | INIT_DONE |  | + | 0.000 | 16.280 |  | f
data arrival time |  |  |  |  |  | 16.280 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 |  |  |  |  | N/C | N/C |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | N/C |  | r
| Clock generation |  |  | + | 5.044 | N/C |  |
INIT_DONE |  |  |  |  |  | N/C |  | f
Operating Conditions | WORST

### SET Register to Asynchronous

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr_enable:ALn | 5.260 | 19.415 | 12.370 | 31.785 | 0.353 | 5.585 | -0.028 | WORST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn | 5.260 | 19.415 | 12.370 | 31.785 | 0.353 | 5.585 | -0.028 | WORST
Path 3 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/CONFIG1_DONE_q1:ALn | 5.260 | 19.415 | 12.370 | 31.785 | 0.353 | 5.585 | -0.028 | WORST
Path 4 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn | 5.260 | 19.415 | 12.370 | 31.785 | 0.353 | 5.585 | -0.028 | WORST
Path 5 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sdif3_spll_lock_q2:ALn | 5.259 | 19.416 | 12.369 | 31.785 | 0.353 | 5.584 | -0.028 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK |  |  |  |  |  |  |  |
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr_enable:ALn |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 31.785 |  |
data arrival time |  |  |  | - |  | 12.370 |  |
slack |  |  |  |  |  | 19.415 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 5.044 | 5.044 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 5.502 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 5.680 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.613 | 6.293 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR | cell |  | ADLIB:RGB | + | 0.316 | 6.609 | 4 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1 |  | + | 0.501 | 7.110 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base:Q | cell |  | ADLIB:SLE | + | 0.087 | 7.197 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNIA34F:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_0 |  | + | 3.298 | 10.495 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNIA34F:YEn | cell |  | ADLIB:GBM | + | 0.374 | 10.869 | 4 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNIA34F/U0_RGB1_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNIA34F/U0_YWn_GEast |  | + | 0.614 | 11.483 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNIA34F/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 11.799 | 15 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr_enable:ALn | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_clk_base_RNIA34F/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.571 | 12.370 |  | r
data arrival time |  |  |  |  |  | 12.370 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | Clock Constraint |  |  |  | 25.000 | 25.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 25.000 |  | r
| Clock generation |  |  | + | 5.044 | 30.044 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 30.502 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 30.680 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.617 | 31.297 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR | cell |  | ADLIB:RGB | + | 0.316 | 31.613 | 15 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr_enable:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1 |  | + | 0.525 | 32.138 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr_enable:ALn | Library recovery time |  | ADLIB:SLE | - | 0.353 | 31.785 |  |
data required time |  |  |  |  |  | 31.785 |  |
Operating Conditions | WORST

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

### SET MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0

No Path

### SET MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB to MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0

No Path

### SET MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 to MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWSIZE_HSIZE0[1] | 1.402 | 3.785 | 8.316 | 12.101 | 1.591 | WORST
Path 2 | MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWSIZE_HSIZE0[0] | 1.403 | 3.877 | 8.317 | 12.194 | 1.498 | WORST
Path 3 | MDDR_Demo_top_0/AXI_IF_0/WSTRB_1[0]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[6] | 1.421 | 4.086 | 8.353 | 12.439 | 1.253 | WORST
Path 4 | MDDR_Demo_top_0/AXI_IF_0/ARADDR[2]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_ARADDR_HADDR1[2] | 1.169 | 4.093 | 8.109 | 12.202 | 1.490 | WORST
Path 5 | MDDR_Demo_top_0/AXI_IF_0/WSTRB_1[0]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_WSTRB[1] | 1.428 | 4.109 | 8.360 | 12.469 | 1.223 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:CLK |  |  |  |  |  |  |  |
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWSIZE_HSIZE0[1] |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 12.101 |  |
data arrival time |  |  |  | - |  | 8.316 |  |
slack |  |  |  |  |  | 3.785 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 4.838 | 4.838 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_net |  | + | 0.461 | 5.299 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 5.477 | 9 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_YWn_GEast |  | + | 0.599 | 6.076 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 6.392 | 85 | r
MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.522 | 6.914 |  | r
MDDR_Demo_top_0/AXI_IF_0/AWSIZE_1[0]:Q | cell |  | ADLIB:SLE | + | 0.108 | 7.022 | 3 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_215:A | net | MDDR_Demo_top_0/AXI_IF_0_BIF_1_AWSIZE[0] |  | + | 0.880 | 7.902 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_215:IPA | cell |  | ADLIB:IP_INTERFACE | + | 0.199 | 8.101 | 1 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWSIZE_HSIZE0[1] | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/F_AWSIZE_HSIZE0_net[1] |  | + | 0.215 | 8.316 |  | f
data arrival time |  |  |  |  |  | 8.316 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 | Clock Constraint |  |  |  | 6.250 | 6.250 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 6.250 |  | r
| Clock generation |  |  | + | 5.044 | 11.294 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 11.752 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 11.930 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.625 | 12.555 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 12.871 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR |  | + | 0.402 | 13.273 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell |  | ADLIB:IP_INTERFACE | + | 0.209 | 13.482 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net |  | + | 0.210 | 13.692 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_AWSIZE_HSIZE0[1] | Library setup time |  | ADLIB:MSS_075_IP | - | 1.591 | 12.101 |  |
data required time |  |  |  |  |  | 12.101 |  |
Operating Conditions | WORST

## Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2

### SET Register to Register

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK | UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | 4.151 | 1.831 | 11.071 | 12.902 | 0.254 | 4.419 | WORST
Path 2 | MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK | UART_IF_0/UART_IF_FSM_0/AXI_address[11]:D | 4.125 | 1.870 | 11.045 | 12.915 | 0.254 | 4.380 | WORST
Path 3 | MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK | UART_IF_0/UART_IF_FSM_0/AXI_address[26]:D | 4.070 | 1.925 | 10.990 | 12.915 | 0.254 | 4.325 | WORST
Path 4 | MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK | UART_IF_0/UART_IF_FSM_0/AXI_address[29]:D | 4.021 | 1.982 | 10.941 | 12.923 | 0.254 | 4.268 | WORST
Path 5 | UART_IF_0/UART_IF_FSM_0/fsm[7]:CLK | UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | 3.977 | 1.988 | 10.914 | 12.902 | 0.254 | 4.262 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK |  |  |  |  |  |  |  |
To: UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 12.902 |  |
data arrival time |  |  |  | - |  | 11.071 |  |
slack |  |  |  |  |  | 1.831 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 4.838 | 4.838 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_net |  | + | 0.461 | 5.299 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 5.477 | 9 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_YWn_GEast |  | + | 0.599 | 6.076 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 6.392 | 85 | r
MDDR_Demo_top_0/AXI_IF_0/BREADY:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.528 | 6.920 |  | r
MDDR_Demo_top_0/AXI_IF_0/BREADY:Q | cell |  | ADLIB:SLE | + | 0.108 | 7.028 | 6 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3[8]:A | net | MDDR_Demo_top_0_BREADY |  | + | 0.438 | 7.466 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3[8]:Y | cell |  | ADLIB:CFG2 | + | 0.164 | 7.630 | 3 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNITNHC1[8]:C | net | UART_IF_0/UART_IF_FSM_0/fsm_ns[8] |  | + | 0.673 | 8.303 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNITNHC1[8]:Y | cell |  | ADLIB:CFG4 | + | 0.087 | 8.390 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]:D | net | UART_IF_0/UART_IF_FSM_0/AXI_address_9_0_49_1 |  | + | 0.507 | 8.897 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]:P | cell |  | ADLIB:ARI1_CC | + | 0.423 | 9.320 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_0:P[0] | net | NET_CC_CONFIG274 |  | + | 0.000 | 9.320 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_0:CO | cell |  | ADLIB:CC_CONFIG | + | 0.580 | 9.900 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_1:CI | net | CI_TO_CO272 |  | + | 0.000 | 9.900 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_1:CO | cell |  | ADLIB:CC_CONFIG | + | 0.185 | 10.085 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_2:CI | net | CI_TO_CO273 |  | + | 0.000 | 10.085 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_2:CC[0] | cell |  | ADLIB:CC_CONFIG | + | 0.116 | 10.201 | 1 | f
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIT41LJ[30]:CC | net | NET_CC_CONFIG348 |  | + | 0.000 | 10.201 |  | f
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIT41LJ[30]:S | cell |  | ADLIB:ARI1_CC | + | 0.056 | 10.257 | 1 | r
UART_IF_0/UART_IF_FSM_0/AXI_address_9[30]:C | net | UART_IF_0/UART_IF_FSM_0/N_424 |  | + | 0.436 | 10.693 |  | r
UART_IF_0/UART_IF_FSM_0/AXI_address_9[30]:Y | cell |  | ADLIB:CFG3 | + | 0.074 | 10.767 | 1 | r
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | net | UART_IF_0/UART_IF_FSM_0/AXI_address_9[30] |  | + | 0.304 | 11.071 |  | r
data arrival time |  |  |  |  |  | 11.071 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 | Clock Constraint |  |  |  | 6.250 | 6.250 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 | Clock source |  |  | + | 0.000 | 6.250 |  | r
| Clock generation |  |  | + | 4.838 | 11.088 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_net |  | + | 0.461 | 11.549 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 11.727 | 9 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_YWn_GEast |  | + | 0.599 | 12.326 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 12.642 | 85 | r
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.514 | 13.156 |  | r
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | Library setup time |  | ADLIB:SLE | - | 0.254 | 12.902 |  |
data required time |  |  |  |  |  | 12.902 |  |
Operating Conditions | WORST

### SET External Setup

No Path

### SET Clock to Output

No Path

### SET Register to Asynchronous

No Path

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

### SET MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 to MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | 4.948 | 0.506 | 12.396 | 12.902 | 0.254 | WORST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | UART_IF_0/UART_IF_FSM_0/AXI_address[11]:D | 4.922 | 0.545 | 12.370 | 12.915 | 0.254 | WORST
Path 3 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | UART_IF_0/UART_IF_FSM_0/AXI_address[26]:D | 4.867 | 0.600 | 12.315 | 12.915 | 0.254 | WORST
Path 4 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | UART_IF_0/UART_IF_FSM_0/AXI_address[29]:D | 4.818 | 0.657 | 12.266 | 12.923 | 0.254 | WORST
Path 5 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | UART_IF_0/UART_IF_FSM_0/AXI_address[31]:D | 4.801 | 0.666 | 12.249 | 12.915 | 0.254 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE |  |  |  |  |  |  |  |
To: UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 12.902 |  |
data arrival time |  |  |  | - |  | 12.396 |  |
slack |  |  |  |  |  | 0.506 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 5.044 | 5.044 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_net |  | + | 0.458 | 5.502 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 5.680 | 10 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.625 | 6.305 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 6.621 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0_INST/U0_RGB1_YR |  | + | 0.402 | 7.023 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell |  | ADLIB:IP_INTERFACE | + | 0.209 | 7.232 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net |  | + | 0.216 | 7.448 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_RVALID | cell |  | ADLIB:MSS_075_IP | + | 2.092 | 9.540 | 10 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]:C | net | MDDR_Demo_top_0_AMBA_MASTER_0_RVALID_M0 |  | + | 0.862 | 10.402 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]:P | cell |  | ADLIB:ARI1_CC | + | 0.243 | 10.645 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_0:P[0] | net | NET_CC_CONFIG274 |  | + | 0.000 | 10.645 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_0:CO | cell |  | ADLIB:CC_CONFIG | + | 0.580 | 11.225 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_1:CI | net | CI_TO_CO272 |  | + | 0.000 | 11.225 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_1:CO | cell |  | ADLIB:CC_CONFIG | + | 0.185 | 11.410 | 1 | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_2:CI | net | CI_TO_CO273 |  | + | 0.000 | 11.410 |  | f
UART_IF_0/UART_IF_FSM_0/fsm_ns_a3_RNI7F0I2[8]_CC_2:CC[0] | cell |  | ADLIB:CC_CONFIG | + | 0.116 | 11.526 | 1 | f
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIT41LJ[30]:CC | net | NET_CC_CONFIG348 |  | + | 0.000 | 11.526 |  | f
UART_IF_0/UART_IF_FSM_0/AXI_address_RNIT41LJ[30]:S | cell |  | ADLIB:ARI1_CC | + | 0.056 | 11.582 | 1 | r
UART_IF_0/UART_IF_FSM_0/AXI_address_9[30]:C | net | UART_IF_0/UART_IF_FSM_0/N_424 |  | + | 0.436 | 12.018 |  | r
UART_IF_0/UART_IF_FSM_0/AXI_address_9[30]:Y | cell |  | ADLIB:CFG3 | + | 0.074 | 12.092 | 1 | r
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | net | UART_IF_0/UART_IF_FSM_0/AXI_address_9[30] |  | + | 0.304 | 12.396 |  | r
data arrival time |  |  |  |  |  | 12.396 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2 | Clock Constraint |  |  |  | 6.250 | 6.250 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 | Clock source |  |  | + | 0.000 | 6.250 |  | r
| Clock generation |  |  | + | 4.838 | 11.088 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_net |  | + | 0.461 | 11.549 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 11.727 | 9 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_YWn_GEast |  | + | 0.599 | 12.326 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 12.642 | 85 | r
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL2_INST/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.514 | 13.156 |  | r
UART_IF_0/UART_IF_FSM_0/AXI_address[30]:D | Library setup time |  | ADLIB:SLE | - | 0.254 | 12.902 |  |
data required time |  |  |  |  |  | 12.902 |  |
Operating Conditions | WORST

## Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

### SET Register to Register

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[7]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | 1.970 | 17.669 | 10.683 | 28.352 | 0.308 | 2.331 | WORST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[2]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | 1.938 | 17.713 | 10.639 | 28.352 | 0.308 | 2.287 | WORST
Path 3 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[6]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | 1.924 | 17.727 | 10.625 | 28.352 | 0.308 | 2.273 | WORST
Path 4 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[1]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | 1.879 | 17.760 | 10.592 | 28.352 | 0.308 | 2.240 | WORST
Path 5 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[5]:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | 1.868 | 17.771 | 10.581 | 28.352 | 0.308 | 2.229 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[7]:CLK |  |  |  |  |  |  |  |
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 28.352 |  |
data arrival time |  |  |  | - |  | 10.683 |  |
slack |  |  |  |  |  | 17.669 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 0.000 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 3.101 | 3.101 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 3.253 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 3.619 | 6.872 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell |  | ADLIB:GBM | + | 0.374 | 7.246 | 3 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast |  | + | 0.605 | 7.851 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR | cell |  | ADLIB:RGB | + | 0.316 | 8.167 | 18 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[7]:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 |  | + | 0.546 | 8.713 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[7]:Q | cell |  | ADLIB:SLE | + | 0.087 | 8.800 | 2 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled4_6:B | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[7] |  | + | 0.603 | 9.403 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled4_6:Y | cell |  | ADLIB:CFG2 | + | 0.143 | 9.546 | 1 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled4:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled4_6 |  | + | 0.304 | 9.850 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled4:Y | cell |  | ADLIB:CFG4 | + | 0.287 | 10.137 | 1 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled4 |  | + | 0.546 | 10.683 |  | f
data arrival time |  |  |  |  |  | 10.683 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 20.000 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 3.101 | 23.101 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 23.253 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 3.619 | 26.872 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell |  | ADLIB:GBM | + | 0.374 | 27.246 | 3 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast |  | + | 0.605 | 27.851 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR | cell |  | ADLIB:RGB | + | 0.316 | 28.167 | 18 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 |  | + | 0.493 | 28.660 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/ddr_settled:EN | Library setup time |  | ADLIB:SLE | - | 0.308 | 28.352 |  |
data required time |  |  |  |  |  | 28.352 |  |
Operating Conditions | WORST

### SET External Setup

No Path

### SET Clock to Output

No Path

### SET Register to Asynchronous

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[6]:ALn | 5.208 | 14.428 | 13.904 | 28.332 | 0.353 | 5.572 | 0.011 | WORST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[4]:ALn | 5.208 | 14.428 | 13.904 | 28.332 | 0.353 | 5.572 | 0.011 | WORST
Path 3 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[2]:ALn | 5.208 | 14.428 | 13.904 | 28.332 | 0.353 | 5.572 | 0.011 | WORST
Path 4 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[12]:ALn | 5.183 | 14.428 | 13.879 | 28.307 | 0.353 | 5.572 | 0.036 | WORST
Path 5 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[10]:ALn | 5.208 | 14.428 | 13.904 | 28.332 | 0.353 | 5.572 | 0.011 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK |  |  |  |  |  |  |  |
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[6]:ALn |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 28.332 |  |
data arrival time |  |  |  | - |  | 13.904 |  |
slack |  |  |  |  |  | 14.428 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 0.000 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 3.101 | 3.101 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 3.253 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 3.619 | 6.872 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell |  | ADLIB:GBM | + | 0.374 | 7.246 | 3 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast |  | + | 0.601 | 7.847 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 8.163 | 11 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1 |  | + | 0.533 | 8.696 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc:Q | cell |  | ADLIB:SLE | + | 0.087 | 8.783 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIGFM6:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_0 |  | + | 3.260 | 12.043 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIGFM6:YEn | cell |  | ADLIB:GBM | + | 0.374 | 12.417 | 1 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIGFM6/U0_RGB1:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIGFM6/U0_YWn_GEast |  | + | 0.595 | 13.012 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIGFM6/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 13.328 | 17 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[6]:ALn | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/sm0_areset_n_rcosc_RNIGFM6/U0_RGB1_YR |  | + | 0.576 | 13.904 |  | r
data arrival time |  |  |  |  |  | 13.904 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint |  |  |  | 20.000 | 20.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source |  |  | + | 0.000 | 20.000 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC |  | + | 3.101 | 23.101 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell |  | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 23.253 | 1 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT |  | + | 3.619 | 26.872 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell |  | ADLIB:GBM | + | 0.374 | 27.246 | 3 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast |  | + | 0.605 | 27.851 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR | cell |  | ADLIB:RGB | + | 0.316 | 28.167 | 18 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[6]:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 |  | + | 0.518 | 28.685 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORERESETP_0/count_ddr[6]:ALn | Library recovery time |  | ADLIB:SLE | - | 0.353 | 28.332 |  |
data required time |  |  |  |  |  | 28.332 |  |
Operating Conditions | WORST

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

### SET MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 to MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

No Path

## Clock Domain MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB

### SET Register to Register

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | 2.037 | 1.491 | 2.037 | 3.528 | 0.245 | -1.491 | BEST
Path 2 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/state[0]:D | 1.434 | 2.131 | 1.434 | 3.565 | 0.201 | -2.131 | BEST
Path 3 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/psel:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | 3.146 | 8.854 | 8.806 | 17.660 | 0.308 | 7.292 | WORST
Path 4 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/psel:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[10]:D | 3.015 | 9.052 | 8.675 | 17.727 | 0.254 | 6.896 | WORST
Path 5 | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/psel:CLK | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:D | 2.975 | 9.107 | 8.635 | 17.742 | 0.254 | 6.786 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB |  |  |  |  |  |  |  |
To: MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | 3.528 |  |
data arrival time |  |  |  | - |  | 2.037 |  |
slack |  |  |  |  |  | 1.491 |  |
Data arrival time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB |  |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | Clock source |  |  | + | 0.000 | 0.000 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PENABLE | cell |  | ADLIB:MSS_075_IP | + | 0.587 | 0.587 | 2 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/next_state4:A | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE |  | + | 0.522 | 1.109 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/next_state4:Y | cell |  | ADLIB:CFG2 | + | 0.098 | 1.207 | 2 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:C | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/next_state4 |  | + | 0.153 | 1.360 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:Y | cell |  | ADLIB:CFG4 | + | 0.060 | 1.420 | 1 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 |  | + | 0.617 | 2.037 |  | f
data arrival time |  |  |  |  |  | 2.037 |  |
Data required time calculation |  |  |  |  |  |  |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB | Max Delay Constraint |  |  |  | 0.000 | 0.000 |  |
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | Clock source |  |  | + | 0.000 | 0.000 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNINJTB:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB |  | + | 2.531 | 2.531 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNINJTB:YEn | cell |  | ADLIB:GBM | + | 0.257 | 2.788 | 7 | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNINJTB/U0_RGB1_RGB5:An | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNINJTB/U0_YWn_GEast |  | + | 0.412 | 3.200 |  | f
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNINJTB/U0_RGB1_RGB5:YR | cell |  | ADLIB:RGB | + | 0.218 | 3.418 | 6 | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK | net | MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/MSS_ADLIB_INST_RNINJTB/U0_RGB1_RGB5_rgbr_net_1 |  | + | 0.355 | 3.773 |  | r
MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | Library setup time |  | ADLIB:SLE | - | 0.245 | 3.528 |  |
data required time |  |  |  |  |  | 3.528 |  |
Operating Conditions | BEST

### SET External Setup

No Path

### SET Clock to Output

No Path

### SET Register to Asynchronous

No Path

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

### SET MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/CCC_0/GL0 to MDDR_Demo_top_0/MDDR_Demo_0/MDDR_Demo_sb_0/MDDR_Demo_sb_MSS_0/CLK_CONFIG_APB

No Path

## Path Set Pin to Pin

### SET Input to Output

No Path

## Path Set User Sets