`timescale 1 ns/100 ps
// Version: v11.8 SP1 11.8.1.12


module UART_IF_TPSRAM_0_TPSRAM(
       WD,
       RD,
       WADDR,
       RADDR,
       WEN,
       REN,
       WCLK,
       RCLK
    );
input  [63:0] WD;
output [31:0] RD;
input  [7:0] WADDR;
input  [8:0] RADDR;
input  WEN;
input  REN;
input  WCLK;
input  RCLK;

    wire VCC, GND, ADLIB_VCC;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign ADLIB_VCC = VCC_power_net1;
    
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C2 (.A_DOUT({nc0, nc1, nc2, nc3, 
        nc4, nc5, nc6, nc7, nc8, nc9, RD[23], RD[22], RD[21], RD[20], 
        RD[19], RD[18], RD[17], RD[16]}), .B_DOUT({nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, 
        nc23, nc24, nc25, nc26, nc27}), .BUSY(), .A_CLK(RCLK), 
        .A_DOUT_CLK(VCC), .A_ARST_N(VCC), .A_DOUT_EN(VCC), .A_BLK({REN, 
        VCC, VCC}), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .A_DIN({
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .A_ADDR({GND, GND, RADDR[8], 
        RADDR[7], RADDR[6], RADDR[5], RADDR[4], RADDR[3], RADDR[2], 
        RADDR[1], RADDR[0], GND, GND, GND}), .A_WEN({GND, GND}), 
        .B_CLK(WCLK), .B_DOUT_CLK(VCC), .B_ARST_N(VCC), .B_DOUT_EN(VCC)
        , .B_BLK({WEN, VCC, VCC}), .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(
        VCC), .B_DIN({GND, WD[55], WD[54], WD[53], WD[52], WD[51], 
        WD[50], WD[49], WD[48], GND, WD[23], WD[22], WD[21], WD[20], 
        WD[19], WD[18], WD[17], WD[16]}), .B_ADDR({GND, GND, WADDR[7], 
        WADDR[6], WADDR[5], WADDR[4], WADDR[3], WADDR[2], WADDR[1], 
        WADDR[0], GND, GND, GND, GND}), .B_WEN({VCC, VCC}), .A_EN(VCC), 
        .A_DOUT_LAT(VCC), .A_WIDTH({GND, VCC, VCC}), .A_WMODE(GND), 
        .B_EN(VCC), .B_DOUT_LAT(VCC), .B_WIDTH({VCC, GND, GND}), 
        .B_WMODE(GND), .SII_LOCK(GND));
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C3 (.A_DOUT({nc28, nc29, nc30, 
        nc31, nc32, nc33, nc34, nc35, nc36, nc37, RD[31], RD[30], 
        RD[29], RD[28], RD[27], RD[26], RD[25], RD[24]}), .B_DOUT({
        nc38, nc39, nc40, nc41, nc42, nc43, nc44, nc45, nc46, nc47, 
        nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55}), .BUSY(), 
        .A_CLK(RCLK), .A_DOUT_CLK(VCC), .A_ARST_N(VCC), .A_DOUT_EN(VCC)
        , .A_BLK({REN, VCC, VCC}), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(
        VCC), .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND}), .A_ADDR({GND, GND, 
        RADDR[8], RADDR[7], RADDR[6], RADDR[5], RADDR[4], RADDR[3], 
        RADDR[2], RADDR[1], RADDR[0], GND, GND, GND}), .A_WEN({GND, 
        GND}), .B_CLK(WCLK), .B_DOUT_CLK(VCC), .B_ARST_N(VCC), 
        .B_DOUT_EN(VCC), .B_BLK({WEN, VCC, VCC}), .B_DOUT_ARST_N(GND), 
        .B_DOUT_SRST_N(VCC), .B_DIN({GND, WD[63], WD[62], WD[61], 
        WD[60], WD[59], WD[58], WD[57], WD[56], GND, WD[31], WD[30], 
        WD[29], WD[28], WD[27], WD[26], WD[25], WD[24]}), .B_ADDR({GND, 
        GND, WADDR[7], WADDR[6], WADDR[5], WADDR[4], WADDR[3], 
        WADDR[2], WADDR[1], WADDR[0], GND, GND, GND, GND}), .B_WEN({
        VCC, VCC}), .A_EN(VCC), .A_DOUT_LAT(VCC), .A_WIDTH({GND, VCC, 
        VCC}), .A_WMODE(GND), .B_EN(VCC), .B_DOUT_LAT(VCC), .B_WIDTH({
        VCC, GND, GND}), .B_WMODE(GND), .SII_LOCK(GND));
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C0 (.A_DOUT({nc56, nc57, nc58, 
        nc59, nc60, nc61, nc62, nc63, nc64, nc65, RD[7], RD[6], RD[5], 
        RD[4], RD[3], RD[2], RD[1], RD[0]}), .B_DOUT({nc66, nc67, nc68, 
        nc69, nc70, nc71, nc72, nc73, nc74, nc75, nc76, nc77, nc78, 
        nc79, nc80, nc81, nc82, nc83}), .BUSY(), .A_CLK(RCLK), 
        .A_DOUT_CLK(VCC), .A_ARST_N(VCC), .A_DOUT_EN(VCC), .A_BLK({REN, 
        VCC, VCC}), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .A_DIN({
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND}), .A_ADDR({GND, GND, RADDR[8], 
        RADDR[7], RADDR[6], RADDR[5], RADDR[4], RADDR[3], RADDR[2], 
        RADDR[1], RADDR[0], GND, GND, GND}), .A_WEN({GND, GND}), 
        .B_CLK(WCLK), .B_DOUT_CLK(VCC), .B_ARST_N(VCC), .B_DOUT_EN(VCC)
        , .B_BLK({WEN, VCC, VCC}), .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(
        VCC), .B_DIN({GND, WD[39], WD[38], WD[37], WD[36], WD[35], 
        WD[34], WD[33], WD[32], GND, WD[7], WD[6], WD[5], WD[4], WD[3], 
        WD[2], WD[1], WD[0]}), .B_ADDR({GND, GND, WADDR[7], WADDR[6], 
        WADDR[5], WADDR[4], WADDR[3], WADDR[2], WADDR[1], WADDR[0], 
        GND, GND, GND, GND}), .B_WEN({VCC, VCC}), .A_EN(VCC), 
        .A_DOUT_LAT(VCC), .A_WIDTH({GND, VCC, VCC}), .A_WMODE(GND), 
        .B_EN(VCC), .B_DOUT_LAT(VCC), .B_WIDTH({VCC, GND, GND}), 
        .B_WMODE(GND), .SII_LOCK(GND));
    RAM1K18 UART_IF_TPSRAM_0_TPSRAM_R0C1 (.A_DOUT({nc84, nc85, nc86, 
        nc87, nc88, nc89, nc90, nc91, nc92, nc93, RD[15], RD[14], 
        RD[13], RD[12], RD[11], RD[10], RD[9], RD[8]}), .B_DOUT({nc94, 
        nc95, nc96, nc97, nc98, nc99, nc100, nc101, nc102, nc103, 
        nc104, nc105, nc106, nc107, nc108, nc109, nc110, nc111}), 
        .BUSY(), .A_CLK(RCLK), .A_DOUT_CLK(VCC), .A_ARST_N(VCC), 
        .A_DOUT_EN(VCC), .A_BLK({REN, VCC, VCC}), .A_DOUT_ARST_N(VCC), 
        .A_DOUT_SRST_N(VCC), .A_DIN({GND, GND, GND, GND, GND, GND, GND, 
        GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
        .A_ADDR({GND, GND, RADDR[8], RADDR[7], RADDR[6], RADDR[5], 
        RADDR[4], RADDR[3], RADDR[2], RADDR[1], RADDR[0], GND, GND, 
        GND}), .A_WEN({GND, GND}), .B_CLK(WCLK), .B_DOUT_CLK(VCC), 
        .B_ARST_N(VCC), .B_DOUT_EN(VCC), .B_BLK({WEN, VCC, VCC}), 
        .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .B_DIN({GND, WD[47], 
        WD[46], WD[45], WD[44], WD[43], WD[42], WD[41], WD[40], GND, 
        WD[15], WD[14], WD[13], WD[12], WD[11], WD[10], WD[9], WD[8]}), 
        .B_ADDR({GND, GND, WADDR[7], WADDR[6], WADDR[5], WADDR[4], 
        WADDR[3], WADDR[2], WADDR[1], WADDR[0], GND, GND, GND, GND}), 
        .B_WEN({VCC, VCC}), .A_EN(VCC), .A_DOUT_LAT(VCC), .A_WIDTH({
        GND, VCC, VCC}), .A_WMODE(GND), .B_EN(VCC), .B_DOUT_LAT(VCC), 
        .B_WIDTH({VCC, GND, GND}), .B_WMODE(GND), .SII_LOCK(GND));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
