#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\m2s_dg0568_liberov11p8_sp1_df\SF2_MDDR_Demo_DF\Final\m2s_dg0534_df\Libero_Project\synthesis\run_options.txt
#--  Written on Thu Apr  8 02:03:45 2021


#project files
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/hdl/AXI_IF.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_sb/CCC_0/MDDR_Demo_sb_CCC_0_FCCC.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_sb/FABOSC_0/MDDR_Demo_sb_FABOSC_0_OSC.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_sb_MSS/MDDR_Demo_sb_MSS_syn.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_sb_MSS/MDDR_Demo_sb_MSS.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/CoreConfigP/7.1.100/rtl/vlog/core/coreconfigp.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_sb/COREAXI_0/rtl/vlog/core/coreaxi.v"
add_file -verilog -lib COREAPB3_LIB "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_sb/MDDR_Demo_sb.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo/MDDR_Demo.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/MDDR_Demo_top/MDDR_Demo_top.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/hdl/DATA_HANDLE_FSM.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/hdl/UART_IF_FSM.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/UART_IF/TPSRAM_0/UART_IF_TPSRAM_0_TPSRAM.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/UART_IF/UART_IF.v"
add_file -verilog "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/Users/I63442/Desktop/v12.6 updates/Smart fusion2/New folder/m2s_dg0568_liberov11p8_sp1_df/SF2_MDDR_Demo_DF/Final/m2s_dg0534_df/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S090TS
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip SmartFusion2
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.edn"
impl -active "synthesis"
