//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Sep 12 09:22:06 2017
// Version: v11.8 SP1 11.8.1.12
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// MDDR_Demo_top
module MDDR_Demo_top(
    // Inputs
    AMBA_SLAVE_0_PRDATAS0,
    AMBA_SLAVE_0_PREADYS0,
    AMBA_SLAVE_0_PSLVERRS0,
    ARADDR_int,
    AWADDR_int,
    DEVRST_N,
    MDDR_DQS_TMATCH_0_IN,
    MMUART_1_RXD,
    RLEN,
    WDATA_int_input,
    WLEN,
    read_start,
    write_start,
    // Outputs
    AMBA_MASTER_0_RDATA_M0,
    AMBA_MASTER_0_RLAST_M0,
    AMBA_MASTER_0_RVALID_M0,
    AMBA_SLAVE_0_PADDRS,
    AMBA_SLAVE_0_PENABLES,
    AMBA_SLAVE_0_PSELS0,
    AMBA_SLAVE_0_PWDATAS,
    AMBA_SLAVE_0_PWRITES,
    AXI_RBUSY,
    AXI_WBUSY,
    BREADY,
    FIC_0_CLK,
    INIT_DONE,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    MMUART_1_TXD,
    MSS_DDR_FIC_SUBSYSTEM_CLK,
    RREADY,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  [31:0] AMBA_SLAVE_0_PRDATAS0;
input         AMBA_SLAVE_0_PREADYS0;
input         AMBA_SLAVE_0_PSLVERRS0;
input  [31:0] ARADDR_int;
input  [31:0] AWADDR_int;
input         DEVRST_N;
input         MDDR_DQS_TMATCH_0_IN;
input         MMUART_1_RXD;
input  [3:0]  RLEN;
input  [63:0] WDATA_int_input;
input  [3:0]  WLEN;
input         read_start;
input         write_start;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [63:0] AMBA_MASTER_0_RDATA_M0;
output        AMBA_MASTER_0_RLAST_M0;
output        AMBA_MASTER_0_RVALID_M0;
output [31:0] AMBA_SLAVE_0_PADDRS;
output        AMBA_SLAVE_0_PENABLES;
output        AMBA_SLAVE_0_PSELS0;
output [31:0] AMBA_SLAVE_0_PWDATAS;
output        AMBA_SLAVE_0_PWRITES;
output        AXI_RBUSY;
output        AXI_WBUSY;
output        BREADY;
output        FIC_0_CLK;
output        INIT_DONE;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        MMUART_1_TXD;
output        MSS_DDR_FIC_SUBSYSTEM_CLK;
output        RREADY;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [63:0] AMBA_MASTER_0_RDATA_M0_net_0;
wire          AMBA_MASTER_0_RLAST_M0_net_0;
wire          AMBA_MASTER_0_RVALID_M0_net_0;
wire   [31:0] AMBA_SLAVE_0_PADDR;
wire          AMBA_SLAVE_0_PENABLE;
wire   [31:0] AMBA_SLAVE_0_PRDATAS0;
wire          AMBA_SLAVE_0_PREADYS0;
wire          AMBA_SLAVE_0_PSELx;
wire          AMBA_SLAVE_0_PSLVERRS0;
wire   [31:0] AMBA_SLAVE_0_PWDATA;
wire          AMBA_SLAVE_0_PWRITE;
wire   [31:0] ARADDR_int;
wire   [31:0] AWADDR_int;
wire   [31:0] AXI_IF_0_BIF_1_ARADDR;
wire   [1:0]  AXI_IF_0_BIF_1_ARBURST;
wire   [3:0]  AXI_IF_0_BIF_1_ARID;
wire   [3:0]  AXI_IF_0_BIF_1_ARLEN;
wire   [1:0]  AXI_IF_0_BIF_1_ARLOCK;
wire          AXI_IF_0_BIF_1_ARREADY;
wire          AXI_IF_0_BIF_1_ARVALID;
wire   [31:0] AXI_IF_0_BIF_1_AWADDR;
wire   [1:0]  AXI_IF_0_BIF_1_AWBURST;
wire   [3:0]  AXI_IF_0_BIF_1_AWID;
wire   [3:0]  AXI_IF_0_BIF_1_AWLEN;
wire   [1:0]  AXI_IF_0_BIF_1_AWLOCK;
wire          AXI_IF_0_BIF_1_AWREADY;
wire   [2:0]  AXI_IF_0_BIF_1_AWSIZE;
wire          AXI_IF_0_BIF_1_AWVALID;
wire   [3:0]  AXI_IF_0_BIF_1_BID;
wire          AXI_IF_0_BIF_1_BREADY;
wire   [1:0]  AXI_IF_0_BIF_1_BRESP;
wire          AXI_IF_0_BIF_1_BVALID;
wire   [3:0]  AXI_IF_0_BIF_1_RID;
wire          AXI_IF_0_BIF_1_RREADY;
wire   [1:0]  AXI_IF_0_BIF_1_RRESP;
wire   [63:0] AXI_IF_0_BIF_1_WDATA;
wire   [3:0]  AXI_IF_0_BIF_1_WID;
wire          AXI_IF_0_BIF_1_WLAST;
wire          AXI_IF_0_BIF_1_WREADY;
wire   [7:0]  AXI_IF_0_BIF_1_WSTRB;
wire          AXI_IF_0_BIF_1_WVALID;
wire          AXI_RBUSY_net_0;
wire          AXI_WBUSY_net_0;
wire          DEVRST_N;
wire          FIC_0_CLK_net_0;
wire          INIT_DONE_net_0;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          MMUART_1_RXD;
wire          MMUART_1_TXD_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_CLK_net_0;
wire          read_start;
wire   [3:0]  RLEN;
wire   [63:0] WDATA_int_input;
wire   [3:0]  WLEN;
wire          write_start;
wire          MMUART_1_TXD_net_1;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          AXI_RBUSY_net_1;
wire          AXI_WBUSY_net_1;
wire          FIC_0_CLK_net_1;
wire          INIT_DONE_net_1;
wire          MSS_DDR_FIC_SUBSYSTEM_CLK_net_1;
wire          AMBA_MASTER_0_RVALID_M0_net_1;
wire          AMBA_MASTER_0_RLAST_M0_net_1;
wire          AMBA_SLAVE_0_PSELx_net_0;
wire          AMBA_SLAVE_0_PENABLE_net_0;
wire          AMBA_SLAVE_0_PWRITE_net_0;
wire          AXI_IF_0_BIF_1_RREADY_net_0;
wire          AXI_IF_0_BIF_1_BREADY_net_0;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
wire   [63:0] AMBA_MASTER_0_RDATA_M0_net_1;
wire   [31:0] AMBA_SLAVE_0_PADDR_net_0;
wire   [31:0] AMBA_SLAVE_0_PWDATA_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
wire          VCC_net;
wire   [3:0]  AMBA_MASTER_0_AWCACHE_M0_const_net_0;
wire   [2:0]  AMBA_MASTER_0_AWPROT_M0_const_net_0;
wire   [3:0]  AMBA_MASTER_0_ARCACHE_M0_const_net_0;
wire   [2:0]  AMBA_MASTER_0_ARPROT_M0_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [1:0]  AXI_IF_0_BIF_1_ARSIZE;
wire   [2:2]  AXI_IF_0_BIF_1_ARSIZE_0_2to2;
wire   [1:0]  AXI_IF_0_BIF_1_ARSIZE_0_1to0;
wire   [2:0]  AXI_IF_0_BIF_1_ARSIZE_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net                              = 1'b0;
assign VCC_net                              = 1'b1;
assign AMBA_MASTER_0_AWCACHE_M0_const_net_0 = 4'h0;
assign AMBA_MASTER_0_AWPROT_M0_const_net_0  = 3'h0;
assign AMBA_MASTER_0_ARCACHE_M0_const_net_0 = 4'h0;
assign AMBA_MASTER_0_ARPROT_M0_const_net_0  = 3'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_1_TXD_net_1              = MMUART_1_TXD_net_0;
assign MMUART_1_TXD                    = MMUART_1_TXD_net_1;
assign MDDR_DQS_TMATCH_0_OUT_net_1     = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT           = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1                = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                      = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1                  = MDDR_CLK_net_0;
assign MDDR_CLK                        = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1                = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                      = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1                  = MDDR_CKE_net_0;
assign MDDR_CKE                        = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1                 = MDDR_CS_N_net_0;
assign MDDR_CS_N                       = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1                  = MDDR_ODT_net_0;
assign MDDR_ODT                        = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1                = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                      = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1              = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                    = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1                 = MDDR_WE_N_net_0;
assign MDDR_WE_N                       = MDDR_WE_N_net_1;
assign AXI_RBUSY_net_1                 = AXI_RBUSY_net_0;
assign AXI_RBUSY                       = AXI_RBUSY_net_1;
assign AXI_WBUSY_net_1                 = AXI_WBUSY_net_0;
assign AXI_WBUSY                       = AXI_WBUSY_net_1;
assign FIC_0_CLK_net_1                 = FIC_0_CLK_net_0;
assign FIC_0_CLK                       = FIC_0_CLK_net_1;
assign INIT_DONE_net_1                 = INIT_DONE_net_0;
assign INIT_DONE                       = INIT_DONE_net_1;
assign MSS_DDR_FIC_SUBSYSTEM_CLK_net_1 = MSS_DDR_FIC_SUBSYSTEM_CLK_net_0;
assign MSS_DDR_FIC_SUBSYSTEM_CLK       = MSS_DDR_FIC_SUBSYSTEM_CLK_net_1;
assign AMBA_MASTER_0_RVALID_M0_net_1   = AMBA_MASTER_0_RVALID_M0_net_0;
assign AMBA_MASTER_0_RVALID_M0         = AMBA_MASTER_0_RVALID_M0_net_1;
assign AMBA_MASTER_0_RLAST_M0_net_1    = AMBA_MASTER_0_RLAST_M0_net_0;
assign AMBA_MASTER_0_RLAST_M0          = AMBA_MASTER_0_RLAST_M0_net_1;
assign AMBA_SLAVE_0_PSELx_net_0        = AMBA_SLAVE_0_PSELx;
assign AMBA_SLAVE_0_PSELS0             = AMBA_SLAVE_0_PSELx_net_0;
assign AMBA_SLAVE_0_PENABLE_net_0      = AMBA_SLAVE_0_PENABLE;
assign AMBA_SLAVE_0_PENABLES           = AMBA_SLAVE_0_PENABLE_net_0;
assign AMBA_SLAVE_0_PWRITE_net_0       = AMBA_SLAVE_0_PWRITE;
assign AMBA_SLAVE_0_PWRITES            = AMBA_SLAVE_0_PWRITE_net_0;
assign AXI_IF_0_BIF_1_RREADY_net_0     = AXI_IF_0_BIF_1_RREADY;
assign RREADY                          = AXI_IF_0_BIF_1_RREADY_net_0;
assign AXI_IF_0_BIF_1_BREADY_net_0     = AXI_IF_0_BIF_1_BREADY;
assign BREADY                          = AXI_IF_0_BIF_1_BREADY_net_0;
assign MDDR_ADDR_net_1                 = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]                 = MDDR_ADDR_net_1;
assign MDDR_BA_net_1                   = MDDR_BA_net_0;
assign MDDR_BA[2:0]                    = MDDR_BA_net_1;
assign AMBA_MASTER_0_RDATA_M0_net_1    = AMBA_MASTER_0_RDATA_M0_net_0;
assign AMBA_MASTER_0_RDATA_M0[63:0]    = AMBA_MASTER_0_RDATA_M0_net_1;
assign AMBA_SLAVE_0_PADDR_net_0        = AMBA_SLAVE_0_PADDR;
assign AMBA_SLAVE_0_PADDRS[31:0]       = AMBA_SLAVE_0_PADDR_net_0;
assign AMBA_SLAVE_0_PWDATA_net_0       = AMBA_SLAVE_0_PWDATA;
assign AMBA_SLAVE_0_PWDATAS[31:0]      = AMBA_SLAVE_0_PWDATA_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign AXI_IF_0_BIF_1_ARSIZE_0_2to2 = 1'b0;
assign AXI_IF_0_BIF_1_ARSIZE_0_1to0 = AXI_IF_0_BIF_1_ARSIZE[1:0];
assign AXI_IF_0_BIF_1_ARSIZE_0 = { AXI_IF_0_BIF_1_ARSIZE_0_2to2, AXI_IF_0_BIF_1_ARSIZE_0_1to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AXI_IF
AXI_IF #( 
        .Bresp_0 ( 4 ),
        .Idle_0  ( 0 ),
        .Idle_1  ( 1 ),
        .Read_0  ( 2 ),
        .Read_1  ( 3 ),
        .Read_2  ( 4 ),
        .Write_0 ( 2 ),
        .Write_1 ( 3 ),
        .Write_2 ( 5 ) )
AXI_IF_0(
        // Inputs
        .CLK             ( MSS_DDR_FIC_SUBSYSTEM_CLK_net_0 ),
        .RESETn          ( INIT_DONE_net_0 ),
        .write_start     ( write_start ),
        .read_start      ( read_start ),
        .AWREADY         ( AXI_IF_0_BIF_1_AWREADY ),
        .WREADY          ( AXI_IF_0_BIF_1_WREADY ),
        .BVALID          ( AXI_IF_0_BIF_1_BVALID ),
        .ARREADY         ( AXI_IF_0_BIF_1_ARREADY ),
        .RLAST           ( AMBA_MASTER_0_RLAST_M0_net_0 ),
        .RVALID          ( AMBA_MASTER_0_RVALID_M0_net_0 ),
        .WLEN            ( WLEN ),
        .RLEN            ( RLEN ),
        .WDATA_int_input ( WDATA_int_input ),
        .AWADDR_int      ( AWADDR_int ),
        .ARADDR_int      ( ARADDR_int ),
        .BID             ( AXI_IF_0_BIF_1_BID ),
        .BRESP           ( AXI_IF_0_BIF_1_BRESP ),
        .RID             ( AXI_IF_0_BIF_1_RID ),
        .RDATA           ( AMBA_MASTER_0_RDATA_M0_net_0 ),
        .RRESP           ( AXI_IF_0_BIF_1_RRESP ),
        // Outputs
        .AXI_WBUSY       ( AXI_WBUSY_net_0 ),
        .AXI_RBUSY       ( AXI_RBUSY_net_0 ),
        .AWVALID         ( AXI_IF_0_BIF_1_AWVALID ),
        .WLAST           ( AXI_IF_0_BIF_1_WLAST ),
        .WVALID          ( AXI_IF_0_BIF_1_WVALID ),
        .BREADY          ( AXI_IF_0_BIF_1_BREADY ),
        .ARVALID         ( AXI_IF_0_BIF_1_ARVALID ),
        .RREADY          ( AXI_IF_0_BIF_1_RREADY ),
        .AWID            ( AXI_IF_0_BIF_1_AWID ),
        .AWADDR          ( AXI_IF_0_BIF_1_AWADDR ),
        .AWLEN           ( AXI_IF_0_BIF_1_AWLEN ),
        .AWSIZE          ( AXI_IF_0_BIF_1_AWSIZE ),
        .AWLOCK          ( AXI_IF_0_BIF_1_AWLOCK ),
        .AWBURST         ( AXI_IF_0_BIF_1_AWBURST ),
        .WID             ( AXI_IF_0_BIF_1_WID ),
        .WSTRB           ( AXI_IF_0_BIF_1_WSTRB ),
        .WDATA           ( AXI_IF_0_BIF_1_WDATA ),
        .ARID            ( AXI_IF_0_BIF_1_ARID ),
        .ARADDR          ( AXI_IF_0_BIF_1_ARADDR ),
        .ARLEN           ( AXI_IF_0_BIF_1_ARLEN ),
        .ARSIZE          ( AXI_IF_0_BIF_1_ARSIZE ),
        .ARLOCK          ( AXI_IF_0_BIF_1_ARLOCK ),
        .ARBURST         ( AXI_IF_0_BIF_1_ARBURST ) 
        );

//--------MDDR_Demo
MDDR_Demo MDDR_Demo_0(
        // Inputs
        .MMUART_1_RXD               ( MMUART_1_RXD ),
        .MDDR_DQS_TMATCH_0_IN       ( MDDR_DQS_TMATCH_0_IN ),
        .DEVRST_N                   ( DEVRST_N ),
        .MDDR_AXI_S_RMW             ( GND_net ),
        .FAB_RESET_N                ( VCC_net ),
        .AMBA_MASTER_0_AWVALID_M0   ( AXI_IF_0_BIF_1_AWVALID ),
        .AMBA_MASTER_0_WLAST_M0     ( AXI_IF_0_BIF_1_WLAST ),
        .AMBA_MASTER_0_WVALID_M0    ( AXI_IF_0_BIF_1_WVALID ),
        .AMBA_MASTER_0_BREADY_M0    ( AXI_IF_0_BIF_1_BREADY ),
        .AMBA_MASTER_0_ARVALID_M0   ( AXI_IF_0_BIF_1_ARVALID ),
        .AMBA_MASTER_0_RREADY_M0    ( AXI_IF_0_BIF_1_RREADY ),
        .AMBA_SLAVE_0_PREADYS0      ( AMBA_SLAVE_0_PREADYS0 ),
        .AMBA_SLAVE_0_PSLVERRS0     ( AMBA_SLAVE_0_PSLVERRS0 ),
        .AMBA_MASTER_0_AWID_M0      ( AXI_IF_0_BIF_1_AWID ),
        .AMBA_MASTER_0_AWADDR_M0    ( AXI_IF_0_BIF_1_AWADDR ),
        .AMBA_MASTER_0_AWLEN_M0     ( AXI_IF_0_BIF_1_AWLEN ),
        .AMBA_MASTER_0_AWSIZE_M0    ( AXI_IF_0_BIF_1_AWSIZE ),
        .AMBA_MASTER_0_AWBURST_M0   ( AXI_IF_0_BIF_1_AWBURST ),
        .AMBA_MASTER_0_AWLOCK_M0    ( AXI_IF_0_BIF_1_AWLOCK ),
        .AMBA_MASTER_0_AWCACHE_M0   ( AMBA_MASTER_0_AWCACHE_M0_const_net_0 ), // tied to 4'h0 from definition
        .AMBA_MASTER_0_AWPROT_M0    ( AMBA_MASTER_0_AWPROT_M0_const_net_0 ), // tied to 3'h0 from definition
        .AMBA_MASTER_0_WID_M0       ( AXI_IF_0_BIF_1_WID ),
        .AMBA_MASTER_0_WDATA_M0     ( AXI_IF_0_BIF_1_WDATA ),
        .AMBA_MASTER_0_WSTRB_M0     ( AXI_IF_0_BIF_1_WSTRB ),
        .AMBA_MASTER_0_ARID_M0      ( AXI_IF_0_BIF_1_ARID ),
        .AMBA_MASTER_0_ARADDR_M0    ( AXI_IF_0_BIF_1_ARADDR ),
        .AMBA_MASTER_0_ARLEN_M0     ( AXI_IF_0_BIF_1_ARLEN ),
        .AMBA_MASTER_0_ARSIZE_M0    ( AXI_IF_0_BIF_1_ARSIZE_0 ),
        .AMBA_MASTER_0_ARBURST_M0   ( AXI_IF_0_BIF_1_ARBURST ),
        .AMBA_MASTER_0_ARLOCK_M0    ( AXI_IF_0_BIF_1_ARLOCK ),
        .AMBA_MASTER_0_ARCACHE_M0   ( AMBA_MASTER_0_ARCACHE_M0_const_net_0 ), // tied to 4'h0 from definition
        .AMBA_MASTER_0_ARPROT_M0    ( AMBA_MASTER_0_ARPROT_M0_const_net_0 ), // tied to 3'h0 from definition
        .AMBA_SLAVE_0_PRDATAS0      ( AMBA_SLAVE_0_PRDATAS0 ),
        // Outputs
        .MMUART_1_TXD               ( MMUART_1_TXD_net_0 ),
        .MDDR_DQS_TMATCH_0_OUT      ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N                 ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK                   ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N                 ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE                   ( MDDR_CKE_net_0 ),
        .MDDR_CS_N                  ( MDDR_CS_N_net_0 ),
        .MDDR_ODT                   ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N                 ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N               ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N                  ( MDDR_WE_N_net_0 ),
        .INIT_DONE                  ( INIT_DONE_net_0 ),
        .DDR_READY                  (  ),
        .FIC_0_CLK                  ( FIC_0_CLK_net_0 ),
        .FIC_0_LOCK                 (  ),
        .MSS_DDR_FIC_SUBSYSTEM_CLK  ( MSS_DDR_FIC_SUBSYSTEM_CLK_net_0 ),
        .MSS_DDR_FIC_SUBSYSTEM_LOCK (  ),
        .POWER_ON_RESET_N           (  ),
        .MSS_READY                  (  ),
        .AMBA_MASTER_0_AWREADY_M0   ( AXI_IF_0_BIF_1_AWREADY ),
        .AMBA_MASTER_0_WREADY_M0    ( AXI_IF_0_BIF_1_WREADY ),
        .AMBA_MASTER_0_BVALID_M0    ( AXI_IF_0_BIF_1_BVALID ),
        .AMBA_MASTER_0_ARREADY_M0   ( AXI_IF_0_BIF_1_ARREADY ),
        .AMBA_MASTER_0_RLAST_M0     ( AMBA_MASTER_0_RLAST_M0_net_0 ),
        .AMBA_MASTER_0_RVALID_M0    ( AMBA_MASTER_0_RVALID_M0_net_0 ),
        .AMBA_SLAVE_0_PSELS0        ( AMBA_SLAVE_0_PSELx ),
        .AMBA_SLAVE_0_PENABLES      ( AMBA_SLAVE_0_PENABLE ),
        .AMBA_SLAVE_0_PWRITES       ( AMBA_SLAVE_0_PWRITE ),
        .MDDR_ADDR                  ( MDDR_ADDR_net_0 ),
        .MDDR_BA                    ( MDDR_BA_net_0 ),
        .AMBA_MASTER_0_BID_M0       ( AXI_IF_0_BIF_1_BID ),
        .AMBA_MASTER_0_BRESP_M0     ( AXI_IF_0_BIF_1_BRESP ),
        .AMBA_MASTER_0_RID_M0       ( AXI_IF_0_BIF_1_RID ),
        .AMBA_MASTER_0_RDATA_M0     ( AMBA_MASTER_0_RDATA_M0_net_0 ),
        .AMBA_MASTER_0_RRESP_M0     ( AXI_IF_0_BIF_1_RRESP ),
        .AMBA_SLAVE_0_PADDRS        ( AMBA_SLAVE_0_PADDR ),
        .AMBA_SLAVE_0_PWDATAS       ( AMBA_SLAVE_0_PWDATA ),
        // Inouts
        .MDDR_DM_RDQS               ( MDDR_DM_RDQS ),
        .MDDR_DQ                    ( MDDR_DQ ),
        .MDDR_DQS                   ( MDDR_DQS ) 
        );


endmodule
