set_family {SmartFusion2}
read_verilog -lib COREAPB3_LIB {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v}
read_verilog -lib COREAPB3_LIB {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
read_verilog -lib COREAPB3_LIB {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_feedthrough.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_interconnect_ntom.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_master_stage.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_m.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_matrix_s.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_arbiter.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_ra_channel.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_16Sto1M.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_rd_channel.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_slave_stage.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_arbiter.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wa_channel.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wd_channel.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wresp_channel.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\COREAXI\3.1.100\rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\work\MDDR_Demo\MDDR_Demo.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\CCC_0\MDDR_Demo_sb_CCC_0_FCCC.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\COREAXI_0\rtl\vlog\core\coreaxi.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\FABOSC_0\MDDR_Demo_sb_FABOSC_0_OSC.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\work\MDDR_Demo_sb\MDDR_Demo_sb.v}
read_verilog {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\component\work\MDDR_Demo_sb_MSS\MDDR_Demo_sb_MSS.v}
set_top_level {MDDR_Demo}
map_netlist
read_sdc {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\constraint\MDDR_Demo_derived_constraints.sdc}
check_constraints {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\constraint\synthesis_sdc_errors.log}
write_fdc {E:\Libero_11p7_capture_tests\new_flow\SF2_MDDR_Demo\designer\MDDR_Demo\synthesis.fdc}
