//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Sep 12 09:21:46 2017
// Version: v11.8 SP1 11.8.1.12
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// MDDR_Demo
module MDDR_Demo(
    // Inputs
    AMBA_MASTER_0_ARADDR_M0,
    AMBA_MASTER_0_ARBURST_M0,
    AMBA_MASTER_0_ARCACHE_M0,
    AMBA_MASTER_0_ARID_M0,
    AMBA_MASTER_0_ARLEN_M0,
    AMBA_MASTER_0_ARLOCK_M0,
    AMBA_MASTER_0_ARPROT_M0,
    AMBA_MASTER_0_ARSIZE_M0,
    AMBA_MASTER_0_ARVALID_M0,
    AMBA_MASTER_0_AWADDR_M0,
    AMBA_MASTER_0_AWBURST_M0,
    AMBA_MASTER_0_AWCACHE_M0,
    AMBA_MASTER_0_AWID_M0,
    AMBA_MASTER_0_AWLEN_M0,
    AMBA_MASTER_0_AWLOCK_M0,
    AMBA_MASTER_0_AWPROT_M0,
    AMBA_MASTER_0_AWSIZE_M0,
    AMBA_MASTER_0_AWVALID_M0,
    AMBA_MASTER_0_BREADY_M0,
    AMBA_MASTER_0_RREADY_M0,
    AMBA_MASTER_0_WDATA_M0,
    AMBA_MASTER_0_WID_M0,
    AMBA_MASTER_0_WLAST_M0,
    AMBA_MASTER_0_WSTRB_M0,
    AMBA_MASTER_0_WVALID_M0,
    AMBA_SLAVE_0_PRDATAS0,
    AMBA_SLAVE_0_PREADYS0,
    AMBA_SLAVE_0_PSLVERRS0,
    DEVRST_N,
    FAB_RESET_N,
    MDDR_AXI_S_RMW,
    MDDR_DQS_TMATCH_0_IN,
    MMUART_1_RXD,
    // Outputs
    AMBA_MASTER_0_ARREADY_M0,
    AMBA_MASTER_0_AWREADY_M0,
    AMBA_MASTER_0_BID_M0,
    AMBA_MASTER_0_BRESP_M0,
    AMBA_MASTER_0_BVALID_M0,
    AMBA_MASTER_0_RDATA_M0,
    AMBA_MASTER_0_RID_M0,
    AMBA_MASTER_0_RLAST_M0,
    AMBA_MASTER_0_RRESP_M0,
    AMBA_MASTER_0_RVALID_M0,
    AMBA_MASTER_0_WREADY_M0,
    AMBA_SLAVE_0_PADDRS,
    AMBA_SLAVE_0_PENABLES,
    AMBA_SLAVE_0_PSELS0,
    AMBA_SLAVE_0_PWDATAS,
    AMBA_SLAVE_0_PWRITES,
    DDR_READY,
    FIC_0_CLK,
    FIC_0_LOCK,
    INIT_DONE,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    MMUART_1_TXD,
    MSS_DDR_FIC_SUBSYSTEM_CLK,
    MSS_DDR_FIC_SUBSYSTEM_LOCK,
    MSS_READY,
    POWER_ON_RESET_N,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  [31:0] AMBA_MASTER_0_ARADDR_M0;
input  [1:0]  AMBA_MASTER_0_ARBURST_M0;
input  [3:0]  AMBA_MASTER_0_ARCACHE_M0;
input  [3:0]  AMBA_MASTER_0_ARID_M0;
input  [3:0]  AMBA_MASTER_0_ARLEN_M0;
input  [1:0]  AMBA_MASTER_0_ARLOCK_M0;
input  [2:0]  AMBA_MASTER_0_ARPROT_M0;
input  [2:0]  AMBA_MASTER_0_ARSIZE_M0;
input         AMBA_MASTER_0_ARVALID_M0;
input  [31:0] AMBA_MASTER_0_AWADDR_M0;
input  [1:0]  AMBA_MASTER_0_AWBURST_M0;
input  [3:0]  AMBA_MASTER_0_AWCACHE_M0;
input  [3:0]  AMBA_MASTER_0_AWID_M0;
input  [3:0]  AMBA_MASTER_0_AWLEN_M0;
input  [1:0]  AMBA_MASTER_0_AWLOCK_M0;
input  [2:0]  AMBA_MASTER_0_AWPROT_M0;
input  [2:0]  AMBA_MASTER_0_AWSIZE_M0;
input         AMBA_MASTER_0_AWVALID_M0;
input         AMBA_MASTER_0_BREADY_M0;
input         AMBA_MASTER_0_RREADY_M0;
input  [63:0] AMBA_MASTER_0_WDATA_M0;
input  [3:0]  AMBA_MASTER_0_WID_M0;
input         AMBA_MASTER_0_WLAST_M0;
input  [7:0]  AMBA_MASTER_0_WSTRB_M0;
input         AMBA_MASTER_0_WVALID_M0;
input  [31:0] AMBA_SLAVE_0_PRDATAS0;
input         AMBA_SLAVE_0_PREADYS0;
input         AMBA_SLAVE_0_PSLVERRS0;
input         DEVRST_N;
input         FAB_RESET_N;
input         MDDR_AXI_S_RMW;
input         MDDR_DQS_TMATCH_0_IN;
input         MMUART_1_RXD;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        AMBA_MASTER_0_ARREADY_M0;
output        AMBA_MASTER_0_AWREADY_M0;
output [3:0]  AMBA_MASTER_0_BID_M0;
output [1:0]  AMBA_MASTER_0_BRESP_M0;
output        AMBA_MASTER_0_BVALID_M0;
output [63:0] AMBA_MASTER_0_RDATA_M0;
output [3:0]  AMBA_MASTER_0_RID_M0;
output        AMBA_MASTER_0_RLAST_M0;
output [1:0]  AMBA_MASTER_0_RRESP_M0;
output        AMBA_MASTER_0_RVALID_M0;
output        AMBA_MASTER_0_WREADY_M0;
output [31:0] AMBA_SLAVE_0_PADDRS;
output        AMBA_SLAVE_0_PENABLES;
output        AMBA_SLAVE_0_PSELS0;
output [31:0] AMBA_SLAVE_0_PWDATAS;
output        AMBA_SLAVE_0_PWRITES;
output        DDR_READY;
output        FIC_0_CLK;
output        FIC_0_LOCK;
output        INIT_DONE;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        MMUART_1_TXD;
output        MSS_DDR_FIC_SUBSYSTEM_CLK;
output        MSS_DDR_FIC_SUBSYSTEM_LOCK;
output        MSS_READY;
output        POWER_ON_RESET_N;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0] AMBA_MASTER_0_ARADDR_M0;
wire   [1:0]  AMBA_MASTER_0_ARBURST_M0;
wire   [3:0]  AMBA_MASTER_0_ARCACHE_M0;
wire   [3:0]  AMBA_MASTER_0_ARID_M0;
wire   [3:0]  AMBA_MASTER_0_ARLEN_M0;
wire   [1:0]  AMBA_MASTER_0_ARLOCK_M0;
wire   [2:0]  AMBA_MASTER_0_ARPROT_M0;
wire          AMBA_MASTER_0_ARREADY;
wire   [2:0]  AMBA_MASTER_0_ARSIZE_M0;
wire          AMBA_MASTER_0_ARVALID_M0;
wire   [31:0] AMBA_MASTER_0_AWADDR_M0;
wire   [1:0]  AMBA_MASTER_0_AWBURST_M0;
wire   [3:0]  AMBA_MASTER_0_AWCACHE_M0;
wire   [3:0]  AMBA_MASTER_0_AWID_M0;
wire   [3:0]  AMBA_MASTER_0_AWLEN_M0;
wire   [1:0]  AMBA_MASTER_0_AWLOCK_M0;
wire   [2:0]  AMBA_MASTER_0_AWPROT_M0;
wire          AMBA_MASTER_0_AWREADY;
wire   [2:0]  AMBA_MASTER_0_AWSIZE_M0;
wire          AMBA_MASTER_0_AWVALID_M0;
wire   [3:0]  AMBA_MASTER_0_BID;
wire          AMBA_MASTER_0_BREADY_M0;
wire   [1:0]  AMBA_MASTER_0_BRESP;
wire          AMBA_MASTER_0_BVALID;
wire   [63:0] AMBA_MASTER_0_RDATA;
wire   [3:0]  AMBA_MASTER_0_RID;
wire          AMBA_MASTER_0_RLAST;
wire          AMBA_MASTER_0_RREADY_M0;
wire   [1:0]  AMBA_MASTER_0_RRESP;
wire          AMBA_MASTER_0_RVALID;
wire   [63:0] AMBA_MASTER_0_WDATA_M0;
wire   [3:0]  AMBA_MASTER_0_WID_M0;
wire          AMBA_MASTER_0_WLAST_M0;
wire          AMBA_MASTER_0_WREADY;
wire   [7:0]  AMBA_MASTER_0_WSTRB_M0;
wire          AMBA_MASTER_0_WVALID_M0;
wire   [31:0] AMBA_SLAVE_0_0_PADDR;
wire          AMBA_SLAVE_0_0_PENABLE;
wire   [31:0] AMBA_SLAVE_0_PRDATAS0;
wire          AMBA_SLAVE_0_PREADYS0;
wire          AMBA_SLAVE_0_0_PSELx;
wire          AMBA_SLAVE_0_PSLVERRS0;
wire   [31:0] AMBA_SLAVE_0_0_PWDATA;
wire          AMBA_SLAVE_0_0_PWRITE;
wire          DDR_READY_net_0;
wire          DEVRST_N;
wire          FAB_RESET_N;
wire          FIC_0_CLK_net_0;
wire          FIC_0_LOCK_net_0;
wire          INIT_DONE_net_0;
wire   [15:0] MDDR_ADDR_net_0;
wire          MDDR_AXI_S_RMW;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          MMUART_1_RXD;
wire          MMUART_1_TXD_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_CLK_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0;
wire          MSS_READY_net_0;
wire          POWER_ON_RESET_N_net_0;
wire          MMUART_1_TXD_net_1;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          INIT_DONE_net_1;
wire          DDR_READY_net_1;
wire          FIC_0_CLK_net_1;
wire          FIC_0_LOCK_net_1;
wire          MSS_DDR_FIC_SUBSYSTEM_CLK_net_1;
wire          MSS_DDR_FIC_SUBSYSTEM_LOCK_net_1;
wire          POWER_ON_RESET_N_net_1;
wire          MSS_READY_net_1;
wire          AMBA_MASTER_0_AWREADY_net_0;
wire          AMBA_MASTER_0_WREADY_net_0;
wire          AMBA_MASTER_0_BVALID_net_0;
wire          AMBA_MASTER_0_ARREADY_net_0;
wire          AMBA_MASTER_0_RLAST_net_0;
wire          AMBA_MASTER_0_RVALID_net_0;
wire          AMBA_SLAVE_0_0_PSELx_net_0;
wire          AMBA_SLAVE_0_0_PENABLE_net_0;
wire          AMBA_SLAVE_0_0_PWRITE_net_0;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
wire   [3:0]  AMBA_MASTER_0_BID_net_0;
wire   [1:0]  AMBA_MASTER_0_BRESP_net_0;
wire   [3:0]  AMBA_MASTER_0_RID_net_0;
wire   [63:0] AMBA_MASTER_0_RDATA_net_0;
wire   [1:0]  AMBA_MASTER_0_RRESP_net_0;
wire   [31:0] AMBA_SLAVE_0_0_PADDR_net_0;
wire   [31:0] AMBA_SLAVE_0_0_PWDATA_net_0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_1_TXD_net_1               = MMUART_1_TXD_net_0;
assign MMUART_1_TXD                     = MMUART_1_TXD_net_1;
assign MDDR_DQS_TMATCH_0_OUT_net_1      = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT            = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1                 = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                       = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1                   = MDDR_CLK_net_0;
assign MDDR_CLK                         = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1                 = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                       = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1                   = MDDR_CKE_net_0;
assign MDDR_CKE                         = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1                  = MDDR_CS_N_net_0;
assign MDDR_CS_N                        = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1                   = MDDR_ODT_net_0;
assign MDDR_ODT                         = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1                 = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                       = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1               = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                     = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1                  = MDDR_WE_N_net_0;
assign MDDR_WE_N                        = MDDR_WE_N_net_1;
assign INIT_DONE_net_1                  = INIT_DONE_net_0;
assign INIT_DONE                        = INIT_DONE_net_1;
assign DDR_READY_net_1                  = DDR_READY_net_0;
assign DDR_READY                        = DDR_READY_net_1;
assign FIC_0_CLK_net_1                  = FIC_0_CLK_net_0;
assign FIC_0_CLK                        = FIC_0_CLK_net_1;
assign FIC_0_LOCK_net_1                 = FIC_0_LOCK_net_0;
assign FIC_0_LOCK                       = FIC_0_LOCK_net_1;
assign MSS_DDR_FIC_SUBSYSTEM_CLK_net_1  = MSS_DDR_FIC_SUBSYSTEM_CLK_net_0;
assign MSS_DDR_FIC_SUBSYSTEM_CLK        = MSS_DDR_FIC_SUBSYSTEM_CLK_net_1;
assign MSS_DDR_FIC_SUBSYSTEM_LOCK_net_1 = MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0;
assign MSS_DDR_FIC_SUBSYSTEM_LOCK       = MSS_DDR_FIC_SUBSYSTEM_LOCK_net_1;
assign POWER_ON_RESET_N_net_1           = POWER_ON_RESET_N_net_0;
assign POWER_ON_RESET_N                 = POWER_ON_RESET_N_net_1;
assign MSS_READY_net_1                  = MSS_READY_net_0;
assign MSS_READY                        = MSS_READY_net_1;
assign AMBA_MASTER_0_AWREADY_net_0      = AMBA_MASTER_0_AWREADY;
assign AMBA_MASTER_0_AWREADY_M0         = AMBA_MASTER_0_AWREADY_net_0;
assign AMBA_MASTER_0_WREADY_net_0       = AMBA_MASTER_0_WREADY;
assign AMBA_MASTER_0_WREADY_M0          = AMBA_MASTER_0_WREADY_net_0;
assign AMBA_MASTER_0_BVALID_net_0       = AMBA_MASTER_0_BVALID;
assign AMBA_MASTER_0_BVALID_M0          = AMBA_MASTER_0_BVALID_net_0;
assign AMBA_MASTER_0_ARREADY_net_0      = AMBA_MASTER_0_ARREADY;
assign AMBA_MASTER_0_ARREADY_M0         = AMBA_MASTER_0_ARREADY_net_0;
assign AMBA_MASTER_0_RLAST_net_0        = AMBA_MASTER_0_RLAST;
assign AMBA_MASTER_0_RLAST_M0           = AMBA_MASTER_0_RLAST_net_0;
assign AMBA_MASTER_0_RVALID_net_0       = AMBA_MASTER_0_RVALID;
assign AMBA_MASTER_0_RVALID_M0          = AMBA_MASTER_0_RVALID_net_0;
assign AMBA_SLAVE_0_0_PSELx_net_0       = AMBA_SLAVE_0_0_PSELx;
assign AMBA_SLAVE_0_PSELS0              = AMBA_SLAVE_0_0_PSELx_net_0;
assign AMBA_SLAVE_0_0_PENABLE_net_0     = AMBA_SLAVE_0_0_PENABLE;
assign AMBA_SLAVE_0_PENABLES            = AMBA_SLAVE_0_0_PENABLE_net_0;
assign AMBA_SLAVE_0_0_PWRITE_net_0      = AMBA_SLAVE_0_0_PWRITE;
assign AMBA_SLAVE_0_PWRITES             = AMBA_SLAVE_0_0_PWRITE_net_0;
assign MDDR_ADDR_net_1                  = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]                  = MDDR_ADDR_net_1;
assign MDDR_BA_net_1                    = MDDR_BA_net_0;
assign MDDR_BA[2:0]                     = MDDR_BA_net_1;
assign AMBA_MASTER_0_BID_net_0          = AMBA_MASTER_0_BID;
assign AMBA_MASTER_0_BID_M0[3:0]        = AMBA_MASTER_0_BID_net_0;
assign AMBA_MASTER_0_BRESP_net_0        = AMBA_MASTER_0_BRESP;
assign AMBA_MASTER_0_BRESP_M0[1:0]      = AMBA_MASTER_0_BRESP_net_0;
assign AMBA_MASTER_0_RID_net_0          = AMBA_MASTER_0_RID;
assign AMBA_MASTER_0_RID_M0[3:0]        = AMBA_MASTER_0_RID_net_0;
assign AMBA_MASTER_0_RDATA_net_0        = AMBA_MASTER_0_RDATA;
assign AMBA_MASTER_0_RDATA_M0[63:0]     = AMBA_MASTER_0_RDATA_net_0;
assign AMBA_MASTER_0_RRESP_net_0        = AMBA_MASTER_0_RRESP;
assign AMBA_MASTER_0_RRESP_M0[1:0]      = AMBA_MASTER_0_RRESP_net_0;
assign AMBA_SLAVE_0_0_PADDR_net_0       = AMBA_SLAVE_0_0_PADDR;
assign AMBA_SLAVE_0_PADDRS[31:0]        = AMBA_SLAVE_0_0_PADDR_net_0;
assign AMBA_SLAVE_0_0_PWDATA_net_0      = AMBA_SLAVE_0_0_PWDATA;
assign AMBA_SLAVE_0_PWDATAS[31:0]       = AMBA_SLAVE_0_0_PWDATA_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------MDDR_Demo_sb
MDDR_Demo_sb MDDR_Demo_sb_0(
        // Inputs
        .MMUART_1_RXD               ( MMUART_1_RXD ),
        .MDDR_DQS_TMATCH_0_IN       ( MDDR_DQS_TMATCH_0_IN ),
        .FAB_RESET_N                ( FAB_RESET_N ),
        .AMBA_MASTER_0_AWVALID_M0   ( AMBA_MASTER_0_AWVALID_M0 ),
        .AMBA_MASTER_0_WLAST_M0     ( AMBA_MASTER_0_WLAST_M0 ),
        .AMBA_MASTER_0_WVALID_M0    ( AMBA_MASTER_0_WVALID_M0 ),
        .AMBA_MASTER_0_BREADY_M0    ( AMBA_MASTER_0_BREADY_M0 ),
        .AMBA_MASTER_0_ARVALID_M0   ( AMBA_MASTER_0_ARVALID_M0 ),
        .AMBA_MASTER_0_RREADY_M0    ( AMBA_MASTER_0_RREADY_M0 ),
        .AMBA_SLAVE_0_PREADYS0      ( AMBA_SLAVE_0_PREADYS0 ),
        .AMBA_SLAVE_0_PSLVERRS0     ( AMBA_SLAVE_0_PSLVERRS0 ),
        .DEVRST_N                   ( DEVRST_N ),
        .MDDR_AXI_S_RMW             ( MDDR_AXI_S_RMW ),
        .AMBA_MASTER_0_AWID_M0      ( AMBA_MASTER_0_AWID_M0 ),
        .AMBA_MASTER_0_AWADDR_M0    ( AMBA_MASTER_0_AWADDR_M0 ),
        .AMBA_MASTER_0_AWLEN_M0     ( AMBA_MASTER_0_AWLEN_M0 ),
        .AMBA_MASTER_0_AWSIZE_M0    ( AMBA_MASTER_0_AWSIZE_M0 ),
        .AMBA_MASTER_0_AWBURST_M0   ( AMBA_MASTER_0_AWBURST_M0 ),
        .AMBA_MASTER_0_AWLOCK_M0    ( AMBA_MASTER_0_AWLOCK_M0 ),
        .AMBA_MASTER_0_AWCACHE_M0   ( AMBA_MASTER_0_AWCACHE_M0 ),
        .AMBA_MASTER_0_AWPROT_M0    ( AMBA_MASTER_0_AWPROT_M0 ),
        .AMBA_MASTER_0_WDATA_M0     ( AMBA_MASTER_0_WDATA_M0 ),
        .AMBA_MASTER_0_WID_M0       ( AMBA_MASTER_0_WID_M0 ),
        .AMBA_MASTER_0_WSTRB_M0     ( AMBA_MASTER_0_WSTRB_M0 ),
        .AMBA_MASTER_0_ARID_M0      ( AMBA_MASTER_0_ARID_M0 ),
        .AMBA_MASTER_0_ARADDR_M0    ( AMBA_MASTER_0_ARADDR_M0 ),
        .AMBA_MASTER_0_ARLEN_M0     ( AMBA_MASTER_0_ARLEN_M0 ),
        .AMBA_MASTER_0_ARSIZE_M0    ( AMBA_MASTER_0_ARSIZE_M0 ),
        .AMBA_MASTER_0_ARBURST_M0   ( AMBA_MASTER_0_ARBURST_M0 ),
        .AMBA_MASTER_0_ARLOCK_M0    ( AMBA_MASTER_0_ARLOCK_M0 ),
        .AMBA_MASTER_0_ARCACHE_M0   ( AMBA_MASTER_0_ARCACHE_M0 ),
        .AMBA_MASTER_0_ARPROT_M0    ( AMBA_MASTER_0_ARPROT_M0 ),
        .AMBA_SLAVE_0_PRDATAS0      ( AMBA_SLAVE_0_PRDATAS0 ),
        // Outputs
        .MMUART_1_TXD               ( MMUART_1_TXD_net_0 ),
        .MDDR_DQS_TMATCH_0_OUT      ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N                 ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK                   ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N                 ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE                   ( MDDR_CKE_net_0 ),
        .MDDR_CS_N                  ( MDDR_CS_N_net_0 ),
        .MDDR_ODT                   ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N                 ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N               ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N                  ( MDDR_WE_N_net_0 ),
        .POWER_ON_RESET_N           ( POWER_ON_RESET_N_net_0 ),
        .INIT_DONE                  ( INIT_DONE_net_0 ),
        .AMBA_MASTER_0_AWREADY_M0   ( AMBA_MASTER_0_AWREADY ),
        .AMBA_MASTER_0_WREADY_M0    ( AMBA_MASTER_0_WREADY ),
        .AMBA_MASTER_0_BVALID_M0    ( AMBA_MASTER_0_BVALID ),
        .AMBA_MASTER_0_ARREADY_M0   ( AMBA_MASTER_0_ARREADY ),
        .AMBA_MASTER_0_RLAST_M0     ( AMBA_MASTER_0_RLAST ),
        .AMBA_MASTER_0_RVALID_M0    ( AMBA_MASTER_0_RVALID ),
        .MSS_DDR_FIC_SUBSYSTEM_CLK  ( MSS_DDR_FIC_SUBSYSTEM_CLK_net_0 ),
        .MSS_DDR_FIC_SUBSYSTEM_LOCK ( MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0 ),
        .AMBA_SLAVE_0_PSELS0        ( AMBA_SLAVE_0_0_PSELx ),
        .AMBA_SLAVE_0_PENABLES      ( AMBA_SLAVE_0_0_PENABLE ),
        .AMBA_SLAVE_0_PWRITES       ( AMBA_SLAVE_0_0_PWRITE ),
        .FIC_0_CLK                  ( FIC_0_CLK_net_0 ),
        .FIC_0_LOCK                 ( FIC_0_LOCK_net_0 ),
        .DDR_READY                  ( DDR_READY_net_0 ),
        .MSS_READY                  ( MSS_READY_net_0 ),
        .MDDR_ADDR                  ( MDDR_ADDR_net_0 ),
        .MDDR_BA                    ( MDDR_BA_net_0 ),
        .AMBA_MASTER_0_BID_M0       ( AMBA_MASTER_0_BID ),
        .AMBA_MASTER_0_BRESP_M0     ( AMBA_MASTER_0_BRESP ),
        .AMBA_MASTER_0_RID_M0       ( AMBA_MASTER_0_RID ),
        .AMBA_MASTER_0_RDATA_M0     ( AMBA_MASTER_0_RDATA ),
        .AMBA_MASTER_0_RRESP_M0     ( AMBA_MASTER_0_RRESP ),
        .AMBA_SLAVE_0_PADDRS        ( AMBA_SLAVE_0_0_PADDR ),
        .AMBA_SLAVE_0_PWDATAS       ( AMBA_SLAVE_0_0_PWDATA ),
        // Inouts
        .MDDR_DM_RDQS               ( MDDR_DM_RDQS ),
        .MDDR_DQ                    ( MDDR_DQ ),
        .MDDR_DQS                   ( MDDR_DQS ) 
        );


endmodule
