#Build: Synplify Pro (R) R-2020.09M-SP1-1, Build 100R, Feb 17 2021 #install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I53165 # Fri Jun 11 22:56:44 2021 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys HDL Compiler, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Verilog Compiler, Version comp202009synp2, Build 147R, Built Mar 17 2021 10:14:42, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\CCC_0\Webserver_TCP_sb_CCC_0_FCCC.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\FABOSC_0\Webserver_TCP_sb_FABOSC_0_OSC.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb_MSS\Webserver_TCP_sb_MSS_syn.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb_MSS\Webserver_TCP_sb_MSS.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v" (library COREAHBLSRAM_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\COREAHBLSRAM_0_0\rtl\vlog\core\lsram_2048to139264x8.v" (library COREAHBLSRAM_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\COREAHBLSRAM_0_0\rtl\vlog\core\usram_128to9216x8.v" (library COREAHBLSRAM_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\COREAHBLSRAM_0_0\rtl\vlog\core\SramCtrlIf.v" (library COREAHBLSRAM_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\COREAHBLSRAM_0_0\rtl\vlog\core\CoreAHBLSRAM.v" (library COREAHBLSRAM_LIB) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\Webserver_TCP_sb\Webserver_TCP_sb.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\top\FCCC_0\top_FCCC_0_FCCC.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\top\FCCC_1\top_FCCC_1_FCCC.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\top\SERDES_IF_0\top_SERDES_IF_0_SERDES_IF_syn.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\top\SERDES_IF_0\top_SERDES_IF_0_SERDES_IF.v" (library work) @I::"C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... Finished optimization stage 1 on CCC (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : top_FCCC_0_FCCC.v(5) | Synthesizing module top_FCCC_0_FCCC in library work. Running optimization stage 1 on top_FCCC_0_FCCC ....... Finished optimization stage 1 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : top_FCCC_1_FCCC.v(5) | Synthesizing module top_FCCC_1_FCCC in library work. Running optimization stage 1 on top_FCCC_1_FCCC ....... Finished optimization stage 1 on top_FCCC_1_FCCC (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF in library work. Running optimization stage 1 on INBUF_DIFF ....... Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 103MB) @N:CG364 : top_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_120_3 in library work. Running optimization stage 1 on SERDESIF_120_3 ....... Finished optimization stage 1 on SERDESIF_120_3 (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 103MB) @N:CG364 : top_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module top_SERDES_IF_0_SERDES_IF in library work. Running optimization stage 1 on top_SERDES_IF_0_SERDES_IF ....... Finished optimization stage 1 on top_SERDES_IF_0_SERDES_IF (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 103MB) @N:CG775 : coreahblite.v(23) | Component CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB @N:CG775 : CoreAHBLSRAM.v(29) | Component Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM not found in library "work" or "__hyper__lib__", but found in library COREAHBLSRAM_LIB @N:CG364 : Webserver_TCP_sb_CCC_0_FCCC.v(5) | Synthesizing module Webserver_TCP_sb_CCC_0_FCCC in library work. Running optimization stage 1 on Webserver_TCP_sb_CCC_0_FCCC ....... Finished optimization stage 1 on Webserver_TCP_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 103MB peak: 104MB) @W:CG168 : coreahblite.v(541) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite.v(541) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite.v(541) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite.v(541) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_matrix4x16.v(2639) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000001 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z1 ....... Finished optimization stage 1 on COREAHBLITE_ADDRDEC_Z1 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Finished optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @W:CG168 : coreahblite_matrix4x16.v(2703) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_masterstage.v(209) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z2 ....... Finished optimization stage 1 on COREAHBLITE_ADDRDEC_Z2 (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 108MB) @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 ....... @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 108MB) @W:CG168 : coreahblite_matrix4x16.v(2767) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG168 : coreahblite_matrix4x16.v(2831) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z3 Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z3 ....... Finished optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z3 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... Finished optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000000001 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s Running optimization stage 1 on COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s ....... Finished optimization stage 1 on COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b010011 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b1 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000000001 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z4 Running optimization stage 1 on CoreAHBLite_Z4 ....... Finished optimization stage 1 on CoreAHBLite_Z4 (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 109MB) @N:CG364 : AHBLSramIf.v(29) | Synthesizing module AHBLSramIf in library COREAHBLSRAM_LIB. Running optimization stage 1 on AHBLSramIf ....... @W:CL169 : AHBLSramIf.v(161) | Pruning unused register HWDATA_d[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(161) | Pruning unused register HTRANS_d[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(161) | Pruning unused register HSEL_d. Make sure that there are no unused intermediate registers. @W:CL169 : AHBLSramIf.v(161) | Pruning unused register HREADYIN_d. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on AHBLSramIf (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : SramCtrlIf.v(29) | Synthesizing module Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf in library COREAHBLSRAM_LIB. SEL_SRAM_TYPE=32'b00000000000000000000000000000000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000001000000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 AHB_DWIDTH=32'b00000000000000000000000000100000 S_IDLE=2'b00 S_WR=2'b01 S_RD=2'b10 Generated name = Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2 @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. Running optimization stage 1 on RAM1K18 ....... Finished optimization stage 1 on RAM1K18 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : lsram_2048to139264x8.v(28) | Synthesizing module Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8 in library COREAHBLSRAM_LIB. DEPTH=32'b00000000000000001000000000000000 AHB_DWIDTH=32'b00000000000000000000000000001000 Generated name = Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s Running optimization stage 1 on Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s ....... @W:CL265 : lsram_2048to139264x8.v(229) | Removing unused bit 15 of ckRdAddr[15:9]. Either assign all bits or reduce the width of the signal. @W:CL265 : lsram_2048to139264x8.v(229) | Removing unused bit 9 of ckRdAddr[15:9]. Either assign all bits or reduce the width of the signal. @W:CL279 : lsram_2048to139264x8.v(229) | Pruning register bits 13 to 10 of ckRdAddr[14:10]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 1 on Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG179 : SramCtrlIf.v(381) | Removing redundant assignment. @W:CG133 : SramCtrlIf.v(95) | Object ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : SramCtrlIf.v(96) | Object u_ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : SramCtrlIf.v(103) | Removing wire u_BUSY_all_0, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(104) | Removing wire u_BUSY_all_1, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(105) | Removing wire u_BUSY_all_2, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(106) | Removing wire u_BUSY_all_3, as there is no assignment to it. @W:CG360 : SramCtrlIf.v(113) | Removing wire u_ahbsram_wdata_upd, as there is no assignment to it. Running optimization stage 1 on Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2 ....... Finished optimization stage 1 on Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2 (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : CoreAHBLSRAM.v(29) | Synthesizing module Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM in library COREAHBLSRAM_LIB. FAMILY=32'b00000000000000000000000000010011 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000001000000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 SEL_SRAM_TYPE=32'b00000000000000000000000000000000 Generated name = Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_32768s_512s_0s Running optimization stage 1 on Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_32768s_512s_0s ....... Finished optimization stage 1 on Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_32768s_512s_0s (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 109MB) @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000001 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z5 Running optimization stage 1 on CoreConfigP_Z5 ....... Finished optimization stage 1 on CoreConfigP_Z5 (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000001 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000001 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z6 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset in library work. Running optimization stage 1 on coreresetp_pcie_hotreset ....... Finished optimization stage 1 on coreresetp_pcie_hotreset (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) Running optimization stage 1 on CoreResetP_Z6 ....... @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreResetP_Z6 (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 1 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... Finished optimization stage 1 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : Webserver_TCP_sb_FABOSC_0_OSC.v(5) | Synthesizing module Webserver_TCP_sb_FABOSC_0_OSC in library work. Running optimization stage 1 on Webserver_TCP_sb_FABOSC_0_OSC ....... @W:CL318 : Webserver_TCP_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Webserver_TCP_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Webserver_TCP_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : Webserver_TCP_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on Webserver_TCP_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... Finished optimization stage 1 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work. Running optimization stage 1 on OUTBUF ....... Finished optimization stage 1 on OUTBUF (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF in library work. Running optimization stage 1 on OUTBUF_DIFF ....... Finished optimization stage 1 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : smartfusion2.v(338) | Synthesizing module BIBUF_DIFF in library work. Running optimization stage 1 on BIBUF_DIFF ....... Finished optimization stage 1 on BIBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... Finished optimization stage 1 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... Finished optimization stage 1 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : Webserver_TCP_sb_MSS_syn.v(5) | Synthesizing module MSS_120 in library work. Running optimization stage 1 on MSS_120 ....... Finished optimization stage 1 on MSS_120 (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : Webserver_TCP_sb_MSS.v(9) | Synthesizing module Webserver_TCP_sb_MSS in library work. Running optimization stage 1 on Webserver_TCP_sb_MSS ....... Finished optimization stage 1 on Webserver_TCP_sb_MSS (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : Webserver_TCP_sb.v(9) | Synthesizing module Webserver_TCP_sb in library work. Running optimization stage 1 on Webserver_TCP_sb ....... Finished optimization stage 1 on Webserver_TCP_sb (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on Webserver_TCP_sb ....... Finished optimization stage 2 on Webserver_TCP_sb (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on Webserver_TCP_sb_MSS ....... Finished optimization stage 2 on Webserver_TCP_sb_MSS (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on MSS_120 ....... Finished optimization stage 2 on MSS_120 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on TRIBUFF ....... Finished optimization stage 2 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on INBUF ....... Finished optimization stage 2 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on BIBUF_DIFF ....... Finished optimization stage 2 on BIBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on OUTBUF_DIFF ....... Finished optimization stage 2 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on OUTBUF ....... Finished optimization stage 2 on OUTBUF (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on SYSRESET ....... Finished optimization stage 2 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on Webserver_TCP_sb_FABOSC_0_OSC ....... @N:CL159 : Webserver_TCP_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. Finished optimization stage 2 on Webserver_TCP_sb_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on RCOSC_25_50MHZ ....... Finished optimization stage 2 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 2 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on coreresetp_pcie_hotreset ....... @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on coreresetp_pcie_hotreset (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on CoreResetP_Z6 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. Finished optimization stage 2 on CoreResetP_Z6 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB) Running optimization stage 2 on CoreConfigP_Z5 ....... @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 Finished optimization stage 2 on CoreConfigP_Z5 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_32768s_512s_0s ....... @W:CL246 : CoreAHBLSRAM.v(68) | Input port bits 31 to 20 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on Webserver_TCP_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_32768s_512s_0s (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s ....... @W:CL247 : lsram_2048to139264x8.v(61) | Input port bit 15 of writeAddr[15:0] is unused @W:CL247 : lsram_2048to139264x8.v(62) | Input port bit 15 of readAddr[15:0] is unused @W:CL246 : lsram_2048to139264x8.v(62) | Input port bits 13 to 0 of readAddr[15:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : lsram_2048to139264x8.v(60) | Input ren is unused. Finished optimization stage 2 on Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on RAM1K18 ....... Finished optimization stage 2 on RAM1K18 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2 ....... @N:CL201 : SramCtrlIf.v(127) | Trying to extract state machine for register sramcurr_state. Extracted state machine for register sramcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : SramCtrlIf.v(72) | Input port bits 19 to 18 of ahbsram_addr[19:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on AHBLSramIf ....... @N:CL201 : AHBLSramIf.v(185) | Trying to extract state machine for register ahbcurr_state. Extracted state machine for register ahbcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL159 : AHBLSramIf.v(97) | Input BUSY is unused. Finished optimization stage 2 on AHBLSramIf (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on CoreAHBLite_Z4 ....... @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused. @N:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused. @N:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused. @N:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused. @N:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused. Finished optimization stage 2 on CoreAHBLite_Z4 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s ....... @N:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused. @N:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused. @N:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused. @N:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused. Finished optimization stage 2 on COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 ....... Finished optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z3 ....... @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Finished optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z3 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 ....... @N:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused. @N:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Finished optimization stage 2 on COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z2 ....... Finished optimization stage 2 on COREAHBLITE_ADDRDEC_Z2 (CPU Time 0h:00m:00s, Memory Used current: 112MB peak: 113MB) Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 ....... @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 1 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 1 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 ....... Finished optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z1 ....... Finished optimization stage 2 on COREAHBLITE_ADDRDEC_Z1 (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on Webserver_TCP_sb_CCC_0_FCCC ....... Finished optimization stage 2 on Webserver_TCP_sb_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on top_SERDES_IF_0_SERDES_IF ....... @W:CL156 : top_SERDES_IF_0_SERDES_IF.v(198) | *Input un1_gnd_net[63:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. Finished optimization stage 2 on top_SERDES_IF_0_SERDES_IF (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on SERDESIF_120_3 ....... Finished optimization stage 2 on SERDESIF_120_3 (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on INBUF_DIFF ....... Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on top_FCCC_1_FCCC ....... Finished optimization stage 2 on top_FCCC_1_FCCC (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on top_FCCC_0_FCCC ....... Finished optimization stage 2 on top_FCCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on CCC ....... Finished optimization stage 2 on CCC (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on BIBUF ....... Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) Running optimization stage 2 on AND2 ....... Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 113MB peak: 114MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 113MB peak: 114MB) Process took 0h:00m:15s realtime, 0h:00m:14s cputime Process completed successfully. # Fri Jun 11 22:57:00 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Jun 11 22:57:00 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:16s realtime, 0h:00m:15s cputime Process completed successfully. # Fri Jun 11 22:57:00 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 107MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Jun 11 22:57:02 2021 ###########################################################] Premap Report # Fri Jun 11 22:57:03 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) Reading constraint file: C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(11) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(12) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(13) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(14) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @W:BN544 : synthesis.fdc(15) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3120) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_5 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3074) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_4 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3028) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_3 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_2 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3350) | Removing user instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1089) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Webserver_TCP_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance Webserver_TCP_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_0(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_2(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2936) | Removing instance slavestage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 (in view: COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_0(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 (in view: COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_1(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 (in view: COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_2(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 (in view: COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_3(verilog)) of type view:ACG4.RAM1K18(PRIM) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=236 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) @W:MT686 : synthesis.fdc(11) | No path from master pin (-source) to source of clock FCCC_0/GL0 @W:MT686 : synthesis.fdc(12) | No path from master pin (-source) to source of clock FCCC_0/GL1 @W:MT686 : synthesis.fdc(13) | No path from master pin (-source) to source of clock FCCC_1/GL0 @W:MT686 : synthesis.fdc(14) | No path from master pin (-source) to source of clock Webserver_TCP_sb_0/CCC_0/GL0 @W:MT686 : synthesis.fdc(15) | No path from master pin (-source) to source of clock Webserver_TCP_sb_0/CCC_0/GL3 Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 46 1 . Webserver_TCP_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 327 1 . Webserver_TCP_sb_0/CCC_0/GL3 125.0 MHz 8.000 generated (from Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 37 0 - Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 40.000 declared default_clkgroup 113 0 - SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_0/GL0 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 1 . FCCC_0/GL1 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 0 - SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 1 . FCCC_1/GL0 125.0 MHz 8.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 1 0 - top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 1 ========================================================================================================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 46 Webserver_TCP_sb_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) Webserver_TCP_sb_0.CORERESETP_0.count_ddr_enable_q1.C - Webserver_TCP_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) Webserver_TCP_sb_0/CCC_0/GL0 327 Webserver_TCP_sb_0.CCC_0.CCC_INST.GL0(CCC) Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.CLK_BASE - Webserver_TCP_sb_0.CCC_0.GL0_INST.I(BUFG) Webserver_TCP_sb_0/CCC_0/GL3 37 Webserver_TCP_sb_0.CCC_0.CCC_INST.GL3(CCC) Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.psel_q1.C - Webserver_TCP_sb_0.CCC_0.GL3_INST.I(BUFG) Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB 113 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.CLK_CONFIG_APB(MSS_120) Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.CLK_MDDR_APB - Webserver_TCP_sb_0.CORECONFIGP_0.un1_FIC_2_APB_M_PCLK.I[0](inv) SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0 SERDES_IF_0.SERDESIF_INST.EPCS_RXCLK[1](SERDESIF_120_3) - - - FCCC_0/GL0 1 FCCC_0.CCC_INST.GL0(CCC) Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.RX_CLKPF - FCCC_0.GL0_INST.I(BUFG) FCCC_0/GL1 1 FCCC_0.CCC_INST.GL1(CCC) Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.TX_CLKPF - FCCC_0.GL1_INST.I(BUFG) SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 0 SERDES_IF_0.SERDESIF_INST.EPCS_TXCLK[1](SERDESIF_120_3) - - - FCCC_1/GL0 1 FCCC_1.CCC_INST.GL0(CCC) Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.GTX_CLKPF - FCCC_1.GL0_INST.I(BUFG) top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 1 SERDES_IF_0.refclk1_inbuf_diff.Y(INBUF_DIFF) SERDES_IF_0.SERDESIF_INST.REFCLK1 - - ============================================================================================================================================================================================================================================================================================================================== @W:MT530 : top_serdes_if_0_serdes_if.v(103) | Found inferred clock top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 184MB) Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine ahbcurr_state[2:0] (in view: COREAHBLSRAM_LIB.AHBLSramIf(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sramcurr_state[2:0] (in view: COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1365) | There are no possible illegal states for state machine sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 98MB peak: 185MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Fri Jun 11 22:57:06 2021 ###########################################################] Map & Optimize Report # Fri Jun 11 22:57:06 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I53165 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : webserver_tcp_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Webserver_TCP_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Webserver_TCP_sb_0.CORERESETP_0.sdif2_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Webserver_TCP_sb_0.CORERESETP_0.sdif2_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : lsram_2048to139264x8.v(229) | Removing sequential instance Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[14] because it is equivalent to instance Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : lsram_2048to139264x8.v(229) | Removing sequential instance Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[14] because it is equivalent to instance Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : lsram_2048to139264x8.v(229) | Removing sequential instance Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[14] because it is equivalent to instance Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. #### START OF SSF LOG MESSAGES #### #### END OF SSF LOG MESSAGES #### Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 174MB peak: 174MB) @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] (in view view:work.Webserver_TCP_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.Webserver_TCP_sb(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[2] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[1] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine ahbcurr_state[2:0] (in view: COREAHBLSRAM_LIB.AHBLSramIf(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[17] (in view: COREAHBLSRAM_LIB.AHBLSramIf(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[18] (in view: COREAHBLSRAM_LIB.AHBLSramIf(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[19] (in view: COREAHBLSRAM_LIB.AHBLSramIf(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine sramcurr_state[2:0] (in view: COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (in view: work.CoreConfigP_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1365) | There are no possible illegal states for state machine sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z6(verilog) instance count_ddr[13:0] @N:MO231 : coreresetp.v(1581) | Found counter in view:work.CoreResetP_Z6(verilog) instance count_sdif3[12:0] @W:BN132 : coreresetp.v(1089) | Removing instance Webserver_TCP_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance Webserver_TCP_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp_pcie_hotreset.v(227) | Found counter in view:work.coreresetp_pcie_hotreset(verilog) instance count[6:0] Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 176MB peak: 176MB) @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. Auto Dissolve of COREAHBLSRAM_0_0.U_SramCtrlIf (inst of view:COREAHBLSRAM_LIB.Webserver_TCP_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2(verilog)) @N:BN362 : ahblsramif.v(161) | Removing sequential instance COREAHBLSRAM_0_0.U_AHBLSramIf.HSIZE_d[2] (in view: work.Webserver_TCP_sb(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 180MB peak: 180MB) Available hyper_sources - for debug and ip models None Found @N:BN362 : coreresetp.v(1089) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.DDR_READY_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.sdif_core_reset_n (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.sdif_core_reset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.hot_reset_n (in view: work.top(verilog)) because it does not drive other instances. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[7] because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[15] because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[14] because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[6] because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_slavearbiter.v(449) | Removing instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[2] because it is equivalent to instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11] (in view: work.top(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 181MB peak: 181MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 181MB peak: 182MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 182MB peak: 182MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 182MB peak: 182MB) @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[6] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.SDIF3_CORE_RESET_N_0 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.reset_n_clk_ltssm (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.pwrite_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.psel_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.reset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_HotReset_q (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_Disabled_q (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_DetectQuiet_q (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.pwrite_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.psel_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_HotReset (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_Disabled (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_DetectQuiet (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_HotReset_entry_p (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_Disabled_entry_p (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_DetectQuiet_entry_p (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.state[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.state[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Webserver_TCP_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[0] (in view: work.top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 182MB peak: 182MB) Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 183MB peak: 183MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:05s -1.31ns 399 / 309 2 0h:00m:05s -1.31ns 396 / 309 3 0h:00m:06s -1.31ns 398 / 309 4 0h:00m:06s -0.81ns 399 / 309 @N:FP130 : | Promoting Net Webserver_TCP_sb_0.FIC_2_APB_M_PRESET_N_arst on CLKINT I_92 @N:FP130 : | Promoting Net Webserver_TCP_sb_0_INIT_APB_S_PCLK on CLKINT I_93 @N:FP130 : | Promoting Net Webserver_TCP_sb_0.MSS_HPMS_READY_int_arst on CLKINT I_94 @N:FP130 : | Promoting Net Webserver_TCP_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_95 @N:FP130 : | Promoting Net Webserver_TCP_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_96 @N:FP130 : | Promoting Net Webserver_TCP_sb_0.CORERESETP_0.sdif3_areset_n_rcosc on CLKINT I_97 @N:FP130 : | Promoting Net Webserver_TCP_sb_0.CORERESETP_0.sm0_areset_n_arst on CLKINT I_98 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 183MB peak: 183MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 183MB peak: 184MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 159 clock pin(s) of sequential element(s) 4 gated/generated clock tree(s) driving 286 clock pin(s) of sequential element(s) 0 instances converted, 286 sequential instances remain driven by gated/generated clocks ============================================================================ Non-Gated/Non-Generated Clocks ============================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0005 SERDES_IF_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF_0.SERDESIF_INST ClockId0006 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_120 112 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST ClockId0007 Webserver_TCP_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 46 Webserver_TCP_sb_0.CORERESETP_0.ddr_settled ========================================================================================================================================================================================= ============================================================================================= Gated/Generated Clocks ============================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 Webserver_TCP_sb_0.CCC_0.CCC_INST CCC 283 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0002 FCCC_0.CCC_INST CCC 1 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0003 FCCC_0.CCC_INST CCC 1 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0004 FCCC_1.CCC_INST CCC 1 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 148MB peak: 184MB) Writing Analyst data base C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 180MB peak: 184MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 182MB peak: 184MB) Finished Writing Netlists (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 182MB peak: 184MB) Start final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 180MB peak: 184MB) @W:MT246 : webserver_tcp_sb_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns @N:MT615 : | Found clock SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns @N:MT615 : | Found clock Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB with period 40.00ns @N:MT615 : | Found clock FCCC_0/GL0 with period 16.00ns @N:MT615 : | Found clock FCCC_0/GL1 with period 16.00ns @N:MT615 : | Found clock FCCC_1/GL0 with period 8.00ns @N:MT615 : | Found clock Webserver_TCP_sb_0/CCC_0/GL0 with period 10.00ns @N:MT615 : | Found clock Webserver_TCP_sb_0/CCC_0/GL3 with period 8.00ns @W:MT420 : | Found inferred clock top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF_0.REFCLK1_OUT. ##### START OF TIMING REPORT #####[ # Timing report written on Fri Jun 11 22:57:16 2021 # Top view: top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\tcl_update\sf2\dg0516\516_v8\DG0516_SF2_Secure_Webserver_TCP_Demo\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.520 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FCCC_0/GL0 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_1/GL0 125.0 MHz NA 8.000 NA NA generated (from SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup Webserver_TCP_sb_0/CCC_0/GL0 100.0 MHz 105.5 MHz 10.000 9.480 0.520 generated (from Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup Webserver_TCP_sb_0/CCC_0/GL3 125.0 MHz NA 8.000 NA NA generated (from Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 20.000 1.989 18.011 declared default_clkgroup Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 114.5 MHz 40.000 8.731 15.829 declared default_clkgroup top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ============================================================================================================================================================================================================================ Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 18.011 | No paths - | No paths - | No paths - Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Webserver_TCP_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB | 40.000 31.269 | No paths - | 20.000 17.792 | 20.000 15.829 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB Webserver_TCP_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Webserver_TCP_sb_0/CCC_0/GL0 Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 10.000 False | No paths - | No paths - | No paths - Webserver_TCP_sb_0/CCC_0/GL0 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB | 10.000 False | No paths - | No paths - | No paths - Webserver_TCP_sb_0/CCC_0/GL0 Webserver_TCP_sb_0/CCC_0/GL0 | 10.000 0.520 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Webserver_TCP_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST Webserver_TCP_sb_0/CCC_0/GL0 MSS_120 F_HM0_ADDR[26] Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] 2.454 0.520 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST Webserver_TCP_sb_0/CCC_0/GL0 MSS_120 F_HM0_ADDR[27] Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] 2.490 0.551 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST Webserver_TCP_sb_0/CCC_0/GL0 MSS_120 F_HM0_TRANS1 Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] 2.512 0.882 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST Webserver_TCP_sb_0/CCC_0/GL0 MSS_120 F_HM0_ADDR[24] Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] 2.472 0.965 Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST Webserver_TCP_sb_0/CCC_0/GL0 MSS_120 F_HM0_ADDR[25] Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] 2.503 1.043 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.masterRegAddrSel Webserver_TCP_sb_0/CCC_0/GL0 SLE Q masterRegAddrSel 0.094 2.280 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[26] Webserver_TCP_sb_0/CCC_0/GL0 SLE Q regHADDR[26] 0.094 3.057 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[27] Webserver_TCP_sb_0/CCC_0/GL0 SLE Q regHADDR[27] 0.094 3.124 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS Webserver_TCP_sb_0/CCC_0/GL0 SLE Q regHTRANS 0.094 3.477 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] Webserver_TCP_sb_0/CCC_0/GL0 SLE Q regHADDR[24] 0.094 3.521 ========================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block0 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block1 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block2 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block3 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block4 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block5 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block6 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block7 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a7[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block8 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a15[0] 9.590 0.520 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block9 Webserver_TCP_sb_0/CCC_0/GL0 RAM1K18 A_WEN[0] wen_a15[0] 9.590 0.520 ======================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.410 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.590 - Propagation time: 9.070 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.520 Number of logic level(s): 6 Starting point: Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[26] Ending point: Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block0 / A_WEN[0] The start point is clocked by Webserver_TCP_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE The end point is clocked by Webserver_TCP_sb_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin A_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST MSS_120 F_HM0_ADDR[26] Out 2.454 2.454 f - Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] Net - - 0.432 - 2 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[26] CFG3 B In - 2.886 f - Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[26] CFG3 Y Out 0.143 3.029 f - M0GATEDHADDR[26] Net - - 0.920 - 10 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_sx[0] CFG2 B In - 3.949 f - Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL_sx[0] CFG2 Y Out 0.143 4.092 f - SADDRSEL_sx[0] Net - - 0.432 - 2 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL[0] CFG4 B In - 4.524 f - Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SADDRSEL[0] CFG4 Y Out 0.129 4.653 r - m0s0AddrSel Net - - 0.849 - 8 Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIT64P[0] CFG3 B In - 5.502 r - Webserver_TCP_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNIT64P[0] CFG3 Y Out 0.143 5.645 r - masterAddrInProg[0] Net - - 1.080 - 27 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_AHBLSramIf.HSIZE_d_RNIMRE82[1] CFG4 B In - 6.726 r - Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_AHBLSramIf.HSIZE_d_RNIMRE82[1] CFG4 Y Out 0.143 6.869 r - ahbsram_size[1] Net - - 0.849 - 8 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.wen_a7_xx_RNI9T1P2[0] CFG4 D In - 7.718 r - Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.wen_a7_xx_RNI9T1P2[0] CFG4 Y Out 0.284 8.002 f - wen_a7[0] Net - - 1.068 - 8 Webserver_TCP_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_0.block0 RAM1K18 A_WEN[0] In - 9.070 f - ================================================================================================================================================================================== Total path delay (propagation time + setup) of 9.480 is 3.849(40.6%) logic and 5.631(59.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[0] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[0] 0.076 18.011 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[0] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[0] 0.076 18.079 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[2] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[2] 0.076 18.227 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[1] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[1] 0.076 18.295 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[3] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[3] 0.076 18.314 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[3] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[3] 0.076 18.314 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[6] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[6] 0.094 18.350 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[2] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[2] 0.094 18.378 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[1] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[1] 0.076 18.382 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[6] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[6] 0.076 18.386 ================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN release_sdif3_core6 19.706 18.011 Webserver_TCP_sb_0.CORERESETP_0.ddr_settled Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE EN ddr_settled6 19.706 18.079 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[13] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[13] 19.778 18.411 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[12] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[12] 19.778 18.425 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[12] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[12] 19.778 18.425 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[11] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[11] 19.778 18.440 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[11] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[11] 19.778 18.440 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[10] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[10] 19.778 18.454 Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[10] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[10] 19.778 18.454 Webserver_TCP_sb_0.CORERESETP_0.count_ddr[9] Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[9] 19.778 18.468 =========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.294 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.706 - Propagation time: 1.696 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 18.011 Number of logic level(s): 2 Starting point: Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[0] / Q Ending point: Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core / EN The start point is clocked by Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.CORERESETP_0.count_sdif3[0] SLE Q Out 0.076 0.076 r - count_sdif3[0] Net - - 0.648 - 3 Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core6_8 CFG4 D In - 0.724 r - Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core6_8 CFG4 Y Out 0.284 1.008 f - release_sdif3_core6_8 Net - - 0.216 - 1 Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core6 CFG4 D In - 1.224 f - Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core6 CFG4 Y Out 0.250 1.474 f - release_sdif3_core6 Net - - 0.221 - 1 Webserver_TCP_sb_0.CORERESETP_0.release_sdif3_core SLE EN In - 1.696 f - ==================================================================================================================== Total path delay (propagation time + setup) of 1.989 is 0.904(45.4%) logic and 1.085(54.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.CORECONFIGP_0.psel Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 15.829 Webserver_TCP_sb_0.CORECONFIGP_0.paddr[13] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q Webserver_TCP_sb_0_SDIF3_INIT_APB_PADDR[13] 0.094 17.792 Webserver_TCP_sb_0.CORECONFIGP_0.paddr[12] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q Webserver_TCP_sb_0_SDIF3_INIT_APB_PADDR[12] 0.094 17.834 Webserver_TCP_sb_0.CORECONFIGP_0.state[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 18.059 Webserver_TCP_sb_0.CORECONFIGP_0.paddr[16] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[16] 0.094 18.413 Webserver_TCP_sb_0.CORECONFIGP_0.SDIF3_PENABLE Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q Webserver_TCP_sb_0_SDIF3_INIT_APB_PENABLE 0.094 18.455 Webserver_TCP_sb_0.CORECONFIGP_0.paddr[15] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q Webserver_TCP_sb_0_SDIF3_INIT_APB_PADDR[15] 0.094 18.495 Webserver_TCP_sb_0.CORECONFIGP_0.MDDR_PENABLE Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q CORECONFIGP_0_MDDR_APBmslave_PENABLE 0.094 18.651 Webserver_TCP_sb_0.CORECONFIGP_0.state[0] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 18.695 Webserver_TCP_sb_0.CORECONFIGP_0.paddr[14] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE Q Webserver_TCP_sb_0_SDIF3_INIT_APB_PADDR[14] 0.076 18.986 =================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ SERDES_IF_0.SERDESIF_INST Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SERDESIF_120_3 APB_PSEL Webserver_TCP_sb_0_SDIF3_INIT_APB_PSELx 18.020 15.829 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 19.778 16.362 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 19.778 16.362 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 19.778 16.491 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 19.778 16.491 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE EN un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 19.706 16.555 Webserver_TCP_sb_0.CORECONFIGP_0.state[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D state_ns[1] 19.778 16.646 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 19.778 16.662 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 19.778 16.662 Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 19.778 16.662 ======================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 1.980 + Clock delay at ending point: 0.000 (ideal) = Required time: 18.020 - Propagation time: 2.191 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 15.829 Number of logic level(s): 1 Starting point: Webserver_TCP_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB [falling] (rise=0.000 fall=20.000 period=40.000) on pin CLK The end point is clocked by Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB [rising] (rise=0.000 fall=20.000 period=40.000) on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------- Webserver_TCP_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 f - psel Net - - 0.708 - 4 Webserver_TCP_sb_0.CORECONFIGP_0.R_SDIF3_PSEL_0_a2_0_a2_1_a2 CFG4 D In - 0.802 f - Webserver_TCP_sb_0.CORECONFIGP_0.R_SDIF3_PSEL_0_a2_0_a2_1_a2 CFG4 Y Out 0.250 1.053 f - Webserver_TCP_sb_0_SDIF3_INIT_APB_PSELx Net - - 1.138 - 35 SERDES_IF_0.SERDESIF_INST SERDESIF_120_3 APB_PSEL In - 2.191 f - ========================================================================================================================================= Total path delay (propagation time + setup) of 4.171 is 2.324(55.7%) logic and 1.847(44.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(18) | Timing constraint (from [get_cells { Webserver_TCP_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Webserver_TCP_sb_0.CORERESETP_0.sm0_areset_n_rcosc Webserver_TCP_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(19) | Timing constraint (from [get_cells { Webserver_TCP_sb_0.CORERESETP_0.MSS_HPMS_READY_int Webserver_TCP_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Webserver_TCP_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(20) | Timing constraint (through [get_nets { Webserver_TCP_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n Webserver_TCP_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(21) | Timing constraint (to [get_cells { Webserver_TCP_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] Webserver_TCP_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 Webserver_TCP_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(23) | Timing constraint (through [get_pins { Webserver_TCP_sb_0.Webserver_TCP_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(24) | Timing constraint (through [get_pins { Webserver_TCP_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT443 : synthesis.fdc(25) | Timing constraint (through [get_nets { Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Webserver_TCP_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Webserver_TCP_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 181MB peak: 184MB) Finished timing report (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 181MB peak: 184MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s150tsfc1152-1 Cell usage: AND2 1 use CCC 3 uses CLKINT 12 uses MSS_120 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_120_3 1 use SYSRESET 1 use CFG1 6 uses CFG2 127 uses CFG3 73 uses CFG4 126 uses Carry cells: ARI1 27 uses - used for arithmetic functions Sequential Cells: SLE 310 uses DSP Blocks: 0 of 240 (0%) I/O ports: 88 I/O primitives: 67 BIBUF 21 uses BIBUF_DIFF 2 uses INBUF 3 uses INBUF_DIFF 1 use OUTBUF 37 uses OUTBUF_DIFF 1 use TRIBUFF 2 uses Global Clock Buffers: 12 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 64 of 236 (27%) Total LUTs: 359 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 2304; LUTs = 2304; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 310 + 0 + 2304 + 0 = 2614; Total number of LUTs after P&R: 359 + 0 + 2304 + 0 = 2663; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 65MB peak: 184MB) Process took 0h:00m:10s realtime, 0h:00m:09s cputime # Fri Jun 11 22:57:16 2021 ###########################################################]