Project Settings Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S150TS Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 159 86 0 - 00m:16s - 11-06-2021 10.57.00 PM (premap) Complete 52 43 0 0m:02s 0m:02s 185MB 11-06-2021 10.57.06 PM (fpga_mapper) Complete 91 27 0 0m:09s 0m:10s 184MB 11-06-2021 10.57.16 PM Multi-srs Generator Complete 11-06-2021 10.57.02 PM Area Summary Carry Cells 27 Sequential Cells 310 DSP Blocks (dsp_used) 0 I/O Cells 67 Global Clock Buffers 12 RAM1K18 (v_ram) 64 LUTs (total_luts) 359 Timing Summary Clock Name Req Freq Est Freq Slack FCCC_0/GL0 62.5 MHz NA NA FCCC_0/GL1 62.5 MHz NA NA FCCC_1/GL0 125.0 MHz NA NA SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA NA SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA NA Webserver_TCP_sb_0/CCC_0/GL0 100.0 MHz 105.5 MHz 0.520 Webserver_TCP_sb_0/CCC_0/GL3 125.0 MHz NA NA Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 18.011 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB 25.0 MHz 114.5 MHz 15.829 top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz NA NA System 100.0 MHz NA NA Optimizations Summary Combined Clock Conversion 3 / 4