Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Fri Jun 11 23:24:56 2021

Design top
Family SmartFusion2
Die M2S150TS
Package 1152 FC
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
FCCC_0/GL0 16.000 62.500 5.682 WORST
FCCC_0/GL1 16.000 62.500 5.392 WORST
FCCC_1/GL0 8.000 125.000
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 8.000 125.000
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 8.000 125.000
Webserver_TCP_sb_0/CCC_0/GL0 10.000 100.000 1.233 WORST
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 8.613 WORST
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB 40.000 25.000 2.727 BEST
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF N/A N/A

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain FCCC_0/GL0

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] 6.410 5.682 6.410 12.092 0.611 WORST
Path 2 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] 6.243 5.807 6.243 12.050 0.653 WORST
Path 3 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[8] 6.317 5.865 6.317 12.182 0.521 WORST
Path 4 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[9] 6.370 5.887 6.370 12.257 0.446 WORST
Path 5 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[1] 6.202 5.899 6.202 12.101 0.602 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0]
data required time 12.092
data arrival time - 6.410
slack 5.682
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[30] cell ADLIB:SERDESIF_120_IP + 0.881 0.881 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_171:A net SERDES_IF_0_EPCS_3_RX_DATA[0] + 5.121 6.002 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_171:IPA cell ADLIB:IP_INTERFACE + 0.194 6.196 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[0] + 0.214 6.410 r
data arrival time 6.410
Data required time calculation
FCCC_0/GL0 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 8.000 r
Clock generation + 2.543 10.543
FCCC_0/GL0_INST:An net FCCC_0/GL0_net + 0.586 11.129 r
FCCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.143 11.272 1 f
FCCC_0/GL0_INST/U0_RGB1:An net FCCC_0/GL0_INST/U0_YWn_GEast + 0.588 11.860 f
FCCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 12.176 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_164:A net FCCC_0/GL0_INST/U0_RGB1_YR + 0.451 12.627 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_164:IPA cell ADLIB:IP_INTERFACE + 0.194 12.821 0 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RX_CLKPF net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/RX_CLKPF_net + 0.202 13.023 r
clock-to-clock uncertainty - 0.320 12.703
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] Library setup time ADLIB:MSS_120_IP - 0.611 12.092
data required time 12.092
Operating Conditions WORST

Clock Domain FCCC_0/GL1

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] to FCCC_0/GL1

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] 6.410 5.392 6.410 11.802 0.924 WORST
Path 2 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] 6.243 5.517 6.243 11.760 0.966 WORST
Path 3 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[8] 6.317 5.522 6.317 11.839 0.887 WORST
Path 4 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[9] 6.370 5.563 6.370 11.933 0.793 WORST
Path 5 SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[1] 6.202 5.610 6.202 11.812 0.914 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
To: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0]
data required time 11.802
data arrival time - 6.410
slack 5.392
Data arrival time calculation
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 0.000 0.000
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] Clock source + 0.000 0.000 r
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[30] cell ADLIB:SERDESIF_120_IP + 0.881 0.881 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_171:A net SERDES_IF_0_EPCS_3_RX_DATA[0] + 5.121 6.002 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_171:IPA cell ADLIB:IP_INTERFACE + 0.194 6.196 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[0] + 0.214 6.410 r
data arrival time 6.410
Data required time calculation
FCCC_0/GL1 Clock Constraint 8.000 8.000
FCCC_0/CCC_INST/INST_CCC_IP:GL1 Clock source + 0.000 8.000 r
Clock generation + 2.571 10.571
FCCC_0/GL1_INST:An net FCCC_0/GL1_net + 0.573 11.144 r
FCCC_0/GL1_INST:YEn cell ADLIB:GBM + 0.143 11.287 1 f
FCCC_0/GL1_INST/U0_RGB1:An net FCCC_0/GL1_INST/U0_YWn_GEast + 0.597 11.884 f
FCCC_0/GL1_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 12.200 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_163:A net FCCC_0/GL1_INST/U0_RGB1_YR + 0.452 12.652 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_163:IPA cell ADLIB:IP_INTERFACE + 0.194 12.846 0 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:TX_CLKPF net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/TX_CLKPF_net + 0.200 13.046 r
clock-to-clock uncertainty - 0.320 12.726
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] Library setup time ADLIB:MSS_120_IP - 0.924 11.802
data required time 11.802
Operating Conditions WORST

Clock Domain FCCC_1/GL0

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET FCCC_1/GL0 to SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]

No Path

Clock Domain Webserver_TCP_sb_0/CCC_0/GL0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/INST_RAM1K18_IP:A_WEN[0] 8.027 1.233 14.706 15.939 0.456 8.767 WORST
Path 2 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block5/INST_RAM1K18_IP:A_WEN[0] 7.842 1.419 14.521 15.940 0.456 8.581 WORST
Path 3 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_0/block4/INST_RAM1K18_IP:A_WEN[0] 7.485 1.765 14.164 15.929 0.456 8.235 WORST
Path 4 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_1/block6/INST_RAM1K18_IP:A_WEN[0] 7.470 1.785 14.149 15.934 0.456 8.215 WORST
Path 5 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_1/block5/INST_RAM1K18_IP:A_WEN[0] 7.394 1.851 14.073 15.924 0.456 8.149 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
To: Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/INST_RAM1K18_IP:A_WEN[0]
data required time 15.939
data arrival time - 14.706
slack 1.233
Data arrival time calculation
Webserver_TCP_sb_0/CCC_0/GL0 0.000 0.000
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.118 4.118
Webserver_TCP_sb_0/CCC_0/GL0_INST:An net Webserver_TCP_sb_0/CCC_0/GL0_net + 0.532 4.650 r
Webserver_TCP_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.143 4.793 10 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.603 5.396 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 5.712 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1 + 0.448 6.160 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB cell ADLIB:IP_INTERFACE + 0.209 6.369 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.310 6.679 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_ADDR[25] cell ADLIB:MSS_120_IP + 0.728 7.407 2 r
Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[25]:B net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] + 1.599 9.006 r
Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/PREGATEDHADDR[25]:Y cell ADLIB:CFG3 + 0.074 9.080 12 r
Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL[0]:A net Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/M0GATEDHADDR[25] + 1.024 10.104 r
Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/SADDRSEL[0]:Y cell ADLIB:CFG4 + 0.326 10.430 8 f
Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIT64P[0]:B net Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/m0s0AddrSel + 0.100 10.530 f
Webserver_TCP_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState_RNIT64P[0]:Y cell ADLIB:CFG3 + 0.087 10.617 27 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_AHBLSramIf/HSIZE_d_RNIMRE82[1]:B net Webserver_TCP_sb_0/masterAddrInProg[0] + 0.113 10.730 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_AHBLSramIf/HSIZE_d_RNIMRE82[1]:Y cell ADLIB:CFG4 + 0.087 10.817 8 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/wen_a7_xx_RNIV36R2[0]:C net Webserver_TCP_sb_0/COREAHBLSRAM_0_0/ahbsram_size[1] + 0.619 11.436 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/wen_a7_xx_RNIV36R2[0]:Y cell ADLIB:CFG4 + 0.164 11.600 8 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/CFG_20:C net Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/wen_a7[0] + 2.824 14.424 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/CFG_20:IPC cell ADLIB:CFG2_IP_BC + 0.208 14.632 1 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/INST_RAM1K18_IP:A_WEN[0] net Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/A_WEN_net[0] + 0.074 14.706 f
data arrival time 14.706
Data required time calculation
Webserver_TCP_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 4.118 14.118
Webserver_TCP_sb_0/CCC_0/GL0_INST:An net Webserver_TCP_sb_0/CCC_0/GL0_net + 0.532 14.650 r
Webserver_TCP_sb_0/CCC_0/GL0_INST:YWn cell ADLIB:GBM + 0.143 14.793 3 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1:An net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_YWn + 0.616 15.409 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 15.725 4 r
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/FF_0:CLK net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.532 16.257 r
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/FF_0:IPCLKn cell ADLIB:SLE_IP_CLK + 0.059 16.316 1 f
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/INST_RAM1K18_IP:A_CLK net Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/A_CLK_net + 0.079 16.395 r
Webserver_TCP_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/block7/INST_RAM1K18_IP:A_WEN[0] Library setup time ADLIB:RAM1K18_IP - 0.456 15.939
data required time 15.939
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE GPIO_6_M2F 10.049 16.728 16.728 WORST
Path 2 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE GPIO_4_M2F 9.976 16.655 16.655 WORST
Path 3 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE GPIO_7_M2F 9.926 16.605 16.605 WORST
Path 4 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE GPIO_5_M2F 9.908 16.587 16.587 WORST
Path 5 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE GPIO_0_M2F 9.728 16.407 16.407 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
To: GPIO_6_M2F
data required time N/C
data arrival time - 16.728
slack N/C
Data arrival time calculation
Webserver_TCP_sb_0/CCC_0/GL0 0.000 0.000
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.118 4.118
Webserver_TCP_sb_0/CCC_0/GL0_INST:An net Webserver_TCP_sb_0/CCC_0/GL0_net + 0.532 4.650 r
Webserver_TCP_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.143 4.793 10 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.603 5.396 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.316 5.712 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1 + 0.448 6.160 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB cell ADLIB:IP_INTERFACE + 0.209 6.369 1 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.310 6.679 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_MGPIO6A_H2F_B cell ADLIB:MSS_120_IP + 1.487 8.166 1 f
GPIO_6_M2F_obuf/U0/U_IOOUTFF:A net GPIO_6_M2F_c + 5.197 13.363 f
GPIO_6_M2F_obuf/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 13.693 1 f
GPIO_6_M2F_obuf/U0/U_IOPAD:D net GPIO_6_M2F_obuf/U0/DOUT + 0.080 13.773 f
GPIO_6_M2F_obuf/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.955 16.728 0 f
GPIO_6_M2F net GPIO_6_M2F + 0.000 16.728 f
data arrival time 16.728
Data required time calculation
Webserver_TCP_sb_0/CCC_0/GL0 N/C N/C
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 4.118 N/C
GPIO_6_M2F N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn 6.302 3.318 12.570 15.888 0.353 6.682 0.027 WORST
Path 2 Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_q1:ALn 6.302 3.318 12.570 15.888 0.353 6.682 0.027 WORST
Path 3 Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_clk_base:ALn 6.302 3.318 12.570 15.888 0.353 6.682 0.027 WORST
Path 4 Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn 6.302 3.330 12.570 15.900 0.353 6.670 0.015 WORST
Path 5 Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK Webserver_TCP_sb_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn 5.875 3.743 12.145 15.888 0.353 6.257 0.029 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
To: Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn
data required time 15.888
data arrival time - 12.570
slack 3.318
Data arrival time calculation
Webserver_TCP_sb_0/CCC_0/GL0 0.000 0.000
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.118 4.118
Webserver_TCP_sb_0/CCC_0/GL0_INST:An net Webserver_TCP_sb_0/CCC_0/GL0_net + 0.532 4.650 r
Webserver_TCP_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.143 4.793 10 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.586 5.379 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YR cell ADLIB:RGB + 0.316 5.695 70 r
Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbr_net_1 + 0.573 6.268 r
Webserver_TCP_sb_0/CORERESETP_0/MSS_HPMS_READY_int:Q cell ADLIB:SLE + 0.087 6.355 129 r
Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n:B net Webserver_TCP_sb_0/MSS_HPMS_READY_int + 2.144 8.499 r
Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n:Y cell ADLIB:CFG2 + 0.074 8.573 1 r
Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n_RNIBFK5:An net Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n + 2.176 10.749 f
Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n_RNIBFK5:YEn cell ADLIB:GBM + 0.357 11.106 2 f
Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n_RNIBFK5/U0_RGB1:An net Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n_RNIBFK5/U0_YWn_GEast + 0.585 11.691 f
Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n_RNIBFK5/U0_RGB1:YR cell ADLIB:RGB + 0.316 12.007 4 r
Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn net Webserver_TCP_sb_0/CORERESETP_0/sdif0_areset_n_RNIBFK5/U0_RGB1_YR + 0.563 12.570 r
data arrival time 12.570
Data required time calculation
Webserver_TCP_sb_0/CCC_0/GL0 Clock Constraint 10.000 10.000
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 4.118 14.118
Webserver_TCP_sb_0/CCC_0/GL0_INST:An net Webserver_TCP_sb_0/CCC_0/GL0_net + 0.532 14.650 r
Webserver_TCP_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.143 14.793 10 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:An net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.582 15.375 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7:YR cell ADLIB:RGB + 0.316 15.691 22 r
Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_q1:CLK net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB7_rgbr_net_1 + 0.550 16.241 r
Webserver_TCP_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn Library recovery time ADLIB:SLE - 0.353 15.888
data required time 15.888
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to Webserver_TCP_sb_0/CCC_0/GL0

No Path

SET Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB to Webserver_TCP_sb_0/CCC_0/GL0

No Path

Clock Domain Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[5]:CLK Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN 2.877 16.763 11.980 28.743 0.308 3.237 WORST
Path 2 Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[10]:CLK Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN 2.755 16.897 11.846 28.743 0.308 3.103 WORST
Path 3 Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[3]:CLK Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN 2.587 17.053 11.690 28.743 0.308 2.947 WORST
Path 4 Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[2]:CLK Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN 2.515 17.137 11.606 28.743 0.308 2.863 WORST
Path 5 Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[11]:CLK Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN 2.472 17.168 11.575 28.743 0.308 2.832 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[5]:CLK
To: Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN
data required time 28.743
data arrival time - 11.980
slack 16.763
Data arrival time calculation
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Webserver_TCP_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.058 2.058 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 2.210 1 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Webserver_TCP_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 5.067 7.277 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.357 7.634 2 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.578 8.212 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 8.528 14 r
Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[5]:CLK net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.575 9.103 r
Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[5]:Q cell ADLIB:SLE + 0.108 9.211 2 f
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core6_1:B net Webserver_TCP_sb_0/CORERESETP_0/count_sdif3_Z[5] + 0.678 9.889 f
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core6_1:Y cell ADLIB:CFG4 + 0.287 10.176 1 f
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core6:C net Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core6_1_Z + 0.303 10.479 f
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core6:Y cell ADLIB:CFG4 + 0.287 10.766 1 f
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN net Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core6_Z + 1.214 11.980 f
data arrival time 11.980
Data required time calculation
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Webserver_TCP_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.058 22.058 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 22.210 1 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Webserver_TCP_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 5.067 27.277 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.357 27.634 2 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.578 28.212 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 28.528 14 r
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:CLK net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.523 29.051 r
Webserver_TCP_sb_0/CORERESETP_0/release_sdif3_core:EN Library setup time ADLIB:SLE - 0.308 28.743
data required time 28.743
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[8]:ALn 5.695 13.937 14.784 28.721 0.353 6.063 0.015 WORST
Path 2 Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[6]:ALn 5.695 13.937 14.784 28.721 0.353 6.063 0.015 WORST
Path 3 Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[4]:ALn 5.695 13.937 14.784 28.721 0.353 6.063 0.015 WORST
Path 4 Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[2]:ALn 5.695 13.937 14.784 28.721 0.353 6.063 0.015 WORST
Path 5 Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[10]:ALn 5.695 13.937 14.784 28.721 0.353 6.063 0.015 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK
To: Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[8]:ALn
data required time 28.721
data arrival time - 14.784
slack 13.937
Data arrival time calculation
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Webserver_TCP_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.058 2.058 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 2.210 1 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Webserver_TCP_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 5.067 7.277 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.357 7.634 2 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.577 8.211 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 8.527 32 r
Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.562 9.089 r
Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 9.176 1 r
Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI7FT3:An net Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_0 + 3.768 12.944 f
Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI7FT3:YEn cell ADLIB:GBM + 0.357 13.301 1 f
Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI7FT3/U0_RGB1:An net Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI7FT3/U0_YWn_GEast + 0.570 13.871 f
Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI7FT3/U0_RGB1:YR cell ADLIB:RGB + 0.316 14.187 14 r
Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[8]:ALn net Webserver_TCP_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI7FT3/U0_RGB1_YR + 0.597 14.784 r
data arrival time 14.784
Data required time calculation
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Webserver_TCP_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.058 22.058 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 22.210 1 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Webserver_TCP_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 5.067 27.277 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.357 27.634 2 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.578 28.212 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 28.528 14 r
Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[8]:CLK net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.546 29.074 r
Webserver_TCP_sb_0/CORERESETP_0/count_sdif3[8]:ALn Library recovery time ADLIB:SLE - 0.353 28.721
data required time 28.721
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Webserver_TCP_sb_0/CCC_0/GL0 to Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable:CLK Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1:D 3.951 8.613 10.209 18.822 0.254 WORST
Path 2 Webserver_TCP_sb_0/CORERESETP_0/count_sdif3_enable:CLK Webserver_TCP_sb_0/CORERESETP_0/count_sdif3_enable_q1:D 3.982 8.669 10.233 18.902 0.174 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable:CLK
To: Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1:D
data required time 18.822
data arrival time - 10.209
slack 8.613
Data arrival time calculation
Webserver_TCP_sb_0/CCC_0/GL0 0.000 0.000
Webserver_TCP_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 4.118 4.118
Webserver_TCP_sb_0/CCC_0/GL0_INST:An net Webserver_TCP_sb_0/CCC_0/GL0_net + 0.532 4.650 r
Webserver_TCP_sb_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.143 4.793 10 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB8:An net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.582 5.375 f
Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB8:YR cell ADLIB:RGB + 0.316 5.691 22 r
Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable:CLK net Webserver_TCP_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB8_rgbr_net_1 + 0.567 6.258 r
Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable:Q cell ADLIB:SLE + 0.087 6.345 1 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST0:A net Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_Z + 0.785 7.130 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST0:Y cell ADLIB:CFG1C_TEST + 0.191 7.321 1 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:A net mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net0 + 0.229 7.550 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:Y cell ADLIB:CFG1C_TEST + 0.191 7.741 1 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST1:A net mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net + 0.287 8.028 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.339 8.367 1 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:A net mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net1 + 0.288 8.655 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.339 8.994 1 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:A net mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net0 + 0.173 9.167 r
mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.339 9.506 1 r
Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1:D net mdr_Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net + 0.703 10.209 r
data arrival time 10.209
Data required time calculation
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 10.000 10.000
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 10.000 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net Webserver_TCP_sb_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 2.058 12.058 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 12.210 1 r
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net Webserver_TCP_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 5.067 17.277 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.357 17.634 2 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.577 18.211 f
Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 18.527 32 r
Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1:CLK net Webserver_TCP_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.549 19.076 r
Webserver_TCP_sb_0/CORERESETP_0/count_ddr_enable_q1:D Library setup time ADLIB:SLE - 0.254 18.822
data required time 18.822
Operating Conditions WORST

Clock Domain Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB Webserver_TCP_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 1.611 2.727 1.611 4.338 0.245 -2.727 BEST
Path 2 Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB Webserver_TCP_sb_0/CORECONFIGP_0/state[0]:D 1.248 3.134 1.248 4.382 0.201 -3.134 BEST
Path 3 Webserver_TCP_sb_0/CORECONFIGP_0/psel:CLK SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL 5.164 12.824 12.138 24.962 1.966 14.352 WORST
Path 4 Webserver_TCP_sb_0/CORECONFIGP_0/SDIF3_PENABLE:CLK SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE 4.689 14.792 11.671 26.463 0.465 10.416 WORST
Path 5 Webserver_TCP_sb_0/CORECONFIGP_0/psel:CLK Webserver_TCP_sb_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:D 2.900 16.514 9.874 26.388 0.254 6.972 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
To: Webserver_TCP_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
data required time 4.338
data arrival time - 1.611
slack 2.727
Data arrival time calculation
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB 0.000 0.000
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE cell ADLIB:MSS_120_IP + 0.215 0.215 3 r
Webserver_TCP_sb_0/CORECONFIGP_0/next_state5:A net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE + 0.710 0.925 r
Webserver_TCP_sb_0/CORECONFIGP_0/next_state5:Y cell ADLIB:CFG2 + 0.098 1.023 2 f
Webserver_TCP_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:C net Webserver_TCP_sb_0/CORECONFIGP_0/next_state5_Z + 0.158 1.181 f
Webserver_TCP_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:Y cell ADLIB:CFG4 + 0.060 1.241 1 f
Webserver_TCP_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN net Webserver_TCP_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0_Z + 0.370 1.611 f
data arrival time 1.611
Data required time calculation
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB Max Delay Constraint 0.000 0.000
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST_RNIL2V5:An net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB + 3.342 3.342 f
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST_RNIL2V5:YEn cell ADLIB:GBM + 0.245 3.587 9 f
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST_RNIL2V5/U0_RGB1_RGB2:An net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST_RNIL2V5/U0_YWn_GEast + 0.413 4.000 f
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST_RNIL2V5/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.218 4.218 42 r
Webserver_TCP_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST_RNIL2V5/U0_RGB1_RGB2_rgbr_net_1 + 0.365 4.583 r
Webserver_TCP_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN Library setup time ADLIB:SLE - 0.245 4.338
data required time 4.338
Operating Conditions BEST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET Webserver_TCP_sb_0/CCC_0/GL0 to Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/CLK_CONFIG_APB

No Path

Clock Domain Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF

SET Register to Register

No Path

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 PHY_MDIO Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF 4.466 4.466 -0.503 3.963 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PHY_MDIO
To: Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF
data required time N/C
data arrival time - 4.466
slack N/C
Data arrival time calculation
PHY_MDIO 0.000 0.000 f
BIBUF_0/U0/U_IOPAD:PAD net PHY_MDIO + 0.000 0.000 f
BIBUF_0/U0/U_IOPAD:Y cell ADLIB:IOPAD_BI + 1.403 1.403 1 f
BIBUF_0/U0/U_IOINFF:A net BIBUF_0/U0/YIN1 + 0.893 2.296 f
BIBUF_0/U0/U_IOINFF:Y cell ADLIB:IOINFF_BYPASS + 0.142 2.438 1 f
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_161:B net BIBUF_0_Y + 1.582 4.020 f
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_161:IPB cell ADLIB:IP_INTERFACE + 0.224 4.244 1 f
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF net Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/MDIF_net + 0.222 4.466 f
data arrival time 4.466
Data required time calculation
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF N/C N/C
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF Clock source + 0.000 N/C r
Webserver_TCP_sb_0/Webserver_TCP_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF Library setup time ADLIB:MSS_120_IP - -0.503 N/C
Operating Conditions WORST

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets