| Project Settings |
|---|
| Project Name | PCIE_HPDMA_top_syn | Implementation Name | synthesis |
| Top Module | PCIE_HPDMA_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
68 |
409 |
0 |
- |
0m:02s |
- |
2/19/2016
2:12:47 PM |
| (premap) | Complete |
106 |
12 |
0 |
0m:01s |
0m:01s |
161MB |
2/19/2016
2:12:51 PM |
| (fpga_mapper) | Complete |
48 |
42 |
0 |
0m:03s |
0m:03s |
158MB |
2/19/2016
2:12:55 PM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 2/19/2016
2:12:49 PM |
| Area Summary |
|---|
| |
| Carry Cells | 44 |
Sequential Cells | 390 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 64 |
| Global Clock Buffers | 7 |
Block Rams (RAM1K18)
(v_ram) | 16 |
| LUTs
(total_luts) | 662 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PCIE_HPDMA_0.CCC_0.GL0_net | 80.0 MHz | 104.1 MHz | 2.898 |
| PCIE_HPDMA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 80.0 MHz | 428.6 MHz | 10.167 |
| PCIE_HPDMA_MSS|FIC_2_APB_M_PCLK_inferred_clock | 80.0 MHz | 107.0 MHz | 1.576 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 1 |
| |
|