@W: MO111 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module PCIE_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module PCIE_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module PCIE_HPDMA_FABOSC_0_OSC) 
@W: MO111 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma\fabosc_0\pcie_hpdma_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module PCIE_HPDMA_FABOSC_0_OSC) 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance PCIE_HPDMA_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":870:4:870:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc_q1,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc_q1
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_q1,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_q1
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif1_areset_n_rcosc,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_rcosc
@W: BN132 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_clk_base,  because it is equivalent to instance PCIE_HPDMA_0.CORERESETP_0.sdif0_areset_n_clk_base
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[6] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[4] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[2] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":229:0:229:5|Register bit CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[0] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[12] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[8] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Register bit arbRegSMCurrentState[4] is always 0, optimizing ...
@W: MO160 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit paddr[16] is always 0, optimizing ...
@W: MT246 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma\ccc_0\pcie_hpdma_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock PCIE_HPDMA_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 12.50ns. Please declare a user-defined clock on object "n:PCIE_HPDMA_0.PCIE_HPDMA_MSS_0.FIC_2_APB_M_PCLK"
@W: MT420 |Found inferred clock PCIE_HPDMA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 12.50ns. Please declare a user-defined clock on object "n:PCIE_HPDMA_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
