@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MT480 :"d:/11.7_upload/adv_mss_hpdma/pcie_hpdma/synthesis/clock.fdc":18:0:18:0|Assigning clock "PCIE_HPDMA_0.CCC_0.GL0_net" to command: create_clock {n:PCIE_HPDMA_0.CCC_0.GL0_net} -period {12.5} -waveform {0 6.25} 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[16] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[17] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[18] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance HADDR_d[19] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_16.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_16.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_1.matrix4x16.slavestage_16.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_1.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: MO225 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|No possible illegal states for state machine sdif0_state[3:0],safe FSM implementation is disabled
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.PCIE_HPDMA(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\work\pcie_hpdma_top\coreahblsram_0\rtl\vlog\core\ahblsramif.v":165:3:165:8|Removing sequential instance COREAHBLSRAM_0.U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance PCIE_HPDMA_0.CORERESETP_0.DDR_READY_int in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_0.matrix4x16.slavestage_1.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: BN362 :"d:\11.7_upload\adv_mss_hpdma\pcie_hpdma\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance PCIE_HPDMA_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.PCIE_HPDMA_top(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net PCIE_HPDMA_0_MSS_READY on CLKINT  I_306 
@N: FP130 |Promoting Net PCIE_HPDMA_0_INIT_APB_S_PRESET_N on CLKINT  I_307 
@N: FP130 |Promoting Net PCIE_HPDMA_0_INIT_APB_S_PCLK on CLKINT  I_308 
@N: FP130 |Promoting Net PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_309 
@N: FP130 |Promoting Net PCIE_HPDMA_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_310 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
