@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":29:7:29:46|Synthesizing module PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":29:7:29:46|Synthesizing module PCIE_HPDMA_top_COREAHBLSRAM_0_SramCtrlIf
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":382:7:382:13|Synthesizing module RAM1K18
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\lsram_2048to139264x8.v":28:7:28:56|Synthesizing module PCIE_HPDMA_top_COREAHBLSRAM_0_lsram_2048to139264x8
@N: CG179 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":394:26:394:38|Removing redundant assignment
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\CoreAHBLSRAM.v":29:7:29:48|Synthesizing module PCIE_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\hdl\Debounce.v":20:8:20:15|Synthesizing module DEBOUNCE
@N: CG179 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\hdl\Debounce.v":81:18:81:26|Removing redundant assignment
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":727:7:727:9|Synthesizing module CCC
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA\CCC_0\PCIE_HPDMA_CCC_0_FCCC.v":5:7:5:27|Synthesizing module PCIE_HPDMA_CCC_0_FCCC
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":20:7:20:32|Synthesizing module COREAHBLITE_DEFAULTSLAVESM
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":20:7:20:30|Synthesizing module COREAHBLITE_SLAVEARBITER
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":22:7:22:28|Synthesizing module COREAHBLITE_SLAVESTAGE
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v":20:7:20:25|Synthesizing module COREAHBLITE_ADDRDEC
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":22:7:22:29|Synthesizing module COREAHBLITE_MASTERSTAGE
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState.
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":23:7:23:28|Synthesizing module COREAHBLITE_MATRIX4X16
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Synthesizing module CoreAHBLite
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA\FABOSC_0\PCIE_HPDMA_FABOSC_0_OSC.v":5:7:5:29|Synthesizing module PCIE_HPDMA_FABOSC_0_OSC
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":274:7:274:12|Synthesizing module OUTBUF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_MSS\PCIE_HPDMA_MSS_syn.v":5:7:5:13|Synthesizing module MSS_075
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_MSS\PCIE_HPDMA_MSS.v":9:7:9:20|Synthesizing module PCIE_HPDMA_MSS
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":718:7:718:14|Synthesizing module SYSRESET
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA\PCIE_HPDMA.v":9:7:9:16|Synthesizing module PCIE_HPDMA
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":320:7:320:16|Synthesizing module INBUF_DIFF
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\SERDES_IF2_0\PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2_syn.v":5:7:5:18|Synthesizing module SERDESIF_075
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\SERDES_IF2_0\PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2.v":5:7:5:44|Synthesizing module PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2
@N: CG364 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\PCIE_HPDMA_top.v":9:7:9:20|Synthesizing module PCIE_HPDMA_top
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Trying to extract state machine for register arbRegSMCurrentState
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\SramCtrlIf.v":133:3:133:8|Trying to extract state machine for register sramcurr_state
@N: CL201 :"D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\component\work\PCIE_HPDMA_top\COREAHBLSRAM_0\rtl\vlog\core\AHBLSramIf.v":189:3:189:8|Trying to extract state machine for register ahbcurr_state
@N|Running in 64-bit mode

