#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\synthesis\run_options.txt
#--  Written on Fri Feb 19 14:12:45 2016


#project files
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/hdl/Debounce.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA/CCC_0/PCIE_HPDMA_CCC_0_FCCC.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA/FABOSC_0/PCIE_HPDMA_FABOSC_0_OSC.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/PCIE_HPDMA_MSS_syn.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/PCIE_HPDMA_MSS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA/PCIE_HPDMA.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2_syn.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2.v"
add_file -verilog -lib COREAHBLSRAM_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/AHBLSramIf.v"
add_file -verilog -lib COREAHBLSRAM_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/lsram_2048to139264x8.v"
add_file -verilog -lib COREAHBLSRAM_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/usram_128to9216x8.v"
add_file -verilog -lib COREAHBLSRAM_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/SramCtrlIf.v"
add_file -verilog -lib COREAHBLSRAM_LIB "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/CoreAHBLSRAM.v"
add_file -verilog "D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/PCIE_HPDMA_top.v"
add_file -fpga_constraint "clock.fdc"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S090TS
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "PCIE_HPDMA_top"

# mapper_options
set_option -frequency 80
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./PCIE_HPDMA_top.edn"
impl -active "synthesis"
