Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)

Date      :  Fri Feb 19 14:09:47 2016
Project   :  D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA
Component :  PCIE_HPDMA_top
Family    :  SmartFusion2


HDL source files for all Synthesis and Simulation tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/AHBLSramIf.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/CoreAHBLSRAM.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/SramCtrlIf.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/lsram_2048to139264x8.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/core/usram_128to9216x8.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/PCIE_HPDMA_top.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2_syn.v

HDL source files for Mentor Precision Synthesis tool:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2_pre.v

Stimulus files for all Simulation tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/SERDESIF_0_PCIE_0_user.bfm
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/SERDESIF_0_PCIE_1_user.bfm
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/SERDESIF_0_compile_bfm.tcl
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/subsystem.bfm

    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/COREAHBLSRAM/2.1.102/coreparameters.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/COREAHBLSRAM/2.1.102/mti/scripts/compileList.do
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/COREAHBLSRAM/2.1.102/mti/scripts/run.do
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/COREAHBLSRAM/2.1.102/mti/scripts/wave.do
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/COREAHBLSRAM_0/rtl/vlog/test/user/tb.v

Firmware files for all Software IDE tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/sys_config_SERDESIF_0.c
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/sys_config_SERDESIF_0.h

Configuration files to be used for all Simulation tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/SERDESIF_0_init.bfm

Configuration files to be used for Power Analysis:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_top/SERDES_IF2_0/SERDESIF_0_init.reg

