//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Fri Feb 19 14:09:45 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// PCIE_HPDMA_top
module PCIE_HPDMA_top(
    // Inputs
    DEVRST_N,
    GPIO_10_F2M,
    GPIO_11_F2M,
    GPIO_8_F2M,
    GPIO_9_F2M,
    MDDR_DQS_TMATCH_0_IN,
    PCIE_0_PERST_N,
    REFCLK0_N_0,
    REFCLK0_P_0,
    RXD0_N_0,
    RXD0_P_0,
    RXD1_N_0,
    RXD1_P_0,
    RXD2_N_0,
    RXD2_P_0,
    RXD3_N_0,
    RXD3_P_0,
    SWITCH,
    // Outputs
    GPIO_0_M2F,
    GPIO_1_M2F,
    GPIO_2_M2F,
    GPIO_3_M2F,
    GPIO_4_M2F,
    GPIO_5_M2F,
    GPIO_6_M2F,
    GPIO_7_M2F,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    TXD0_N_0,
    TXD0_P_0,
    TXD1_N_0,
    TXD1_P_0,
    TXD2_N_0,
    TXD2_P_0,
    TXD3_N_0,
    TXD3_P_0,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input         GPIO_10_F2M;
input         GPIO_11_F2M;
input         GPIO_8_F2M;
input         GPIO_9_F2M;
input         MDDR_DQS_TMATCH_0_IN;
input         PCIE_0_PERST_N;
input         REFCLK0_N_0;
input         REFCLK0_P_0;
input         RXD0_N_0;
input         RXD0_P_0;
input         RXD1_N_0;
input         RXD1_P_0;
input         RXD2_N_0;
input         RXD2_P_0;
input         RXD3_N_0;
input         RXD3_P_0;
input         SWITCH;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        GPIO_0_M2F;
output        GPIO_1_M2F;
output        GPIO_2_M2F;
output        GPIO_3_M2F;
output        GPIO_4_M2F;
output        GPIO_5_M2F;
output        GPIO_6_M2F;
output        GPIO_7_M2F;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        TXD0_N_0;
output        TXD0_P_0;
output        TXD1_N_0;
output        TXD1_P_0;
output        TXD2_N_0;
output        TXD2_P_0;
output        TXD3_N_0;
output        TXD3_P_0;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          DEBOUNCE_0_INTERRUPT;
wire          DEVRST_N;
wire          GPIO_0_M2F_net_0;
wire          GPIO_1_M2F_net_0;
wire          GPIO_2_M2F_net_0;
wire          GPIO_3_M2F_net_0;
wire          GPIO_4_M2F_net_0;
wire          GPIO_5_M2F_net_0;
wire          GPIO_6_M2F_net_0;
wire          GPIO_7_M2F_net_0;
wire          GPIO_8_F2M;
wire          GPIO_9_F2M;
wire          GPIO_10_F2M;
wire          GPIO_11_F2M;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          PCIE_0_PERST_N;
wire   [31:0] PCIE_HPDMA_0_AMBA_SLAVE_0_HADDR;
wire   [2:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HBURST;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_HMASTLOCK;
wire   [3:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HPROT;
wire   [31:0] PCIE_HPDMA_0_AMBA_SLAVE_0_HRDATA;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_HREADY;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_HREADYOUT;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_HSELx;
wire   [1:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HTRANS;
wire   [31:0] PCIE_HPDMA_0_AMBA_SLAVE_0_HWDATA;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_HWRITE;
wire   [31:0] PCIE_HPDMA_0_AMBA_SLAVE_0_1_HADDR;
wire   [2:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_1_HBURST;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_1_HMASTLOCK;
wire   [3:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_1_HPROT;
wire   [31:0] PCIE_HPDMA_0_AMBA_SLAVE_0_1_HRDATA;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_1_HREADY;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_1_HREADYOUT;
wire   [1:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_1_HRESP;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_1_HSELx;
wire   [2:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_1_HSIZE;
wire   [1:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_1_HTRANS;
wire   [31:0] PCIE_HPDMA_0_AMBA_SLAVE_0_1_HWDATA;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_1_HWRITE;
wire          PCIE_HPDMA_0_FIC_0_CLK;
wire          PCIE_HPDMA_0_INIT_APB_S_PCLK;
wire          PCIE_HPDMA_0_INIT_APB_S_PRESET_N;
wire          PCIE_HPDMA_0_MSS_READY;
wire          PCIE_HPDMA_0_SDIF0_0_CORE_RESET_N;
wire          PCIE_HPDMA_0_SDIF0_INIT_APB_PENABLE;
wire   [31:0] PCIE_HPDMA_0_SDIF0_INIT_APB_PRDATA;
wire          PCIE_HPDMA_0_SDIF0_INIT_APB_PREADY;
wire          PCIE_HPDMA_0_SDIF0_INIT_APB_PSELx;
wire          PCIE_HPDMA_0_SDIF0_INIT_APB_PSLVERR;
wire   [31:0] PCIE_HPDMA_0_SDIF0_INIT_APB_PWDATA;
wire          PCIE_HPDMA_0_SDIF0_INIT_APB_PWRITE;
wire          PCIE_HPDMA_0_SDIF0_PHY_RESET_N;
wire          REFCLK0_N_0;
wire          REFCLK0_P_0;
wire          RXD0_N_0;
wire          RXD0_P_0;
wire          RXD1_N_0;
wire          RXD1_P_0;
wire          RXD2_N_0;
wire          RXD2_P_0;
wire          RXD3_N_0;
wire          RXD3_P_0;
wire   [31:0] SERDES_IF2_0_AHB_0_MASTER_HADDR;
wire   [2:0]  SERDES_IF2_0_AHB_0_MASTER_HBURST;
wire   [31:0] SERDES_IF2_0_AHB_0_MASTER_HRDATA;
wire          SERDES_IF2_0_AHB_0_MASTER_HREADY;
wire   [1:0]  SERDES_IF2_0_AHB_0_MASTER_HTRANS;
wire   [31:0] SERDES_IF2_0_AHB_0_MASTER_HWDATA;
wire          SERDES_IF2_0_AHB_0_MASTER_HWRITE;
wire          SERDES_IF2_0_SPLL_LOCK;
wire          SWITCH;
wire          TXD0_N_0_net_0;
wire          TXD0_P_0_net_0;
wire          TXD1_N_0_net_0;
wire          TXD1_P_0_net_0;
wire          TXD2_N_0_net_0;
wire          TXD2_P_0_net_0;
wire          TXD3_N_0_net_0;
wire          TXD3_P_0_net_0;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          GPIO_0_M2F_net_1;
wire          GPIO_1_M2F_net_1;
wire          GPIO_2_M2F_net_1;
wire          GPIO_3_M2F_net_1;
wire          GPIO_4_M2F_net_1;
wire          GPIO_5_M2F_net_1;
wire          GPIO_6_M2F_net_1;
wire          GPIO_7_M2F_net_1;
wire          TXD0_P_0_net_1;
wire          TXD0_N_0_net_1;
wire          TXD1_P_0_net_1;
wire          TXD1_N_0_net_1;
wire          TXD2_P_0_net_1;
wire          TXD2_N_0_net_1;
wire          TXD3_P_0_net_1;
wire          TXD3_N_0_net_1;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
wire   [3:0]  PCIE_0_INTERRUPT_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
wire   [3:1]  PCIE_0_INTERRUPT_const_net_0;
wire   [19:0] EPCS_0_TX_DATA_const_net_0;
wire   [19:0] EPCS_1_TX_DATA_const_net_0;
wire   [19:0] EPCS_2_TX_DATA_const_net_0;
wire   [19:0] EPCS_3_TX_DATA_const_net_0;
wire   [9:0]  SGMII_TX_DATA_const_net_0;
wire          GND_net;
wire   [3:0]  AXI_0_M_BID_const_net_0;
wire   [1:0]  AXI_0_M_BRESP_const_net_0;
wire   [3:0]  AXI_0_M_RID_const_net_0;
wire   [63:0] AXI_0_M_RDATA_const_net_0;
wire   [1:0]  AXI_0_M_RRESP_const_net_0;
wire   [3:0]  AXI_0_S_AWID_const_net_0;
wire   [31:0] AXI_0_S_AWADDR_const_net_0;
wire   [3:0]  AXI_0_S_AWLEN_const_net_0;
wire   [1:0]  AXI_0_S_AWSIZE_const_net_0;
wire   [1:0]  AXI_0_S_AWBURST_const_net_0;
wire   [1:0]  AXI_0_S_AWLOCK_const_net_0;
wire   [3:0]  AXI_0_S_WID_const_net_0;
wire   [7:0]  AXI_0_S_WSTRB_const_net_0;
wire   [63:0] AXI_0_S_WDATA_const_net_0;
wire   [3:0]  AXI_0_S_ARID_const_net_0;
wire   [31:0] AXI_0_S_ARADDR_const_net_0;
wire   [3:0]  AXI_0_S_ARLEN_const_net_0;
wire   [1:0]  AXI_0_S_ARSIZE_const_net_0;
wire   [1:0]  AXI_0_S_ARBURST_const_net_0;
wire   [1:0]  AXI_0_S_ARLOCK_const_net_0;
wire   [3:0]  AXI_1_M_BID_const_net_0;
wire   [1:0]  AXI_1_M_BRESP_const_net_0;
wire   [3:0]  AXI_1_M_RID_const_net_0;
wire   [63:0] AXI_1_M_RDATA_const_net_0;
wire   [1:0]  AXI_1_M_RRESP_const_net_0;
wire   [3:0]  AXI_1_S_AWID_const_net_0;
wire   [31:0] AXI_1_S_AWADDR_const_net_0;
wire   [3:0]  AXI_1_S_AWLEN_const_net_0;
wire   [1:0]  AXI_1_S_AWSIZE_const_net_0;
wire   [1:0]  AXI_1_S_AWBURST_const_net_0;
wire   [1:0]  AXI_1_S_AWLOCK_const_net_0;
wire   [3:0]  AXI_1_S_WID_const_net_0;
wire   [7:0]  AXI_1_S_WSTRB_const_net_0;
wire   [63:0] AXI_1_S_WDATA_const_net_0;
wire   [3:0]  AXI_1_S_ARID_const_net_0;
wire   [31:0] AXI_1_S_ARADDR_const_net_0;
wire   [3:0]  AXI_1_S_ARLEN_const_net_0;
wire   [1:0]  AXI_1_S_ARSIZE_const_net_0;
wire   [1:0]  AXI_1_S_ARBURST_const_net_0;
wire   [1:0]  AXI_1_S_ARLOCK_const_net_0;
wire   [31:0] AHB_1_M_HRDATA_const_net_0;
wire   [31:0] AHB_1_S_HADDR_const_net_0;
wire   [2:0]  AHB_1_S_HBURST_const_net_0;
wire   [1:0]  AHB_1_S_HSIZE_const_net_0;
wire   [1:0]  AHB_1_S_HTRANS_const_net_0;
wire   [31:0] AHB_1_S_HWDATA_const_net_0;
wire   [4:0]  XAUI_MMD_PRTAD_const_net_0;
wire   [4:0]  XAUI_MMD_DEVID_const_net_0;
wire   [63:0] XAUI_TXD_const_net_0;
wire   [7:0]  XAUI_TXC_const_net_0;
wire   [3:0]  PCIE_1_INTERRUPT_const_net_0;
wire   [3:0]  AMBA_MASTER_0_HPROT_M0_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [1:1]  PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0_1to1;
wire   [0:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0_0to0;
wire   [1:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0;
wire          PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP;
wire   [2:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE;
wire   [1:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE_0_1to0;
wire   [1:0]  PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE_0;
wire   [15:2] PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR;
wire   [14:2] PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR_0_14to2;
wire   [14:2] PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR_0;
wire   [1:0]  SERDES_IF2_0_AHB_0_MASTER_HRESP;
wire   [0:0]  SERDES_IF2_0_AHB_0_MASTER_HRESP_0_0to0;
wire          SERDES_IF2_0_AHB_0_MASTER_HRESP_0;
wire   [2:2]  SERDES_IF2_0_AHB_0_MASTER_HSIZE_0_2to2;
wire   [1:0]  SERDES_IF2_0_AHB_0_MASTER_HSIZE_0_1to0;
wire   [2:0]  SERDES_IF2_0_AHB_0_MASTER_HSIZE_0;
wire   [1:0]  SERDES_IF2_0_AHB_0_MASTER_HSIZE;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net                            = 1'b1;
assign PCIE_0_INTERRUPT_const_net_0       = 3'h0;
assign EPCS_0_TX_DATA_const_net_0         = 20'h00000;
assign EPCS_1_TX_DATA_const_net_0         = 20'h00000;
assign EPCS_2_TX_DATA_const_net_0         = 20'h00000;
assign EPCS_3_TX_DATA_const_net_0         = 20'h00000;
assign SGMII_TX_DATA_const_net_0          = 10'h000;
assign GND_net                            = 1'b0;
assign AXI_0_M_BID_const_net_0            = 4'h0;
assign AXI_0_M_BRESP_const_net_0          = 2'h0;
assign AXI_0_M_RID_const_net_0            = 4'h0;
assign AXI_0_M_RDATA_const_net_0          = 64'h0000000000000000;
assign AXI_0_M_RRESP_const_net_0          = 2'h0;
assign AXI_0_S_AWID_const_net_0           = 4'h0;
assign AXI_0_S_AWADDR_const_net_0         = 32'h00000000;
assign AXI_0_S_AWLEN_const_net_0          = 4'h0;
assign AXI_0_S_AWSIZE_const_net_0         = 2'h0;
assign AXI_0_S_AWBURST_const_net_0        = 2'h0;
assign AXI_0_S_AWLOCK_const_net_0         = 2'h0;
assign AXI_0_S_WID_const_net_0            = 4'h0;
assign AXI_0_S_WSTRB_const_net_0          = 8'h00;
assign AXI_0_S_WDATA_const_net_0          = 64'h0000000000000000;
assign AXI_0_S_ARID_const_net_0           = 4'h0;
assign AXI_0_S_ARADDR_const_net_0         = 32'h00000000;
assign AXI_0_S_ARLEN_const_net_0          = 4'h0;
assign AXI_0_S_ARSIZE_const_net_0         = 2'h0;
assign AXI_0_S_ARBURST_const_net_0        = 2'h0;
assign AXI_0_S_ARLOCK_const_net_0         = 2'h0;
assign AXI_1_M_BID_const_net_0            = 4'h0;
assign AXI_1_M_BRESP_const_net_0          = 2'h0;
assign AXI_1_M_RID_const_net_0            = 4'h0;
assign AXI_1_M_RDATA_const_net_0          = 64'h0000000000000000;
assign AXI_1_M_RRESP_const_net_0          = 2'h0;
assign AXI_1_S_AWID_const_net_0           = 4'h0;
assign AXI_1_S_AWADDR_const_net_0         = 32'h00000000;
assign AXI_1_S_AWLEN_const_net_0          = 4'h0;
assign AXI_1_S_AWSIZE_const_net_0         = 2'h0;
assign AXI_1_S_AWBURST_const_net_0        = 2'h0;
assign AXI_1_S_AWLOCK_const_net_0         = 2'h0;
assign AXI_1_S_WID_const_net_0            = 4'h0;
assign AXI_1_S_WSTRB_const_net_0          = 8'h00;
assign AXI_1_S_WDATA_const_net_0          = 64'h0000000000000000;
assign AXI_1_S_ARID_const_net_0           = 4'h0;
assign AXI_1_S_ARADDR_const_net_0         = 32'h00000000;
assign AXI_1_S_ARLEN_const_net_0          = 4'h0;
assign AXI_1_S_ARSIZE_const_net_0         = 2'h0;
assign AXI_1_S_ARBURST_const_net_0        = 2'h0;
assign AXI_1_S_ARLOCK_const_net_0         = 2'h0;
assign AHB_1_M_HRDATA_const_net_0         = 32'h00000000;
assign AHB_1_S_HADDR_const_net_0          = 32'h00000000;
assign AHB_1_S_HBURST_const_net_0         = 3'h0;
assign AHB_1_S_HSIZE_const_net_0          = 2'h0;
assign AHB_1_S_HTRANS_const_net_0         = 2'h0;
assign AHB_1_S_HWDATA_const_net_0         = 32'h00000000;
assign XAUI_MMD_PRTAD_const_net_0         = 5'h00;
assign XAUI_MMD_DEVID_const_net_0         = 5'h00;
assign XAUI_TXD_const_net_0               = 64'h0000000000000000;
assign XAUI_TXC_const_net_0               = 8'h00;
assign PCIE_1_INTERRUPT_const_net_0       = 4'h0;
assign AMBA_MASTER_0_HPROT_M0_const_net_0 = 4'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MDDR_DQS_TMATCH_0_OUT_net_1 = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT       = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1            = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                  = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1              = MDDR_CLK_net_0;
assign MDDR_CLK                    = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1            = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                  = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1              = MDDR_CKE_net_0;
assign MDDR_CKE                    = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1             = MDDR_CS_N_net_0;
assign MDDR_CS_N                   = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1              = MDDR_ODT_net_0;
assign MDDR_ODT                    = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1            = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                  = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1          = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1             = MDDR_WE_N_net_0;
assign MDDR_WE_N                   = MDDR_WE_N_net_1;
assign GPIO_0_M2F_net_1            = GPIO_0_M2F_net_0;
assign GPIO_0_M2F                  = GPIO_0_M2F_net_1;
assign GPIO_1_M2F_net_1            = GPIO_1_M2F_net_0;
assign GPIO_1_M2F                  = GPIO_1_M2F_net_1;
assign GPIO_2_M2F_net_1            = GPIO_2_M2F_net_0;
assign GPIO_2_M2F                  = GPIO_2_M2F_net_1;
assign GPIO_3_M2F_net_1            = GPIO_3_M2F_net_0;
assign GPIO_3_M2F                  = GPIO_3_M2F_net_1;
assign GPIO_4_M2F_net_1            = GPIO_4_M2F_net_0;
assign GPIO_4_M2F                  = GPIO_4_M2F_net_1;
assign GPIO_5_M2F_net_1            = GPIO_5_M2F_net_0;
assign GPIO_5_M2F                  = GPIO_5_M2F_net_1;
assign GPIO_6_M2F_net_1            = GPIO_6_M2F_net_0;
assign GPIO_6_M2F                  = GPIO_6_M2F_net_1;
assign GPIO_7_M2F_net_1            = GPIO_7_M2F_net_0;
assign GPIO_7_M2F                  = GPIO_7_M2F_net_1;
assign TXD0_P_0_net_1              = TXD0_P_0_net_0;
assign TXD0_P_0                    = TXD0_P_0_net_1;
assign TXD0_N_0_net_1              = TXD0_N_0_net_0;
assign TXD0_N_0                    = TXD0_N_0_net_1;
assign TXD1_P_0_net_1              = TXD1_P_0_net_0;
assign TXD1_P_0                    = TXD1_P_0_net_1;
assign TXD1_N_0_net_1              = TXD1_N_0_net_0;
assign TXD1_N_0                    = TXD1_N_0_net_1;
assign TXD2_P_0_net_1              = TXD2_P_0_net_0;
assign TXD2_P_0                    = TXD2_P_0_net_1;
assign TXD2_N_0_net_1              = TXD2_N_0_net_0;
assign TXD2_N_0                    = TXD2_N_0_net_1;
assign TXD3_P_0_net_1              = TXD3_P_0_net_0;
assign TXD3_P_0                    = TXD3_P_0_net_1;
assign TXD3_N_0_net_1              = TXD3_N_0_net_0;
assign TXD3_N_0                    = TXD3_N_0_net_1;
assign MDDR_ADDR_net_1             = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]             = MDDR_ADDR_net_1;
assign MDDR_BA_net_1               = MDDR_BA_net_0;
assign MDDR_BA[2:0]                = MDDR_BA_net_1;
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign PCIE_0_INTERRUPT_net_0 = { 3'h0 , DEBOUNCE_0_INTERRUPT };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0_1to1 = 1'b0;
assign PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0_0to0 = PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP;
assign PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0 = { PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0_1to1, PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0_0to0 };

assign PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE_0_1to0 = PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE[1:0];
assign PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE_0 = { PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE_0_1to0 };

assign PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR_0_14to2 = PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR[14:2];
assign PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR_0 = { PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR_0_14to2 };

assign SERDES_IF2_0_AHB_0_MASTER_HRESP_0_0to0 = SERDES_IF2_0_AHB_0_MASTER_HRESP[0:0];
assign SERDES_IF2_0_AHB_0_MASTER_HRESP_0 = { SERDES_IF2_0_AHB_0_MASTER_HRESP_0_0to0 };

assign SERDES_IF2_0_AHB_0_MASTER_HSIZE_0_2to2 = 1'b0;
assign SERDES_IF2_0_AHB_0_MASTER_HSIZE_0_1to0 = SERDES_IF2_0_AHB_0_MASTER_HSIZE[1:0];
assign SERDES_IF2_0_AHB_0_MASTER_HSIZE_0 = { SERDES_IF2_0_AHB_0_MASTER_HSIZE_0_2to2, SERDES_IF2_0_AHB_0_MASTER_HSIZE_0_1to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------PCIE_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM   -   Actel:DirectCore:COREAHBLSRAM:2.1.102
PCIE_HPDMA_top_COREAHBLSRAM_0_COREAHBLSRAM #( 
        .AHB_AWIDTH                   ( 32 ),
        .AHB_DWIDTH                   ( 32 ),
        .FAMILY                       ( 19 ),
        .LSRAM_NUM_LOCATIONS_DWIDTH32 ( 32768 ),
        .SEL_SRAM_TYPE                ( 0 ),
        .USRAM_NUM_LOCATIONS_DWIDTH32 ( 512 ) )
COREAHBLSRAM_0(
        // Inputs
        .HCLK      ( PCIE_HPDMA_0_FIC_0_CLK ),
        .HRESETN   ( PCIE_HPDMA_0_MSS_READY ),
        .HSEL      ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HSELx ),
        .HREADYIN  ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HREADY ),
        .HWRITE    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HWRITE ),
        .HSIZE     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HSIZE ),
        .HTRANS    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HTRANS ),
        .HBURST    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HBURST ),
        .HADDR     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HADDR ),
        .HWDATA    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HWDATA ),
        // Outputs
        .HREADYOUT ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HREADYOUT ),
        .HRDATA    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HRDATA ),
        .HRESP     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HRESP ) 
        );

//--------DEBOUNCE
DEBOUNCE DEBOUNCE_0(
        // Inputs
        .CLK       ( PCIE_HPDMA_0_FIC_0_CLK ),
        .RESET_N   ( PCIE_HPDMA_0_MSS_READY ),
        .SWITCH    ( SWITCH ),
        // Outputs
        .INTERRUPT ( DEBOUNCE_0_INTERRUPT ) 
        );

//--------PCIE_HPDMA
PCIE_HPDMA PCIE_HPDMA_0(
        // Inputs
        .MDDR_DQS_TMATCH_0_IN        ( MDDR_DQS_TMATCH_0_IN ),
        .FAB_RESET_N                 ( VCC_net ),
        .AMBA_SLAVE_0_HREADYOUT_S0   ( PCIE_HPDMA_0_AMBA_SLAVE_0_HREADYOUT ),
        .AMBA_SLAVE_0_1_HREADYOUT_S1 ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HREADYOUT ),
        .AMBA_MASTER_0_HWRITE_M0     ( SERDES_IF2_0_AHB_0_MASTER_HWRITE ),
        .AMBA_MASTER_0_HMASTLOCK_M0  ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PREADY                ( PCIE_HPDMA_0_SDIF0_INIT_APB_PREADY ),
        .SDIF0_PSLVERR               ( PCIE_HPDMA_0_SDIF0_INIT_APB_PSLVERR ),
        .DEVRST_N                    ( DEVRST_N ),
        .SDIF0_SPLL_LOCK             ( SERDES_IF2_0_SPLL_LOCK ),
        .GPIO_8_F2M                  ( GPIO_8_F2M ),
        .GPIO_9_F2M                  ( GPIO_9_F2M ),
        .GPIO_10_F2M                 ( GPIO_10_F2M ),
        .GPIO_11_F2M                 ( GPIO_11_F2M ),
        .AMBA_SLAVE_0_HRDATA_S0      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HRDATA ),
        .AMBA_SLAVE_0_HRESP_S0       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP_0 ),
        .AMBA_SLAVE_0_1_HRDATA_S1    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HRDATA ),
        .AMBA_SLAVE_0_1_HRESP_S1     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HRESP ),
        .AMBA_MASTER_0_HADDR_M0      ( SERDES_IF2_0_AHB_0_MASTER_HADDR ),
        .AMBA_MASTER_0_HTRANS_M0     ( SERDES_IF2_0_AHB_0_MASTER_HTRANS ),
        .AMBA_MASTER_0_HSIZE_M0      ( SERDES_IF2_0_AHB_0_MASTER_HSIZE_0 ),
        .AMBA_MASTER_0_HBURST_M0     ( SERDES_IF2_0_AHB_0_MASTER_HBURST ),
        .AMBA_MASTER_0_HPROT_M0      ( AMBA_MASTER_0_HPROT_M0_const_net_0 ), // tied to 4'h0 from definition
        .AMBA_MASTER_0_HWDATA_M0     ( SERDES_IF2_0_AHB_0_MASTER_HWDATA ),
        .SDIF0_PRDATA                ( PCIE_HPDMA_0_SDIF0_INIT_APB_PRDATA ),
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT       ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N                  ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK                    ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N                  ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE                    ( MDDR_CKE_net_0 ),
        .MDDR_CS_N                   ( MDDR_CS_N_net_0 ),
        .MDDR_ODT                    ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N                  ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N                ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N                   ( MDDR_WE_N_net_0 ),
        .POWER_ON_RESET_N            (  ),
        .INIT_DONE                   (  ),
        .AMBA_SLAVE_0_HWRITE_S0      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HWRITE ),
        .AMBA_SLAVE_0_HSEL_S0        ( PCIE_HPDMA_0_AMBA_SLAVE_0_HSELx ),
        .AMBA_SLAVE_0_HREADY_S0      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HREADY ),
        .AMBA_SLAVE_0_HMASTLOCK_S0   ( PCIE_HPDMA_0_AMBA_SLAVE_0_HMASTLOCK ),
        .AMBA_SLAVE_0_1_HWRITE_S1    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HWRITE ),
        .AMBA_SLAVE_0_1_HSEL_S1      ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HSELx ),
        .AMBA_SLAVE_0_1_HREADY_S1    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HREADY ),
        .AMBA_SLAVE_0_1_HMASTLOCK_S1 ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HMASTLOCK ),
        .AMBA_MASTER_0_HREADY_M0     ( SERDES_IF2_0_AHB_0_MASTER_HREADY ),
        .FIC_0_CLK                   ( PCIE_HPDMA_0_FIC_0_CLK ),
        .FIC_0_LOCK                  (  ),
        .DDR_READY                   (  ),
        .SDIF_READY                  (  ),
        .SDIF0_PSEL                  ( PCIE_HPDMA_0_SDIF0_INIT_APB_PSELx ),
        .SDIF0_PENABLE               ( PCIE_HPDMA_0_SDIF0_INIT_APB_PENABLE ),
        .SDIF0_PWRITE                ( PCIE_HPDMA_0_SDIF0_INIT_APB_PWRITE ),
        .INIT_APB_S_PCLK             ( PCIE_HPDMA_0_INIT_APB_S_PCLK ),
        .INIT_APB_S_PRESET_N         ( PCIE_HPDMA_0_INIT_APB_S_PRESET_N ),
        .SDIF0_PHY_RESET_N           ( PCIE_HPDMA_0_SDIF0_PHY_RESET_N ),
        .SDIF0_0_CORE_RESET_N        ( PCIE_HPDMA_0_SDIF0_0_CORE_RESET_N ),
        .SDIF0_1_CORE_RESET_N        (  ),
        .FAB_CCC_GL3                 (  ),
        .FAB_CCC_LOCK                (  ),
        .MSS_READY                   ( PCIE_HPDMA_0_MSS_READY ),
        .GPIO_0_M2F                  ( GPIO_0_M2F_net_0 ),
        .GPIO_1_M2F                  ( GPIO_1_M2F_net_0 ),
        .GPIO_2_M2F                  ( GPIO_2_M2F_net_0 ),
        .GPIO_3_M2F                  ( GPIO_3_M2F_net_0 ),
        .GPIO_4_M2F                  ( GPIO_4_M2F_net_0 ),
        .GPIO_5_M2F                  ( GPIO_5_M2F_net_0 ),
        .GPIO_6_M2F                  ( GPIO_6_M2F_net_0 ),
        .GPIO_7_M2F                  ( GPIO_7_M2F_net_0 ),
        .MDDR_ADDR                   ( MDDR_ADDR_net_0 ),
        .MDDR_BA                     ( MDDR_BA_net_0 ),
        .AMBA_SLAVE_0_HADDR_S0       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HADDR ),
        .AMBA_SLAVE_0_HTRANS_S0      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HTRANS ),
        .AMBA_SLAVE_0_HSIZE_S0       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE ),
        .AMBA_SLAVE_0_HWDATA_S0      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HWDATA ),
        .AMBA_SLAVE_0_HBURST_S0      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HBURST ),
        .AMBA_SLAVE_0_HPROT_S0       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HPROT ),
        .AMBA_SLAVE_0_1_HADDR_S1     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HADDR ),
        .AMBA_SLAVE_0_1_HTRANS_S1    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HTRANS ),
        .AMBA_SLAVE_0_1_HSIZE_S1     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HSIZE ),
        .AMBA_SLAVE_0_1_HWDATA_S1    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HWDATA ),
        .AMBA_SLAVE_0_1_HBURST_S1    ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HBURST ),
        .AMBA_SLAVE_0_1_HPROT_S1     ( PCIE_HPDMA_0_AMBA_SLAVE_0_1_HPROT ),
        .AMBA_MASTER_0_HRDATA_M0     ( SERDES_IF2_0_AHB_0_MASTER_HRDATA ),
        .AMBA_MASTER_0_HRESP_M0      ( SERDES_IF2_0_AHB_0_MASTER_HRESP ),
        .SDIF0_PADDR                 ( PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR ),
        .SDIF0_PWDATA                ( PCIE_HPDMA_0_SDIF0_INIT_APB_PWDATA ),
        // Inouts
        .MDDR_DM_RDQS                ( MDDR_DM_RDQS ),
        .MDDR_DQ                     ( MDDR_DQ ),
        .MDDR_DQS                    ( MDDR_DQS ) 
        );

//--------PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2   -   Actel:SgCore:SERDES_IF2:1.2.212
PCIE_HPDMA_top_SERDES_IF2_0_SERDES_IF2 SERDES_IF2_0(
        // Inputs
        .APB_S_PADDR         ( PCIE_HPDMA_0_SDIF0_INIT_APB_PADDR_0 ),
        .APB_S_PENABLE       ( PCIE_HPDMA_0_SDIF0_INIT_APB_PENABLE ),
        .APB_S_PSEL          ( PCIE_HPDMA_0_SDIF0_INIT_APB_PSELx ),
        .APB_S_PWDATA        ( PCIE_HPDMA_0_SDIF0_INIT_APB_PWDATA ),
        .APB_S_PWRITE        ( PCIE_HPDMA_0_SDIF0_INIT_APB_PWRITE ),
        .AHB_0_M_HREADY      ( SERDES_IF2_0_AHB_0_MASTER_HREADY ),
        .AHB_0_M_HRESP       ( SERDES_IF2_0_AHB_0_MASTER_HRESP_0 ),
        .AHB_0_M_HRDATA      ( SERDES_IF2_0_AHB_0_MASTER_HRDATA ),
        .AHB_0_S_HSEL        ( PCIE_HPDMA_0_AMBA_SLAVE_0_HSELx ),
        .AHB_0_S_HADDR       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HADDR ),
        .AHB_0_S_HBURST      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HBURST ),
        .AHB_0_S_HSIZE       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HSIZE_0 ),
        .AHB_0_S_HTRANS      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HTRANS ),
        .AHB_0_S_HWRITE      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HWRITE ),
        .AHB_0_S_HWDATA      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HWDATA ),
        .AHB_0_S_HREADY      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HREADY ),
        .PCIE_0_CORE_RESET_N ( PCIE_HPDMA_0_SDIF0_0_CORE_RESET_N ),
        .PHY_RESET_N         ( PCIE_HPDMA_0_SDIF0_PHY_RESET_N ),
        .APB_S_PRESET_N      ( PCIE_HPDMA_0_INIT_APB_S_PRESET_N ),
        .CLK_BASE            ( PCIE_HPDMA_0_FIC_0_CLK ),
        .APB_S_PCLK          ( PCIE_HPDMA_0_INIT_APB_S_PCLK ),
        .PCIE_0_INTERRUPT    ( PCIE_0_INTERRUPT_net_0 ),
        .PCIE_0_PERST_N      ( PCIE_0_PERST_N ),
        .REFCLK0_P           ( REFCLK0_P_0 ),
        .REFCLK0_N           ( REFCLK0_N_0 ),
        .RXD0_P              ( RXD0_P_0 ),
        .RXD0_N              ( RXD0_N_0 ),
        .RXD1_P              ( RXD1_P_0 ),
        .RXD1_N              ( RXD1_N_0 ),
        .RXD2_P              ( RXD2_P_0 ),
        .RXD2_N              ( RXD2_N_0 ),
        .RXD3_P              ( RXD3_P_0 ),
        .RXD3_N              ( RXD3_N_0 ),
        // Outputs
        .APB_S_PRDATA        ( PCIE_HPDMA_0_SDIF0_INIT_APB_PRDATA ),
        .APB_S_PREADY        ( PCIE_HPDMA_0_SDIF0_INIT_APB_PREADY ),
        .APB_S_PSLVERR       ( PCIE_HPDMA_0_SDIF0_INIT_APB_PSLVERR ),
        .AHB_0_M_HADDR       ( SERDES_IF2_0_AHB_0_MASTER_HADDR ),
        .AHB_0_M_HBURST      ( SERDES_IF2_0_AHB_0_MASTER_HBURST ),
        .AHB_0_M_HSIZE       ( SERDES_IF2_0_AHB_0_MASTER_HSIZE ),
        .AHB_0_M_HTRANS      ( SERDES_IF2_0_AHB_0_MASTER_HTRANS ),
        .AHB_0_M_HWRITE      ( SERDES_IF2_0_AHB_0_MASTER_HWRITE ),
        .AHB_0_M_HWDATA      ( SERDES_IF2_0_AHB_0_MASTER_HWDATA ),
        .AHB_0_S_HREADYOUT   ( PCIE_HPDMA_0_AMBA_SLAVE_0_HREADYOUT ),
        .AHB_0_S_HRESP       ( PCIE_HPDMA_0_AMBA_SLAVE_0_HRESP ),
        .AHB_0_S_HRDATA      ( PCIE_HPDMA_0_AMBA_SLAVE_0_HRDATA ),
        .PCIE_0_SYSTEM_INT   (  ),
        .PLL_LOCK_INT        (  ),
        .PLL_LOCKLOST_INT    (  ),
        .SPLL_LOCK           ( SERDES_IF2_0_SPLL_LOCK ),
        .PCIE_0_LTSSM        (  ),
        .PCIE_0_EV_1US       (  ),
        .REFCLK0_OUT         (  ),
        .PCIE_0_L2P2_ACTIVE  (  ),
        .PCIE_0_RESET_PHASE  (  ),
        .TXD0_P              ( TXD0_P_0_net_0 ),
        .TXD0_N              ( TXD0_N_0_net_0 ),
        .TXD1_P              ( TXD1_P_0_net_0 ),
        .TXD1_N              ( TXD1_N_0_net_0 ),
        .TXD2_P              ( TXD2_P_0_net_0 ),
        .TXD2_N              ( TXD2_N_0_net_0 ),
        .TXD3_P              ( TXD3_P_0_net_0 ),
        .TXD3_N              ( TXD3_N_0_net_0 ) 
        );


endmodule
