Timing Report Max Delay Analysis

SmartTime Version v11.6
Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)
Date: Wed Sep 23 17:58:30 2015


Design: PCIE_HPDMA_top
Family: SmartFusion2
Die: M2S150T
Package: 1152 FC
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                                     
Period (ns):                14.074                                                                          
Frequency (MHz):            71.053                                                                          
Required Period (ns):       13.333                                                                          
Required Frequency (MHz):   75.002                                                                          
External Setup (ns):        3.538                                                                           
External Hold (ns):         -0.526                                                                          
Min Clock-To-Out (ns):      8.734                                                                           
Max Clock-To-Out (ns):      14.625                                                                          

Clock Domain:               PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3                                     
Period (ns):                4.154                                                                           
Frequency (MHz):            240.732                                                                         
Required Period (ns):       8.000                                                                           
Required Frequency (MHz):   125.000                                                                         
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

Clock Domain:               PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                                   
Period (ns):                4.821                                                                           
Frequency (MHz):            207.426                                                                         
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

Clock Domain:               FIC2_CLK                                                                        
Period (ns):                27.587                                                                          
Frequency (MHz):            36.249                                                                          
Required Period (ns):       53.333                                                                          
Required Frequency (MHz):   18.750                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[30]
  Delay (ns):                  12.110                                                                          
  Slack (ns):                  -0.741                                                                          
  Arrival (ns):                17.516                                                                          
  Required (ns):               16.775                                                                          
  Setup (ns):                  2.018                                                                           
  Minimum Period (ns):         14.074                                                                          

Path 2
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[10]
  Delay (ns):                  11.930                                                                          
  Slack (ns):                  -0.686                                                                          
  Arrival (ns):                17.336                                                                          
  Required (ns):               16.650                                                                          
  Setup (ns):                  2.143                                                                           
  Minimum Period (ns):         14.019                                                                          

Path 3
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[9]
  Delay (ns):                  11.864                                                                          
  Slack (ns):                  -0.655                                                                          
  Arrival (ns):                17.270                                                                          
  Required (ns):               16.615                                                                          
  Setup (ns):                  2.178                                                                           
  Minimum Period (ns):         13.988                                                                          

Path 4
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[5]
  Delay (ns):                  11.947                                                                          
  Slack (ns):                  -0.632                                                                          
  Arrival (ns):                17.353                                                                          
  Required (ns):               16.721                                                                          
  Setup (ns):                  2.072                                                                           
  Minimum Period (ns):         13.965                                                                          

Path 5
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[7]
  Delay (ns):                  11.928                                                                          
  Slack (ns):                  -0.582                                                                          
  Arrival (ns):                17.334                                                                          
  Required (ns):               16.752                                                                          
  Setup (ns):                  2.041                                                                           
  Minimum Period (ns):         13.915                                                                          


Expanded Path 1
  From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[30]
  data required time                             16.775    
  data arrival time                          -   17.516    
  slack                                          -0.741    
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  3.334                        
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  3.620                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.763                        PCIE_HPDMA_0/CCC_0/GL0_INST:YWn (f)
               +     0.570          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn
  4.333                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB24:An (f)
               +     0.317          cell: ADLIB:RGB
  4.650                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB24:YL (r)
               +     0.443          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB24_rgbl_net_1
  5.093                        SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_7:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  5.302                        SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_7:IPB (r)
               +     0.104          net: SERDES_IF_0/SERDESIF_INST/CLK_BASE_net
  5.406                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE (r)
               +     0.624          cell: ADLIB:SERDESIF_120_IP
  6.030                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:M_AWADDR_HADDR[28] (f)
               +     8.388          net: SERDES_IF_0_AHB_MASTER_HADDR[28]
  14.418                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/HTRANS_i_o3:C (f)
               +     0.087          cell: ADLIB:CFG4
  14.505                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/HTRANS_i_o3:Y (f)
               +     0.221          net: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/N_202
  14.726                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2[0]:D (f)
               +     0.147          cell: ADLIB:CFG4
  14.873                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2[0]:Y (r)
               +     1.414          net: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/N_152
  16.287                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2_RNI6IGI[0]:C (r)
               +     0.074          cell: ADLIB:CFG4
  16.361                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2_RNI6IGI[0]:Y (r)
               +     0.903          net: PCIE_HPDMA_0/N_128_i_0
  17.264                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_118:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  17.473                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_118:IPB (r)
               +     0.043          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/F_FM0_ADDR_net[30]
  17.516                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[30] (r)
                                    
  17.516                       data arrival time
  ________________________________________________________
  Data required time calculation
  13.333                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  13.333                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  16.667                       
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  16.953                       PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  17.096                       PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.611          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  17.707                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  18.023                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.448          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  18.471                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  18.680                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  18.793                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     2.018          Library setup time: ADLIB:MSS_120_IP
  16.775                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[30]
                                    
  16.775                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        GPIO_10_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10A_F2H_GPIN
  Delay (ns):                  7.091                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.091                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.705                                                                           
  External Setup (ns):         3.538                                                                           

Path 2
  From:                        GPIO_9_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO9A_F2H_GPIN
  Delay (ns):                  7.066                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.066                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.553                                                                           
  External Setup (ns):         3.361                                                                           

Path 3
  From:                        GPIO_8_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO8A_F2H_GPIN
  Delay (ns):                  7.137                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.137                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.459                                                                           
  External Setup (ns):         3.338                                                                           

Path 4
  From:                        GPIO_11_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11A_F2H_GPIN
  Delay (ns):                  7.000                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.000                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.591                                                                           
  External Setup (ns):         3.333                                                                           

Path 5
  From:                        SWITCH
  To:                          DEBOUNCE_0/DFF1:D
  Delay (ns):                  6.333                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                6.333                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.254                                                                           
  External Setup (ns):         1.525                                                                           


Expanded Path 1
  From: GPIO_10_F2M
  To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10A_F2H_GPIN
  data required time                             N/C       
  data arrival time                          -   7.091     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        GPIO_10_F2M (f)
               +     0.000          net: GPIO_10_F2M
  0.000                        GPIO_10_F2M_ibuf/U0/U_IOPAD:PAD (f)
               +     1.841          cell: ADLIB:IOPAD_IN
  1.841                        GPIO_10_F2M_ibuf/U0/U_IOPAD:Y (f)
               +     0.000          net: GPIO_10_F2M_ibuf/U0/YIN1
  1.841                        GPIO_10_F2M_ibuf/U0/U_IOINFF:A (f)
               +     0.090          cell: ADLIB:IOINFF_BYPASS
  1.931                        GPIO_10_F2M_ibuf/U0/U_IOINFF:Y (f)
               +     4.907          net: GPIO_10_F2M_c
  6.838                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_216:A (f)
               +     0.199          cell: ADLIB:IP_INTERFACE
  7.037                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_216:IPA (f)
               +     0.054          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/MGPIO10A_F2H_GPIN_net
  7.091                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10A_F2H_GPIN (f)
                                    
  7.091                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  N/C                          
               +     0.257          net: PCIE_HPDMA_0/CCC_0/GL0_net
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.129          cell: ADLIB:GBM
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.550          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.284          cell: ADLIB:RGB
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.403          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.188          cell: ADLIB:IP_INTERFACE
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     1.705          Library setup time: ADLIB:MSS_120_IP
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10A_F2H_GPIN


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_6_M2F
  Delay (ns):                  9.152                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                14.625                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           14.625                                                                          

Path 2
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_4_M2F
  Delay (ns):                  9.031                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                14.504                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           14.504                                                                          

Path 3
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_5_M2F
  Delay (ns):                  9.026                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                14.499                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           14.499                                                                          

Path 4
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_7_M2F
  Delay (ns):                  9.015                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                14.488                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           14.488                                                                          

Path 5
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_0_M2F
  Delay (ns):                  8.986                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                14.459                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           14.459                                                                          


Expanded Path 1
  From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To: GPIO_6_M2F
  data required time                             N/C       
  data arrival time                          -   14.625    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  3.334                        
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  3.620                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.763                        PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.611          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.374                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  4.690                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.448          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  5.138                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  5.347                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.126          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  5.473                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               +     0.844          cell: ADLIB:MSS_120_IP
  6.317                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_MGPIO6A_H2F_B (f)
               +     5.010          net: GPIO_6_M2F_c
  11.327                       GPIO_6_M2F_obuf/U0/U_IOOUTFF:A (f)
               +     0.343          cell: ADLIB:IOOUTFF_BYPASS
  11.670                       GPIO_6_M2F_obuf/U0/U_IOOUTFF:Y (f)
               +     0.000          net: GPIO_6_M2F_obuf/U0/DOUT
  11.670                       GPIO_6_M2F_obuf/U0/U_IOPAD:D (f)
               +     2.955          cell: ADLIB:IOPAD_TRI
  14.625                       GPIO_6_M2F_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: GPIO_6_M2F
  14.625                       GPIO_6_M2F (f)
                                    
  14.625                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  N/C                          
                                    
  N/C                          GPIO_6_M2F (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:ALn
  Delay (ns):                  4.776                                                                           
  Slack (ns):                  8.137                                                                           
  Arrival (ns):                10.027                                                                          
  Required (ns):               18.164                                                                          
  Recovery (ns):               0.354                                                                           
  Minimum Period (ns):         5.196                                                                           
  Skew (ns):                   0.066                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif1_core_clk_base:ALn
  Delay (ns):                  4.776                                                                           
  Slack (ns):                  8.137                                                                           
  Arrival (ns):                10.027                                                                          
  Required (ns):               18.164                                                                          
  Recovery (ns):               0.354                                                                           
  Minimum Period (ns):         5.196                                                                           
  Skew (ns):                   0.066                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_state[3]:ALn
  Delay (ns):                  4.776                                                                           
  Slack (ns):                  8.137                                                                           
  Arrival (ns):                10.027                                                                          
  Required (ns):               18.164                                                                          
  Recovery (ns):               0.354                                                                           
  Minimum Period (ns):         5.196                                                                           
  Skew (ns):                   0.066                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif0_spll_lock_q2:ALn
  Delay (ns):                  4.776                                                                           
  Slack (ns):                  8.137                                                                           
  Arrival (ns):                10.027                                                                          
  Required (ns):               18.164                                                                          
  Recovery (ns):               0.354                                                                           
  Minimum Period (ns):         5.196                                                                           
  Skew (ns):                   0.066                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core_clk_base:ALn
  Delay (ns):                  4.776                                                                           
  Slack (ns):                  8.137                                                                           
  Arrival (ns):                10.027                                                                          
  Required (ns):               18.164                                                                          
  Recovery (ns):               0.354                                                                           
  Minimum Period (ns):         5.196                                                                           
  Skew (ns):                   0.066                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:ALn
  data required time                             18.164    
  data arrival time                          -   10.027    
  slack                                          8.137     
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  3.334                        
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  3.620                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.763                        PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.587          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.350                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An (f)
               +     0.317          cell: ADLIB:RGB
  4.667                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YL (r)
               +     0.584          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbl_net_1
  5.251                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:CLK (r)
               +     0.092          cell: ADLIB:SLE
  5.343                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:Q (r)
               +     2.837          net: PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base_0
  8.180                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base_RNIJBRA:An (f)
               +     0.357          cell: ADLIB:GBM
  8.537                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base_RNIJBRA:YEn (f)
               +     0.571          net: PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base_RNIJBRA/U0_YWn_GEast
  9.108                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base_RNIJBRA/U0_RGB1:An (f)
               +     0.317          cell: ADLIB:RGB
  9.425                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base_RNIJBRA/U0_RGB1:YL (r)
               +     0.602          net: PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base
  10.027                       PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:ALn (r)
                                    
  10.027                       data arrival time
  ________________________________________________________
  Data required time calculation
  13.333                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  13.333                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  16.667                       
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  16.953                       PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  17.096                       PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.587          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  17.683                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An (f)
               +     0.317          cell: ADLIB:RGB
  18.000                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YL (r)
               +     0.518          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbl_net_1
  18.518                       PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK (r)
               -     0.354          Library recovery time: ADLIB:SLE
  18.164                       PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:ALn
                                    
  18.164                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:ALn
  Delay (ns):                  5.030                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.030                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      0.329                                                                           

Path 2
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_re:ALn
  Delay (ns):                  5.030                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.030                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      0.329                                                                           

Path 3
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q3:ALn
  Delay (ns):                  5.030                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.030                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      0.318                                                                           

Path 4
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:ALn
  Delay (ns):                  5.030                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.030                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      0.317                                                                           


Expanded Path 1
  From: SDIF0_PERST_N
  To: PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:ALn
  data required time                             N/C       
  data arrival time                          -   5.030     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        SDIF0_PERST_N (r)
               +     0.000          net: SDIF0_PERST_N
  0.000                        SDIF0_PERST_N_ibuf/U0/U_IOPAD:PAD (r)
               +     2.430          cell: ADLIB:IOPAD_IN
  2.430                        SDIF0_PERST_N_ibuf/U0/U_IOPAD:Y (r)
               +     0.000          net: SDIF0_PERST_N_ibuf/U0/YIN1
  2.430                        SDIF0_PERST_N_ibuf/U0/U_IOINFF:A (r)
               +     0.083          cell: ADLIB:IOINFF_BYPASS
  2.513                        SDIF0_PERST_N_ibuf/U0/U_IOINFF:Y (r)
               +     2.517          net: SDIF0_PERST_N_c
  5.030                        PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:ALn (r)
                                    
  5.030                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  N/C                          
               +     0.257          net: PCIE_HPDMA_0/CCC_0/GL0_net
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.129          cell: ADLIB:GBM
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.539          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB8:An (f)
               +     0.285          cell: ADLIB:RGB
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB8:YL (r)
               +     0.510          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB8_rgbl_net_1
  N/C                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  N/C                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:ALn


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path 

END SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET FIC2_CLK to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N
  Delay (ns):                  3.052                                                                           
  Slack (ns):                  8.265                                                                           
  Arrival (ns):                9.777                                                                           
  Required (ns):               18.042                                                                          
  Setup (ns):                                                                                                  

Path 2
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:D
  Delay (ns):                  2.048                                                                           
  Slack (ns):                  9.481                                                                           
  Arrival (ns):                8.783                                                                           
  Required (ns):               18.264                                                                          
  Setup (ns):                  0.254                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D
  Delay (ns):                  2.025                                                                           
  Slack (ns):                  9.538                                                                           
  Arrival (ns):                8.723                                                                           
  Required (ns):               18.261                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK
  To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N
  data required time                             18.042    
  data arrival time                          -   9.777     
  slack                                          8.265     
  ________________________________________________________
  Data arrival time calculation
  0.000                        FIC2_CLK
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.912          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK
  4.912                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An (f)
               +     0.357          cell: ADLIB:GBM
  5.269                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn (f)
               +     0.593          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast
  5.862                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  6.178                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB1:YR (r)
               +     0.547          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB1_rgbr_net_1
  6.725                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  6.833                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:Q (f)
               +     0.977          net: PCIE_HPDMA_0/CORECONFIGP_0/CORECONFIGP_0_SOFT_RESET_F2M
  7.810                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg_RNINJUE[1]:A (f)
               +     0.099          cell: ADLIB:CFG1
  7.909                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg_RNINJUE[1]:Y (r)
               +     1.623          net: PCIE_HPDMA_0/CORECONFIGP_0_SOFT_RESET_F2M_i_0
  9.532                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  9.726                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPA (r)
               +     0.051          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/USER_MSS_RESET_N_net
  9.777                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N (r)
                                    
  9.777                        data arrival time
  ________________________________________________________
  Data required time calculation
  13.333                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  13.333                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  16.667                       
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  16.953                       PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  17.096                       PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.611          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  17.707                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  18.023                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.448          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  18.471                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  18.680                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  18.793                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     0.751          Library recovery time: ADLIB:MSS_120_IP
  18.042                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N
                                    
  18.042                       data required time


END SET FIC2_CLK to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

Clock Domain PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

SET Register to Register

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  Delay (ns):                  2.403                                                                           
  Slack (ns):                  5.286                                                                           
  Arrival (ns):                7.631                                                                           
  Required (ns):               12.917                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.714                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[6]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  Delay (ns):                  2.327                                                                           
  Slack (ns):                  5.357                                                                           
  Arrival (ns):                7.560                                                                           
  Required (ns):               12.917                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.643                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/hot_reset_n:EN
  Delay (ns):                  2.124                                                                           
  Slack (ns):                  5.495                                                                           
  Arrival (ns):                7.352                                                                           
  Required (ns):               12.847                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.505                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[5]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  Delay (ns):                  2.170                                                                           
  Slack (ns):                  5.526                                                                           
  Arrival (ns):                7.391                                                                           
  Required (ns):               12.917                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.474                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  Delay (ns):                  2.154                                                                           
  Slack (ns):                  5.542                                                                           
  Arrival (ns):                7.375                                                                           
  Required (ns):               12.917                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.458                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  data required time                             12.917    
  data arrival time                          -   7.631     
  slack                                          5.286     
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.316          Clock generation
  3.316                        
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  3.598                        PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.741                        PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.600          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  4.341                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  4.658                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:YL (r)
               +     0.570          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0_rgbl_net_1
  5.228                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  5.336                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:Q (f)
               +     0.480          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/count
  5.816                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_RNI0GFB[6]:A (f)
               +     0.087          cell: ADLIB:CFG2
  5.903                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_RNI0GFB[6]:Y (f)
               +     0.223          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/m6_3
  6.126                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_RNILUTB[4]:D (f)
               +     0.164          cell: ADLIB:CFG4
  6.290                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_RNILUTB[4]:Y (f)
               +     0.430          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/N_16_mux
  6.720                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state_RNO_0[0]:D (f)
               +     0.099          cell: ADLIB:CFG4
  6.819                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state_RNO_0[0]:Y (r)
               +     0.434          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/state_RNO_0[0]
  7.253                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state_RNO[0]:D (r)
               +     0.074          cell: ADLIB:CFG4
  7.327                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state_RNO[0]:Y (r)
               +     0.304          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/state_RNO[0]
  7.631                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D (r)
                                    
  7.631                        data arrival time
  ________________________________________________________
  Data required time calculation
  8.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  8.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.316          Clock generation
  11.316                       
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  11.598                       PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  11.741                       PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.600          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  12.341                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  12.658                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:YL (r)
               +     0.513          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0_rgbl_net_1
  13.171                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  12.917                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
                                    
  12.917                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_q:ALn
  Delay (ns):                  3.743                                                                           
  Slack (ns):                  3.846                                                                           
  Arrival (ns):                8.972                                                                           
  Required (ns):               12.818                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.154                                                                           
  Skew (ns):                   0.058                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[1]:ALn
  Delay (ns):                  3.743                                                                           
  Slack (ns):                  3.846                                                                           
  Arrival (ns):                8.972                                                                           
  Required (ns):               12.818                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.154                                                                           
  Skew (ns):                   0.058                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:ALn
  Delay (ns):                  3.743                                                                           
  Slack (ns):                  3.846                                                                           
  Arrival (ns):                8.972                                                                           
  Required (ns):               12.818                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.154                                                                           
  Skew (ns):                   0.058                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_entry_p:ALn
  Delay (ns):                  3.743                                                                           
  Slack (ns):                  3.846                                                                           
  Arrival (ns):                8.972                                                                           
  Required (ns):               12.818                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.154                                                                           
  Skew (ns):                   0.058                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_DetectQuiet:ALn
  Delay (ns):                  3.743                                                                           
  Slack (ns):                  3.846                                                                           
  Arrival (ns):                8.972                                                                           
  Required (ns):               12.818                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.154                                                                           
  Skew (ns):                   0.058                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_q:ALn
  data required time                             12.818    
  data arrival time                          -   8.972     
  slack                                          3.846     
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.316          Clock generation
  3.316                        
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  3.598                        PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.741                        PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.603          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  4.344                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB1:An (f)
               +     0.317          cell: ADLIB:RGB
  4.661                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB1:YL (r)
               +     0.568          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB1_rgbl_net_1
  5.229                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.316                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:Q (r)
               +     1.776          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_0
  7.092                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm_RNIR4M6:An (f)
               +     0.357          cell: ADLIB:GBM
  7.449                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm_RNIR4M6:YEn (f)
               +     0.599          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_YWn_GEast
  8.048                        PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  8.365                        PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_RGB1_RGB0:YL (r)
               +     0.607          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_RGB1_RGB0_rgbl_net_1
  8.972                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_q:ALn (r)
                                    
  8.972                        data arrival time
  ________________________________________________________
  Data required time calculation
  8.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  8.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.316          Clock generation
  11.316                       
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  11.598                       PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  11.741                       PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.600          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  12.341                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  12.658                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:YL (r)
               +     0.513          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0_rgbl_net_1
  13.171                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_q:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  12.818                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_q:ALn
                                    
  12.818                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

----------------------------------------------------

SET FIC2_CLK to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

No Path 

END SET FIC2_CLK to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

----------------------------------------------------

Clock Domain PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
  Delay (ns):                  2.570                                                                           
  Slack (ns):                  16.995                                                                          
  Arrival (ns):                10.976                                                                          
  Required (ns):               27.971                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         3.005                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[6]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
  Delay (ns):                  2.520                                                                           
  Slack (ns):                  17.057                                                                          
  Arrival (ns):                10.914                                                                          
  Required (ns):               27.971                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.943                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[7]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
  Delay (ns):                  2.420                                                                           
  Slack (ns):                  17.145                                                                          
  Arrival (ns):                10.826                                                                          
  Required (ns):               27.971                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.855                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[2]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
  Delay (ns):                  2.350                                                                           
  Slack (ns):                  17.227                                                                          
  Arrival (ns):                10.744                                                                          
  Required (ns):               27.971                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.773                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
  Delay (ns):                  2.275                                                                           
  Slack (ns):                  17.290                                                                          
  Arrival (ns):                10.681                                                                          
  Required (ns):               27.971                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.710                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
  data required time                             27.971    
  data arrival time                          -   10.976    
  slack                                          16.995    
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  1.392                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  1.544                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  6.588                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  6.945                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.568          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  7.513                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  7.830                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL (r)
               +     0.576          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1
  8.406                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  8.514                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:Q (f)
               +     0.611          net: PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]
  9.125                        PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core4_7:B (f)
               +     0.209          cell: ADLIB:CFG4
  9.334                        PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core4_7:Y (f)
               +     0.303          net: PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core4_7
  9.637                        PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core4:C (f)
               +     0.287          cell: ADLIB:CFG4
  9.924                        PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core4:Y (f)
               +     1.052          net: PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core4
  10.976                       PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN (f)
                                    
  10.976                       data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  21.392                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  21.544                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  26.588                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  26.945                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.568          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  27.513                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  27.830                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL (r)
               +     0.476          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1
  28.306                       PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  27.971                       PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core:EN
                                    
  27.971                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:ALn
  Delay (ns):                  4.458                                                                           
  Slack (ns):                  15.179                                                                          
  Arrival (ns):                12.807                                                                          
  Required (ns):               27.986                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.821                                                                           
  Skew (ns):                   0.010                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[8]:ALn
  Delay (ns):                  4.458                                                                           
  Slack (ns):                  15.179                                                                          
  Arrival (ns):                12.807                                                                          
  Required (ns):               27.986                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.821                                                                           
  Skew (ns):                   0.010                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]:ALn
  Delay (ns):                  4.458                                                                           
  Slack (ns):                  15.179                                                                          
  Arrival (ns):                12.807                                                                          
  Required (ns):               27.986                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.821                                                                           
  Skew (ns):                   0.010                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:ALn
  Delay (ns):                  4.457                                                                           
  Slack (ns):                  15.180                                                                          
  Arrival (ns):                12.806                                                                          
  Required (ns):               27.986                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.820                                                                           
  Skew (ns):                   0.010                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[2]:ALn
  Delay (ns):                  4.457                                                                           
  Slack (ns):                  15.180                                                                          
  Arrival (ns):                12.806                                                                          
  Required (ns):               27.986                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.820                                                                           
  Skew (ns):                   0.010                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:ALn
  data required time                             27.986    
  data arrival time                          -   12.807    
  slack                                          15.179    
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  1.392                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  1.544                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  6.588                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  6.945                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.566          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  7.511                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An (f)
               +     0.317          cell: ADLIB:RGB
  7.828                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL (r)
               +     0.521          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_O2F
  8.349                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK (r)
               +     0.092          cell: ADLIB:SLE
  8.441                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:Q (r)
               +     2.517          net: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc
  10.958                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3:An (f)
               +     0.357          cell: ADLIB:GBM
  11.315                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3:YEn (f)
               +     0.573          net: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_YWn_GEast
  11.888                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_RGB1:An (f)
               +     0.317          cell: ADLIB:RGB
  12.205                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_RGB1:YL (r)
               +     0.602          net: PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_rcosc
  12.807                       PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:ALn (r)
                                    
  12.807                       data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  21.392                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  21.544                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  26.588                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  26.945                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.568          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  27.513                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.317          cell: ADLIB:RGB
  27.830                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL (r)
               +     0.509          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1
  28.339                       PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  27.986                       PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:ALn
                                    
  27.986                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

----------------------------------------------------

Clock Domain FIC2_CLK

SET Register to Register

Path 1
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
  Delay (ns):                  2.951                                                                           
  Slack (ns):                  3.358                                                                           
  Arrival (ns):                2.951                                                                           
  Required (ns):               6.309                                                                           
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         -3.358                                                                          

Path 2
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/state[0]:D
  Delay (ns):                  2.468                                                                           
  Slack (ns):                  3.956                                                                           
  Arrival (ns):                2.468                                                                           
  Required (ns):               6.424                                                                           
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         -3.956                                                                          

Path 3
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/psel:CLK
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:D
  Delay (ns):                  13.400                                                                          
  Slack (ns):                  12.873                                                                          
  Arrival (ns):                20.289                                                                          
  Required (ns):               33.162                                                                          
  Setup (ns):                  0.174                                                                           
  Minimum Period (ns):         27.587                                                                          

Path 4
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/psel:CLK
  To:                          SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL
  Delay (ns):                  8.694                                                                           
  Slack (ns):                  15.955                                                                          
  Arrival (ns):                15.583                                                                          
  Required (ns):               31.538                                                                          
  Setup (ns):                  1.966                                                                           
  Minimum Period (ns):         21.422                                                                          

Path 5
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/SDIF0_PENABLE:CLK
  To:                          SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE
  Delay (ns):                  8.405                                                                           
  Slack (ns):                  18.046                                                                          
  Arrival (ns):                15.284                                                                          
  Required (ns):               33.330                                                                          
  Setup (ns):                  0.174                                                                           
  Minimum Period (ns):         17.240                                                                          


Expanded Path 1
  From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To: PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
  data required time                             6.309     
  data arrival time                          -   2.951     
  slack                                          3.358     
  ________________________________________________________
  Data arrival time calculation
  0.000                        FIC2_CLK
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     0.310          cell: ADLIB:MSS_120_IP
  0.310                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE (r)
               +     1.538          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE
  1.848                        PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o2:B (r)
               +     0.074          cell: ADLIB:CFG3
  1.922                        PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o2:Y (r)
               +     0.097          net: PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o2
  2.019                        PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_0:B (r)
               +     0.074          cell: ADLIB:CFG4
  2.093                        PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_0:Y (r)
               +     0.221          net: PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_0
  2.314                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:C (r)
               +     0.100          cell: ADLIB:CFG4
  2.414                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:Y (f)
               +     0.537          net: PCIE_HPDMA_0/CORECONFIGP_0/N_1327_i_0
  2.951                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN (f)
                                    
  2.951                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        FIC2_CLK
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.912          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK
  4.912                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An (f)
               +     0.357          cell: ADLIB:GBM
  5.269                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn (f)
               +     0.584          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast
  5.853                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB6:An (f)
               +     0.316          cell: ADLIB:RGB
  6.169                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB6:YR (r)
               +     0.475          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB6_rgbr_net_1
  6.644                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  6.309                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
                                    
  6.309                        data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D
  Delay (ns):                  2.058                                                                           
  Slack (ns):                  12.439                                                                          
  Arrival (ns):                7.309                                                                           
  Required (ns):               19.748                                                                          
  Setup (ns):                  0.254                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D
  Delay (ns):                  1.963                                                                           
  Slack (ns):                  12.542                                                                          
  Arrival (ns):                7.214                                                                           
  Required (ns):               19.756                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK
  To: PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D
  data required time                             19.748    
  data arrival time                          -   7.309     
  slack                                          12.439    
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.334          Clock generation
  3.334                        
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  3.620                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.763                        PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.587          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.350                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6:An (f)
               +     0.317          cell: ADLIB:RGB
  4.667                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6:YL (r)
               +     0.584          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB6_rgbl_net_1
  5.251                        PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK (r)
               +     0.092          cell: ADLIB:SLE
  5.343                        PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:Q (r)
               +     1.966          net: PCIE_HPDMA_0/CORERESETP_0_SDIF_RELEASED
  7.309                        PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D (r)
                                    
  7.309                        data arrival time
  ________________________________________________________
  Data required time calculation
  13.333                       FIC2_CLK
               +     0.000          Clock source
  13.333                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.912          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK
  18.245                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An (f)
               +     0.357          cell: ADLIB:GBM
  18.602                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn (f)
               +     0.588          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast
  19.190                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:An (f)
               +     0.316          cell: ADLIB:RGB
  19.506                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:YR (r)
               +     0.496          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4_rgbr_net_1
  20.002                       PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  19.748                       PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D
                                    
  19.748                       data required time


END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

