Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)

Date      :  Fri Feb 19 14:08:34 2016
Project   :  D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA
Component :  PCIE_HPDMA
Family    :  SmartFusion2


HDL source files for all Synthesis and Simulation tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA/CCC_0/PCIE_HPDMA_CCC_0_FCCC.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA/FABOSC_0/PCIE_HPDMA_FABOSC_0_OSC.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA/PCIE_HPDMA.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/PCIE_HPDMA_MSS.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/SgCore/OSC/2.0.101/osc_comps.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/PCIE_HPDMA_MSS_syn.v

HDL source files for Mentor Precision Synthesis tool:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/SgCore/OSC/2.0.101/osc_comps_pre.v
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/PCIE_HPDMA_MSS_pre.v

Stimulus files for all Simulation tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/Actel/SmartFusion2MSS/MSS/1.1.400/peripheral_init.bfm
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/CM3_compile_bfm.tcl
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/test.bfm
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/user.bfm

Firmware files for all Software IDE tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/sys_config_mddr_define.h
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/sys_config_mss_clocks.h

Configuration files to be used for Programming:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/ENVM.cfg

Configuration files to be used for all Simulation tools:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/ENVM.cfg
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/MDDR_init.bfm

Configuration files to be used for Power Analysis:
    D:/11.7_Upload/ADV_MSS_HPDMA/PCIE_HPDMA/component/work/PCIE_HPDMA_MSS/MDDR_init.reg

