Timing Violation Report Min Delay Analysis

SmartTime Version v11.6
Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)
Date: Wed Sep 23 17:50:04 2015


Design: PCIE_HPDMA_top
Family: SmartFusion2
Die: M2S150T
Package: 1152 FC
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/pwrite_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/pwrite_q2:D
  Delay (ns):                  0.291                                                                           
  Slack (ns):                  0.242                                                                           
  Arrival (ns):                3.546                                                                           
  Required (ns):               3.304                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.250                                                                           
  Arrival (ns):                3.566                                                                           
  Required (ns):               3.316                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q1[4]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q2[4]:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.250                                                                           
  Arrival (ns):                3.541                                                                           
  Required (ns):               3.291                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q1[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q2[0]:D
  Delay (ns):                  0.291                                                                           
  Slack (ns):                  0.251                                                                           
  Arrival (ns):                3.546                                                                           
  Required (ns):               3.295                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/sdif_core_reset_n_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/sdif_core_reset_n:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.253                                                                           
  Arrival (ns):                3.539                                                                           
  Required (ns):               3.286                                                                           

Path 6
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.254                                                                           
  Arrival (ns):                5.518                                                                           
  Required (ns):               5.264                                                                           

Path 7
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_state[1]:D
  Delay (ns):                  0.293                                                                           
  Slack (ns):                  0.254                                                                           
  Arrival (ns):                3.557                                                                           
  Required (ns):               3.303                                                                           

Path 8
  From:                        PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.542                                                                           
  Required (ns):               3.286                                                                           

Path 9
  From:                        PCIE_HPDMA_0/CORERESETP_0/ddr_settled_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled_clk_base:D
  Delay (ns):                  0.295                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.557                                                                           
  Required (ns):               3.301                                                                           

Path 10
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/psel_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/psel_q2:D
  Delay (ns):                  0.288                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.551                                                                           
  Required (ns):               3.295                                                                           

Path 11
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q1[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q2[1]:D
  Delay (ns):                  0.289                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.551                                                                           
  Required (ns):               3.295                                                                           

Path 12
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                3.553                                                                           
  Required (ns):               3.295                                                                           

Path 13
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/hot_reset_n:D
  Delay (ns):                  0.309                                                                           
  Slack (ns):                  0.261                                                                           
  Arrival (ns):                3.564                                                                           
  Required (ns):               3.303                                                                           

Path 14
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[9]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[9]:D
  Delay (ns):                  0.303                                                                           
  Slack (ns):                  0.263                                                                           
  Arrival (ns):                3.561                                                                           
  Required (ns):               3.298                                                                           

Path 15
  From:                        PCIE_HPDMA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.263                                                                           
  Arrival (ns):                3.549                                                                           
  Required (ns):               3.286                                                                           

Path 16
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q1[3]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q2[3]:D
  Delay (ns):                  0.305                                                                           
  Slack (ns):                  0.264                                                                           
  Arrival (ns):                3.568                                                                           
  Required (ns):               3.304                                                                           

Path 17
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[13]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[13]:D
  Delay (ns):                  0.304                                                                           
  Slack (ns):                  0.264                                                                           
  Arrival (ns):                3.562                                                                           
  Required (ns):               3.298                                                                           

Path 18
  From:                        COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/ahbcurr_state[1]:CLK
  To:                          COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/ahbcurr_state[1]:D
  Delay (ns):                  0.304                                                                           
  Slack (ns):                  0.265                                                                           
  Arrival (ns):                3.556                                                                           
  Required (ns):               3.291                                                                           

Path 19
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif3_spll_lock_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif3_spll_lock_q2:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.265                                                                           
  Arrival (ns):                3.570                                                                           
  Required (ns):               3.305                                                                           

Path 20
  From:                        COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/ahbcurr_state[0]:CLK
  To:                          COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/ahbcurr_state[0]:D
  Delay (ns):                  0.305                                                                           
  Slack (ns):                  0.266                                                                           
  Arrival (ns):                3.557                                                                           
  Required (ns):               3.291                                                                           

Path 21
  From:                        COREAHBLSRAM_0/U_SramCtrlIf/sramcurr_state[1]:CLK
  To:                          COREAHBLSRAM_0/U_SramCtrlIf/sramcurr_state[1]:D
  Delay (ns):                  0.304                                                                           
  Slack (ns):                  0.267                                                                           
  Arrival (ns):                3.562                                                                           
  Required (ns):               3.295                                                                           

Path 22
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_DetectQuiet:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_DetectQuiet_q:D
  Delay (ns):                  0.307                                                                           
  Slack (ns):                  0.267                                                                           
  Arrival (ns):                3.570                                                                           
  Required (ns):               3.303                                                                           

Path 23
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_state[2]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_state[2]:D
  Delay (ns):                  0.308                                                                           
  Slack (ns):                  0.268                                                                           
  Arrival (ns):                3.579                                                                           
  Required (ns):               3.311                                                                           

Path 24
  From:                        PCIE_HPDMA_0/CORERESETP_0/RESET_N_M2F_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/RESET_N_M2F_clk_base:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.548                                                                           
  Required (ns):               3.278                                                                           

Path 25
  From:                        PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_clk_base:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.573                                                                           
  Required (ns):               3.303                                                                           

Path 26
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_state[5]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_state[5]:D
  Delay (ns):                  0.310                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.581                                                                           
  Required (ns):               3.311                                                                           

Path 27
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[5]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[5]:D
  Delay (ns):                  0.310                                                                           
  Slack (ns):                  0.273                                                                           
  Arrival (ns):                3.551                                                                           
  Required (ns):               3.278                                                                           

Path 28
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[9]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[9]:D
  Delay (ns):                  0.310                                                                           
  Slack (ns):                  0.273                                                                           
  Arrival (ns):                3.546                                                                           
  Required (ns):               3.273                                                                           

Path 29
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/masterRegAddrSel:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/masterRegAddrSel:D
  Delay (ns):                  0.311                                                                           
  Slack (ns):                  0.274                                                                           
  Arrival (ns):                3.553                                                                           
  Required (ns):               3.279                                                                           

Path 30
  From:                        DEBOUNCE_0/DFF1:CLK
  To:                          DEBOUNCE_0/DFF2:D
  Delay (ns):                  0.315                                                                           
  Slack (ns):                  0.275                                                                           
  Arrival (ns):                3.588                                                                           
  Required (ns):               3.313                                                                           

Path 31
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif0_state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif0_state[0]:D
  Delay (ns):                  0.315                                                                           
  Slack (ns):                  0.276                                                                           
  Arrival (ns):                3.577                                                                           
  Required (ns):               3.301                                                                           

Path 32
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[13]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[13]:D
  Delay (ns):                  0.312                                                                           
  Slack (ns):                  0.276                                                                           
  Arrival (ns):                3.543                                                                           
  Required (ns):               3.267                                                                           

Path 33
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[1]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[1]:D
  Delay (ns):                  0.316                                                                           
  Slack (ns):                  0.276                                                                           
  Arrival (ns):                3.574                                                                           
  Required (ns):               3.298                                                                           

Path 34
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[1]:D
  Delay (ns):                  0.317                                                                           
  Slack (ns):                  0.277                                                                           
  Arrival (ns):                3.572                                                                           
  Required (ns):               3.295                                                                           

Path 35
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[13]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[13]:D
  Delay (ns):                  0.317                                                                           
  Slack (ns):                  0.278                                                                           
  Arrival (ns):                3.565                                                                           
  Required (ns):               3.287                                                                           

Path 36
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[5]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[5]:D
  Delay (ns):                  0.318                                                                           
  Slack (ns):                  0.279                                                                           
  Arrival (ns):                3.566                                                                           
  Required (ns):               3.287                                                                           

Path 37
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[9]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[9]:D
  Delay (ns):                  0.320                                                                           
  Slack (ns):                  0.281                                                                           
  Arrival (ns):                3.568                                                                           
  Required (ns):               3.287                                                                           

Path 38
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[7]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[7]:D
  Delay (ns):                  0.322                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.576                                                                           
  Required (ns):               3.294                                                                           

Path 39
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:D
  Delay (ns):                  0.321                                                                           
  Slack (ns):                  0.284                                                                           
  Arrival (ns):                3.556                                                                           
  Required (ns):               3.272                                                                           

Path 40
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[1]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[1]:D
  Delay (ns):                  0.324                                                                           
  Slack (ns):                  0.284                                                                           
  Arrival (ns):                3.578                                                                           
  Required (ns):               3.294                                                                           

Path 41
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[15]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[15]:D
  Delay (ns):                  0.326                                                                           
  Slack (ns):                  0.287                                                                           
  Arrival (ns):                3.574                                                                           
  Required (ns):               3.287                                                                           

Path 42
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[15]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[15]:D
  Delay (ns):                  0.325                                                                           
  Slack (ns):                  0.287                                                                           
  Arrival (ns):                3.571                                                                           
  Required (ns):               3.284                                                                           

Path 43
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_Disabled:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_Disabled_q:D
  Delay (ns):                  0.329                                                                           
  Slack (ns):                  0.289                                                                           
  Arrival (ns):                3.592                                                                           
  Required (ns):               3.303                                                                           

Path 44
  From:                        PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q3:D
  Delay (ns):                  0.327                                                                           
  Slack (ns):                  0.296                                                                           
  Arrival (ns):                3.603                                                                           
  Required (ns):               3.307                                                                           

Path 45
  From:                        PCIE_HPDMA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:D
  Delay (ns):                  0.346                                                                           
  Slack (ns):                  0.301                                                                           
  Arrival (ns):                3.595                                                                           
  Required (ns):               3.294                                                                           

Path 46
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_state[3]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable:D
  Delay (ns):                  0.359                                                                           
  Slack (ns):                  0.320                                                                           
  Arrival (ns):                3.625                                                                           
  Required (ns):               3.305                                                                           

Path 47
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif0_spll_lock_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif0_spll_lock_q2:D
  Delay (ns):                  0.368                                                                           
  Slack (ns):                  0.321                                                                           
  Arrival (ns):                3.634                                                                           
  Required (ns):               3.313                                                                           

Path 48
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/LTSSM_HotReset_q:D
  Delay (ns):                  0.363                                                                           
  Slack (ns):                  0.323                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.295                                                                           

Path 49
  From:                        PCIE_HPDMA_0/CORERESETP_0/release_sdif1_core_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif1_core_clk_base:D
  Delay (ns):                  0.382                                                                           
  Slack (ns):                  0.323                                                                           
  Arrival (ns):                3.637                                                                           
  Required (ns):               3.314                                                                           

Path 50
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:D
  Delay (ns):                  0.364                                                                           
  Slack (ns):                  0.324                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.294                                                                           

Path 51
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q1[2]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q2[2]:D
  Delay (ns):                  0.372                                                                           
  Slack (ns):                  0.325                                                                           
  Arrival (ns):                3.616                                                                           
  Required (ns):               3.291                                                                           

Path 52
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base:D
  Delay (ns):                  0.368                                                                           
  Slack (ns):                  0.326                                                                           
  Arrival (ns):                3.610                                                                           
  Required (ns):               3.284                                                                           

Path 53
  From:                        PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q3:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_re:D
  Delay (ns):                  0.365                                                                           
  Slack (ns):                  0.326                                                                           
  Arrival (ns):                3.633                                                                           
  Required (ns):               3.307                                                                           

Path 54
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_clk_base:D
  Delay (ns):                  0.369                                                                           
  Slack (ns):                  0.328                                                                           
  Arrival (ns):                3.640                                                                           
  Required (ns):               3.312                                                                           

Path 55
  From:                        COREAHBLSRAM_0/U_SramCtrlIf/sram_done:CLK
  To:                          COREAHBLSRAM_0/U_SramCtrlIf/sramahb_ack:D
  Delay (ns):                  0.366                                                                           
  Slack (ns):                  0.329                                                                           
  Arrival (ns):                3.630                                                                           
  Required (ns):               3.301                                                                           

Path 56
  From:                        PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_clk_base:D
  Delay (ns):                  0.360                                                                           
  Slack (ns):                  0.329                                                                           
  Arrival (ns):                3.634                                                                           
  Required (ns):               3.305                                                                           

Path 57
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:D
  Delay (ns):                  0.375                                                                           
  Slack (ns):                  0.332                                                                           
  Arrival (ns):                5.601                                                                           
  Required (ns):               5.269                                                                           

Path 58
  From:                        PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/release_sdif0_core_clk_base:D
  Delay (ns):                  0.367                                                                           
  Slack (ns):                  0.335                                                                           
  Arrival (ns):                3.640                                                                           
  Required (ns):               3.305                                                                           

Path 59
  From:                        PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_state[2]:D
  Delay (ns):                  0.386                                                                           
  Slack (ns):                  0.341                                                                           
  Arrival (ns):                3.652                                                                           
  Required (ns):               3.311                                                                           

Path 60
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:D
  Delay (ns):                  0.372                                                                           
  Slack (ns):                  0.342                                                                           
  Arrival (ns):                5.582                                                                           
  Required (ns):               5.240                                                                           

Path 61
  From:                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[3]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[2]:D
  Delay (ns):                  0.371                                                                           
  Slack (ns):                  0.348                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.272                                                                           

Path 62
  From:                        PCIE_HPDMA_0/CORERESETP_0/sm0_state[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/sm0_state[2]:D
  Delay (ns):                  0.396                                                                           
  Slack (ns):                  0.349                                                                           
  Arrival (ns):                3.660                                                                           
  Required (ns):               3.311                                                                           

Path 63
  From:                        COREAHBLSRAM_0/U_SramCtrlIf/sram_done:CLK
  To:                          COREAHBLSRAM_0/U_SramCtrlIf/sramcurr_state[1]:D
  Delay (ns):                  0.383                                                                           
  Slack (ns):                  0.352                                                                           
  Arrival (ns):                3.647                                                                           
  Required (ns):               3.295                                                                           

Path 64
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.280                                                                           

Path 65
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[5]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.280                                                                           

Path 66
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[15]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[14]:D
  Delay (ns):                  0.401                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                3.649                                                                           
  Required (ns):               3.293                                                                           

Path 67
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.280                                                                           

Path 68
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[3]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.280                                                                           

Path 69
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[9]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.280                                                                           

Path 70
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[7]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.280                                                                           

Path 71
  From:                        DEBOUNCE_0/q_reg[9]:CLK
  To:                          DEBOUNCE_0/q_reg[9]:D
  Delay (ns):                  0.399                                                                           
  Slack (ns):                  0.359                                                                           
  Arrival (ns):                3.675                                                                           
  Required (ns):               3.316                                                                           

Path 72
  From:                        DEBOUNCE_0/q_reg[3]:CLK
  To:                          DEBOUNCE_0/q_reg[3]:D
  Delay (ns):                  0.400                                                                           
  Slack (ns):                  0.360                                                                           
  Arrival (ns):                3.673                                                                           
  Required (ns):               3.313                                                                           

Path 73
  From:                        DEBOUNCE_0/q_reg[5]:CLK
  To:                          DEBOUNCE_0/q_reg[5]:D
  Delay (ns):                  0.400                                                                           
  Slack (ns):                  0.360                                                                           
  Arrival (ns):                3.673                                                                           
  Required (ns):               3.313                                                                           

Path 74
  From:                        DEBOUNCE_0/q_reg[13]:CLK
  To:                          DEBOUNCE_0/q_reg[13]:D
  Delay (ns):                  0.400                                                                           
  Slack (ns):                  0.360                                                                           
  Arrival (ns):                3.677                                                                           
  Required (ns):               3.317                                                                           

Path 75
  From:                        DEBOUNCE_0/q_reg[1]:CLK
  To:                          DEBOUNCE_0/q_reg[1]:D
  Delay (ns):                  0.400                                                                           
  Slack (ns):                  0.360                                                                           
  Arrival (ns):                3.673                                                                           
  Required (ns):               3.313                                                                           

Path 76
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.361                                                                           
  Arrival (ns):                5.641                                                                           
  Required (ns):               5.280                                                                           

Path 77
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[7]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[7]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.361                                                                           
  Arrival (ns):                5.641                                                                           
  Required (ns):               5.280                                                                           

Path 78
  From:                        DEBOUNCE_0/q_reg[11]:CLK
  To:                          DEBOUNCE_0/q_reg[11]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                3.678                                                                           
  Required (ns):               3.316                                                                           

Path 79
  From:                        DEBOUNCE_0/q_reg[7]:CLK
  To:                          DEBOUNCE_0/q_reg[7]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                3.675                                                                           
  Required (ns):               3.313                                                                           

Path 80
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[7]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[7]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.640                                                                           
  Required (ns):               5.278                                                                           

Path 81
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[5]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[5]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.642                                                                           
  Required (ns):               5.280                                                                           

Path 82
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[5]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[5]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.640                                                                           
  Required (ns):               5.278                                                                           

Path 83
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[9]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[9]:D
  Delay (ns):                  0.403                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.642                                                                           
  Required (ns):               5.280                                                                           

Path 84
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[1]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.640                                                                           
  Required (ns):               5.278                                                                           

Path 85
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[6]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[6]:D
  Delay (ns):                  0.403                                                                           
  Slack (ns):                  0.363                                                                           
  Arrival (ns):                3.654                                                                           
  Required (ns):               3.291                                                                           

Path 86
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:D
  Delay (ns):                  0.404                                                                           
  Slack (ns):                  0.363                                                                           
  Arrival (ns):                5.643                                                                           
  Required (ns):               5.280                                                                           

Path 87
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[3]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[3]:D
  Delay (ns):                  0.404                                                                           
  Slack (ns):                  0.363                                                                           
  Arrival (ns):                5.643                                                                           
  Required (ns):               5.280                                                                           

Path 88
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]:D
  Delay (ns):                  0.403                                                                           
  Slack (ns):                  0.363                                                                           
  Arrival (ns):                5.641                                                                           
  Required (ns):               5.278                                                                           

Path 89
  From:                        DEBOUNCE_0/q_reg[4]:CLK
  To:                          DEBOUNCE_0/q_reg[4]:D
  Delay (ns):                  0.403                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                3.669                                                                           
  Required (ns):               3.305                                                                           

Path 90
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[10]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.272                                                                           

Path 91
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[2]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.272                                                                           

Path 92
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[6]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.272                                                                           

Path 93
  From:                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[7]:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/slave_arbiter/arbRegSMCurrentState[6]:D
  Delay (ns):                  0.403                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                3.657                                                                           
  Required (ns):               3.293                                                                           

Path 94
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[11]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[11]:D
  Delay (ns):                  0.404                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.642                                                                           
  Required (ns):               5.278                                                                           

Path 95
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[8]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.272                                                                           

Path 96
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[4]:EN
  Delay (ns):                  0.432                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.636                                                                           
  Required (ns):               5.272                                                                           

Path 97
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[3]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[3]:D
  Delay (ns):                  0.404                                                                           
  Slack (ns):                  0.364                                                                           
  Arrival (ns):                5.642                                                                           
  Required (ns):               5.278                                                                           

Path 98
  From:                        DEBOUNCE_0/q_reg[6]:CLK
  To:                          DEBOUNCE_0/q_reg[6]:D
  Delay (ns):                  0.404                                                                           
  Slack (ns):                  0.365                                                                           
  Arrival (ns):                3.670                                                                           
  Required (ns):               3.305                                                                           

Path 99
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_sdif0[8]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0[8]:D
  Delay (ns):                  0.405                                                                           
  Slack (ns):                  0.365                                                                           
  Arrival (ns):                5.637                                                                           
  Required (ns):               5.272                                                                           

Path 100
  From:                        DEBOUNCE_0/q_reg[10]:CLK
  To:                          DEBOUNCE_0/q_reg[10]:D
  Delay (ns):                  0.404                                                                           
  Slack (ns):                  0.365                                                                           
  Arrival (ns):                3.672                                                                           
  Required (ns):               3.307                                                                           

