<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.7.0.119</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Fri Feb 19 14:21:35 2016
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>PCIE_HPDMA_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>12.260</cell>
 <cell>81.566</cell>
 <cell>12.500</cell>
 <cell>80.000</cell>
 <cell>0.504</cell>
 <cell>1.418</cell>
 <cell>8.919</cell>
 <cell>16.068</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>5.318</cell>
 <cell>188.041</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>19.934</cell>
 <cell>50.166</cell>
 <cell>50.000</cell>
 <cell>20.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[10]</cell>
 <cell>9.972</cell>
 <cell>0.240</cell>
 <cell>16.586</cell>
 <cell>16.826</cell>
 <cell>2.297</cell>
 <cell>12.260</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[18]</cell>
 <cell>9.938</cell>
 <cell>0.256</cell>
 <cell>16.552</cell>
 <cell>16.808</cell>
 <cell>2.315</cell>
 <cell>12.244</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[5]</cell>
 <cell>9.987</cell>
 <cell>0.261</cell>
 <cell>16.601</cell>
 <cell>16.862</cell>
 <cell>2.261</cell>
 <cell>12.239</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[17]</cell>
 <cell>9.982</cell>
 <cell>0.264</cell>
 <cell>16.596</cell>
 <cell>16.860</cell>
 <cell>2.263</cell>
 <cell>12.236</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[11]</cell>
 <cell>9.959</cell>
 <cell>0.294</cell>
 <cell>16.573</cell>
 <cell>16.867</cell>
 <cell>2.256</cell>
 <cell>12.206</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[10]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>16.586</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.240</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>4.604</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>4.802</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YWn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.177</cell>
 <cell>4.979</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB20:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.618</cell>
 <cell>5.597</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB20:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.317</cell>
 <cell>5.914</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_7:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB20_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.408</cell>
 <cell>6.322</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/IP_INTERFACE_7:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>6.531</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.083</cell>
 <cell>6.614</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:M_AWBURST_HTRANS[1]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SERDESIF_075_IP</cell>
 <cell>+</cell>
 <cell>1.088</cell>
 <cell>7.702</cell>
 <cell>4</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/SADDRSEL_i_o2[16]:B</cell>
 <cell>net</cell>
 <cell>SERDES_IF2_0_AHB_0_MASTER_HTRANS[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.710</cell>
 <cell>11.412</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/SADDRSEL_i_o2[16]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>11.486</cell>
 <cell>5</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNIEEMI[0]:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/N_62</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.451</cell>
 <cell>13.937</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNIEEMI[0]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.158</cell>
 <cell>14.095</cell>
 <cell>37</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/HADDR[10]:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/N_22_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.415</cell>
 <cell>15.510</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/HADDR[10]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>15.584</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_27:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1_AHBmslave16_HADDR[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.672</cell>
 <cell>16.256</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_27:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>16.465</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[10]</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/F_FM0_ADDR_net[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.121</cell>
 <cell>16.586</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.586</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.500</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>17.104</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>17.302</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>17.480</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.633</cell>
 <cell>18.113</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>18.429</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.406</cell>
 <cell>18.835</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>19.044</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.079</cell>
 <cell>19.123</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_FM0_ADDR[10]</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>-</cell>
 <cell>2.297</cell>
 <cell>16.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.826</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>External Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>GPIO_10_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO10A_F2H_GPIN</cell>
 <cell>5.581</cell>
 <cell></cell>
 <cell>5.581</cell>
 <cell></cell>
 <cell>1.294</cell>
 <cell>0.504</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>GPIO_11_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO11A_F2H_GPIN</cell>
 <cell>5.545</cell>
 <cell></cell>
 <cell>5.545</cell>
 <cell></cell>
 <cell>1.278</cell>
 <cell>0.452</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>GPIO_8_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO8A_F2H_GPIN</cell>
 <cell>5.502</cell>
 <cell></cell>
 <cell>5.502</cell>
 <cell></cell>
 <cell>1.136</cell>
 <cell>0.267</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>GPIO_9_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO9A_F2H_GPIN</cell>
 <cell>5.471</cell>
 <cell></cell>
 <cell>5.471</cell>
 <cell></cell>
 <cell>1.031</cell>
 <cell>0.131</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>SWITCH</cell>
 <cell>DEBOUNCE_0/DFF1:D</cell>
 <cell>4.393</cell>
 <cell></cell>
 <cell>4.393</cell>
 <cell></cell>
 <cell>0.254</cell>
 <cell>-1.527</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: GPIO_10_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO10A_F2H_GPIN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.581</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GPIO_10_F2M</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_10_F2M_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>GPIO_10_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_10_F2M_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>2.544</cell>
 <cell>2.544</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_10_F2M_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>GPIO_10_F2M_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>2.544</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_10_F2M_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.090</cell>
 <cell>2.634</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_158:A</cell>
 <cell>net</cell>
 <cell>GPIO_10_F2M_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.663</cell>
 <cell>5.297</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_158:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>5.496</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO10A_F2H_GPIN</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/MGPIO10A_F2H_GPIN_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.085</cell>
 <cell>5.581</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.581</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.172</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.155</cell>
 <cell>N/C</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.551</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.275</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.353</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.182</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.079</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO10A_F2H_GPIN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>-</cell>
 <cell>1.294</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_7_M2F</cell>
 <cell>9.433</cell>
 <cell></cell>
 <cell>16.068</cell>
 <cell></cell>
 <cell>16.068</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_5_M2F</cell>
 <cell>9.390</cell>
 <cell></cell>
 <cell>16.025</cell>
 <cell></cell>
 <cell>16.025</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_1_M2F</cell>
 <cell>9.160</cell>
 <cell></cell>
 <cell>15.795</cell>
 <cell></cell>
 <cell>15.795</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_0_M2F</cell>
 <cell>8.963</cell>
 <cell></cell>
 <cell>15.598</cell>
 <cell></cell>
 <cell>15.598</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_6_M2F</cell>
 <cell>8.941</cell>
 <cell></cell>
 <cell>15.576</cell>
 <cell></cell>
 <cell>15.576</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: GPIO_7_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>16.068</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>4.604</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>4.802</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>4.980</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.633</cell>
 <cell>5.613</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>5.929</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.406</cell>
 <cell>6.335</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>6.544</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.091</cell>
 <cell>6.635</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SS0_MGPIO7A_H2F_B</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>0.495</cell>
 <cell>7.130</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_7_M2F_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>GPIO_7_M2F_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>5.929</cell>
 <cell>13.059</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_7_M2F_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.343</cell>
 <cell>13.402</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_7_M2F_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>GPIO_7_M2F_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>13.402</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_7_M2F_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.666</cell>
 <cell>16.068</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>GPIO_7_M2F</cell>
 <cell>net</cell>
 <cell>GPIO_7_M2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>16.068</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>16.068</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GPIO_7_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[11]:ALn</cell>
 <cell>6.330</cell>
 <cell>5.767</cell>
 <cell>12.756</cell>
 <cell>18.523</cell>
 <cell>0.353</cell>
 <cell>6.733</cell>
 <cell>0.050</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[13]:ALn</cell>
 <cell>6.330</cell>
 <cell>5.767</cell>
 <cell>12.756</cell>
 <cell>18.523</cell>
 <cell>0.353</cell>
 <cell>6.733</cell>
 <cell>0.050</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[16]:ALn</cell>
 <cell>6.330</cell>
 <cell>5.767</cell>
 <cell>12.756</cell>
 <cell>18.523</cell>
 <cell>0.353</cell>
 <cell>6.733</cell>
 <cell>0.050</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[1]:ALn</cell>
 <cell>6.330</cell>
 <cell>5.767</cell>
 <cell>12.756</cell>
 <cell>18.523</cell>
 <cell>0.353</cell>
 <cell>6.733</cell>
 <cell>0.050</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[17]:ALn</cell>
 <cell>6.330</cell>
 <cell>5.767</cell>
 <cell>12.756</cell>
 <cell>18.523</cell>
 <cell>0.353</cell>
 <cell>6.733</cell>
 <cell>0.050</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[11]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>18.523</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>12.756</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.767</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>4.604</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>4.802</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>4.980</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.624</cell>
 <cell>5.604</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>5.920</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.506</cell>
 <cell>6.426</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>6.513</cell>
 <cell>23</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.371</cell>
 <cell>10.884</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>11.258</cell>
 <cell>6</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.621</cell>
 <cell>11.879</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>12.195</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[11]:ALn</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.561</cell>
 <cell>12.756</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.756</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.500</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>17.104</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>17.302</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>17.480</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.623</cell>
 <cell>18.103</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>18.419</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[11]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.457</cell>
 <cell>18.876</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/regHADDR[11]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>18.523</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>18.523</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FIC2_CLK to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_RESET_N</cell>
 <cell>1.971</cell>
 <cell>11.502</cell>
 <cell>7.303</cell>
 <cell>18.805</cell>
 <cell></cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>0.790</cell>
 <cell>12.507</cell>
 <cell>6.123</cell>
 <cell>18.630</cell>
 <cell>0.254</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>0.617</cell>
 <cell>12.692</cell>
 <cell>5.938</cell>
 <cell>18.630</cell>
 <cell>0.254</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_RESET_N</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>18.805</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.303</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.502</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.516</cell>
 <cell>3.516</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>3.890</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.596</cell>
 <cell>4.486</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>4.802</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.530</cell>
 <cell>5.332</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>5.440</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg_RNINJUE[1]:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/CORECONFIGP_0_SOFT_RESET_F2M</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.428</cell>
 <cell>5.868</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg_RNINJUE[1]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.099</cell>
 <cell>5.967</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_135:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0_SOFT_RESET_F2M_i_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.127</cell>
 <cell>7.094</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_135:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>7.303</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_RESET_N</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/USER_MSS_RESET_N_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.303</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.303</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.500</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>17.104</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>17.302</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>17.480</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.633</cell>
 <cell>18.113</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>18.429</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.406</cell>
 <cell>18.835</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>19.044</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.079</cell>
 <cell>19.123</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_RESET_N</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>-</cell>
 <cell>0.318</cell>
 <cell>18.805</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>18.805</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.471</cell>
 <cell>17.105</cell>
 <cell>10.768</cell>
 <cell>27.873</cell>
 <cell>0.335</cell>
 <cell>2.895</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.425</cell>
 <cell>17.151</cell>
 <cell>10.722</cell>
 <cell>27.873</cell>
 <cell>0.335</cell>
 <cell>2.849</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.326</cell>
 <cell>17.250</cell>
 <cell>10.623</cell>
 <cell>27.873</cell>
 <cell>0.335</cell>
 <cell>2.750</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[8]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.317</cell>
 <cell>17.258</cell>
 <cell>10.615</cell>
 <cell>27.873</cell>
 <cell>0.335</cell>
 <cell>2.742</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[1]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>2.285</cell>
 <cell>17.278</cell>
 <cell>10.595</cell>
 <cell>27.873</cell>
 <cell>0.335</cell>
 <cell>2.722</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>27.873</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.768</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.105</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.640</cell>
 <cell>2.640</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>2.792</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.693</cell>
 <cell>6.485</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>6.859</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.588</cell>
 <cell>7.447</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>7.763</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.534</cell>
 <cell>8.297</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>8.405</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled4_7:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.527</cell>
 <cell>8.932</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled4_7:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.287</cell>
 <cell>9.219</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled4:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled4_7</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.204</cell>
 <cell>9.423</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.287</cell>
 <cell>9.710</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.058</cell>
 <cell>10.768</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.768</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.640</cell>
 <cell>22.640</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>22.792</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.693</cell>
 <cell>26.485</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>26.859</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.588</cell>
 <cell>27.447</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>27.763</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.445</cell>
 <cell>28.208</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>27.873</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>27.873</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>4.897</cell>
 <cell>14.682</cell>
 <cell>13.193</cell>
 <cell>27.875</cell>
 <cell>0.353</cell>
 <cell>5.318</cell>
 <cell>0.068</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell>4.897</cell>
 <cell>14.682</cell>
 <cell>13.193</cell>
 <cell>27.875</cell>
 <cell>0.353</cell>
 <cell>5.318</cell>
 <cell>0.068</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_q1:ALn</cell>
 <cell>4.897</cell>
 <cell>14.682</cell>
 <cell>13.193</cell>
 <cell>27.875</cell>
 <cell>0.353</cell>
 <cell>5.318</cell>
 <cell>0.068</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[10]:ALn</cell>
 <cell>4.897</cell>
 <cell>14.682</cell>
 <cell>13.193</cell>
 <cell>27.875</cell>
 <cell>0.353</cell>
 <cell>5.318</cell>
 <cell>0.068</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:ALn</cell>
 <cell>4.896</cell>
 <cell>14.683</cell>
 <cell>13.192</cell>
 <cell>27.875</cell>
 <cell>0.353</cell>
 <cell>5.317</cell>
 <cell>0.068</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>27.875</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>13.193</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.682</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.640</cell>
 <cell>2.640</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>2.792</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.693</cell>
 <cell>6.485</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>6.859</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.587</cell>
 <cell>7.446</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>7.762</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.534</cell>
 <cell>8.296</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>8.383</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.956</cell>
 <cell>11.339</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>11.713</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.587</cell>
 <cell>12.300</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>12.616</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.577</cell>
 <cell>13.193</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.193</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>20.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>20.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.640</cell>
 <cell>22.640</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.152</cell>
 <cell>22.792</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.693</cell>
 <cell>26.485</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>26.859</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.588</cell>
 <cell>27.447</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>27.763</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.465</cell>
 <cell>28.228</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[4]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>27.875</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>27.875</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>2.537</cell>
 <cell>2.390</cell>
 <cell>2.537</cell>
 <cell>4.927</cell>
 <cell>0.335</cell>
 <cell>-2.390</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/state[0]:D</cell>
 <cell>2.034</cell>
 <cell>2.975</cell>
 <cell>2.034</cell>
 <cell>5.009</cell>
 <cell>0.254</cell>
 <cell>-2.975</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL</cell>
 <cell>7.096</cell>
 <cell>15.033</cell>
 <cell>12.761</cell>
 <cell>27.794</cell>
 <cell>2.663</cell>
 <cell>19.934</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/SDIF0_PENABLE:CLK</cell>
 <cell>SERDES_IF2_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE</cell>
 <cell>6.610</cell>
 <cell>17.477</cell>
 <cell>12.265</cell>
 <cell>29.742</cell>
 <cell>0.715</cell>
 <cell>15.046</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[16]:EN</cell>
 <cell>2.546</cell>
 <cell>21.732</cell>
 <cell>8.211</cell>
 <cell>29.943</cell>
 <cell>0.335</cell>
 <cell>6.536</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.927</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.390</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PENABLE</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>0.849</cell>
 <cell>0.849</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o4:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.788</cell>
 <cell>1.637</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.158</cell>
 <cell>1.795</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:C</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/N_50</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.096</cell>
 <cell>1.891</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>1.991</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/N_51_i_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.546</cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.537</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Max Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.516</cell>
 <cell>3.516</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>3.890</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.596</cell>
 <cell>4.486</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>4.802</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.460</cell>
 <cell>5.262</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.335</cell>
 <cell>4.927</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.927</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>0.612</cell>
 <cell>10.469</cell>
 <cell>7.041</cell>
 <cell>17.510</cell>
 <cell>0.254</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D</cell>
 <cell>0.591</cell>
 <cell>10.491</cell>
 <cell>7.011</cell>
 <cell>17.502</cell>
 <cell>0.254</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.510</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.041</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.469</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>4.604</cell>
 <cell>4.604</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.198</cell>
 <cell>4.802</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>4.980</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.624</cell>
 <cell>5.604</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>5.920</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.509</cell>
 <cell>6.429</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>6.516</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/INIT_DONE_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.525</cell>
 <cell>7.041</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.041</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.500</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.500</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.516</cell>
 <cell>16.016</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>16.390</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.596</cell>
 <cell>16.986</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>17.302</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.462</cell>
 <cell>17.764</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>17.510</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>17.510</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
