<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.7.0.119</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Fri Feb 19 14:21:36 2016
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>PCIE_HPDMA_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>12.260</cell>
 <cell>81.566</cell>
 <cell>12.500</cell>
 <cell>80.000</cell>
 <cell>0.504</cell>
 <cell>1.418</cell>
 <cell>8.919</cell>
 <cell>16.068</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>5.318</cell>
 <cell>188.041</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>19.934</cell>
 <cell>50.166</cell>
 <cell>50.000</cell>
 <cell>20.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_clk_base:D</cell>
 <cell>0.278</cell>
 <cell>0.229</cell>
 <cell>4.161</cell>
 <cell>3.932</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_clk_base:D</cell>
 <cell>0.283</cell>
 <cell>0.234</cell>
 <cell>4.158</cell>
 <cell>3.924</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_spll_lock_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_spll_lock_q2:D</cell>
 <cell>0.284</cell>
 <cell>0.235</cell>
 <cell>4.167</cell>
 <cell>3.932</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sm0_state[0]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sm0_state[1]:D</cell>
 <cell>0.285</cell>
 <cell>0.236</cell>
 <cell>4.168</cell>
 <cell>3.932</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_clk_base:D</cell>
 <cell>0.287</cell>
 <cell>0.238</cell>
 <cell>4.162</cell>
 <cell>3.924</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/ddr_settled_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/ddr_settled_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.161</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.932</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.229</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>2.766</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.886</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.992</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>3.365</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>3.555</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_q1:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.328</cell>
 <cell>3.883</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.935</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_clk_base:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.226</cell>
 <cell>4.161</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.161</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>2.766</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.886</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.992</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>3.365</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>3.555</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>3.932</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/ddr_settled_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.932</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.932</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
 <cell>External Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>SWITCH</cell>
 <cell>DEBOUNCE_0/DFF1:D</cell>
 <cell>2.591</cell>
 <cell></cell>
 <cell>2.591</cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>1.418</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>GPIO_9_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO9A_F2H_GPIN</cell>
 <cell>3.130</cell>
 <cell></cell>
 <cell>3.130</cell>
 <cell></cell>
 <cell>-0.730</cell>
 <cell>0.304</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>GPIO_8_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO8A_F2H_GPIN</cell>
 <cell>3.141</cell>
 <cell></cell>
 <cell>3.141</cell>
 <cell></cell>
 <cell>-0.742</cell>
 <cell>0.281</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>GPIO_11_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO11A_F2H_GPIN</cell>
 <cell>3.170</cell>
 <cell></cell>
 <cell>3.170</cell>
 <cell></cell>
 <cell>-0.848</cell>
 <cell>0.146</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>GPIO_10_F2M</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MGPIO10A_F2H_GPIN</cell>
 <cell>3.190</cell>
 <cell></cell>
 <cell>3.190</cell>
 <cell></cell>
 <cell>-0.850</cell>
 <cell>0.124</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: SWITCH</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: DEBOUNCE_0/DFF1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.591</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>SWITCH</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SWITCH_ibuf/U0/U_IOPAD:PAD</cell>
 <cell>net</cell>
 <cell>SWITCH</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SWITCH_ibuf/U0/U_IOPAD:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_IN</cell>
 <cell>+</cell>
 <cell>1.415</cell>
 <cell>1.415</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>SWITCH_ibuf/U0/U_IOINFF:A</cell>
 <cell>net</cell>
 <cell>SWITCH_ibuf/U0/YIN1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>1.415</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>SWITCH_ibuf/U0/U_IOINFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOINFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>1.465</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>DEBOUNCE_0/DFF1:D</cell>
 <cell>net</cell>
 <cell>SWITCH_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.126</cell>
 <cell>2.591</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.591</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.122</cell>
 <cell>N/C</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB19:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.394</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB19:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>N/C</cell>
 <cell>19</cell>
 <cell>r</cell>
</row>
<row>
 <cell>DEBOUNCE_0/DFF1:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB19_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>DEBOUNCE_0/DFF1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_3_M2F</cell>
 <cell>4.935</cell>
 <cell></cell>
 <cell>8.919</cell>
 <cell></cell>
 <cell>8.919</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_4_M2F</cell>
 <cell>4.936</cell>
 <cell></cell>
 <cell>8.920</cell>
 <cell></cell>
 <cell>8.920</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_2_M2F</cell>
 <cell>5.003</cell>
 <cell></cell>
 <cell>8.987</cell>
 <cell></cell>
 <cell>8.987</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_0_M2F</cell>
 <cell>5.003</cell>
 <cell></cell>
 <cell>8.987</cell>
 <cell></cell>
 <cell>8.987</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>GPIO_6_M2F</cell>
 <cell>5.091</cell>
 <cell></cell>
 <cell>9.075</cell>
 <cell></cell>
 <cell>9.075</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: GPIO_3_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.919</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>2.766</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.886</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.992</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.378</cell>
 <cell>3.370</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>3.560</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.244</cell>
 <cell>3.804</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.126</cell>
 <cell>3.930</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.984</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CAN_RXBUS_MGPIO3A_H2F_B</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>0.113</cell>
 <cell>4.097</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_3_M2F_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>GPIO_3_M2F_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.176</cell>
 <cell>7.273</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_3_M2F_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.212</cell>
 <cell>7.485</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_3_M2F_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>GPIO_3_M2F_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.485</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_3_M2F_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.434</cell>
 <cell>8.919</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>GPIO_3_M2F</cell>
 <cell>net</cell>
 <cell>GPIO_3_M2F</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>8.919</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.919</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>GPIO_3_M2F</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>0.480</cell>
 <cell>0.431</cell>
 <cell>4.336</cell>
 <cell>3.905</cell>
 <cell>0.000</cell>
 <cell>-0.049</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>0.480</cell>
 <cell>0.431</cell>
 <cell>4.336</cell>
 <cell>3.905</cell>
 <cell>0.000</cell>
 <cell>-0.049</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>0.480</cell>
 <cell>0.431</cell>
 <cell>4.336</cell>
 <cell>3.905</cell>
 <cell>0.000</cell>
 <cell>-0.049</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_q1:ALn</cell>
 <cell>1.216</cell>
 <cell>1.178</cell>
 <cell>5.075</cell>
 <cell>3.897</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_clk_base:ALn</cell>
 <cell>1.217</cell>
 <cell>1.179</cell>
 <cell>5.076</cell>
 <cell>3.897</cell>
 <cell>0.000</cell>
 <cell>-0.038</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.336</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.905</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.431</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>2.766</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.886</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.992</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.372</cell>
 <cell>3.364</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>3.554</cell>
 <cell>5</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.302</cell>
 <cell>3.856</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.908</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.428</cell>
 <cell>4.336</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.336</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>2.766</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.886</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.992</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>3.365</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>3.555</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/mss_ready_state:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.350</cell>
 <cell>3.905</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.905</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.905</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET FIC2_CLK to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>0.370</cell>
 <cell>23.643</cell>
 <cell>3.566</cell>
 <cell>-20.077</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>0.469</cell>
 <cell>23.749</cell>
 <cell>3.672</cell>
 <cell>-20.077</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:USER_MSS_RESET_N</cell>
 <cell>1.184</cell>
 <cell>24.603</cell>
 <cell>4.386</cell>
 <cell>-20.217</cell>
 <cell></cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.566</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-20.077</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>23.643</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.114</cell>
 <cell>2.114</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.338</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>2.694</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.884</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.312</cell>
 <cell>3.196</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>3.248</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0_CONFIG2_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.318</cell>
 <cell>3.566</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.566</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-24.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>-21.234</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>-21.114</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>-21.008</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>-20.635</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>-20.445</cell>
 <cell>24</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.368</cell>
 <cell>-20.077</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-20.077</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-20.077</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>0.287</cell>
 <cell>0.241</cell>
 <cell>5.258</cell>
 <cell>5.017</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:D</cell>
 <cell>0.358</cell>
 <cell>0.289</cell>
 <cell>5.321</cell>
 <cell>5.032</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[0]:EN</cell>
 <cell>0.384</cell>
 <cell>0.330</cell>
 <cell>5.355</cell>
 <cell>5.025</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_q1:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:D</cell>
 <cell>0.360</cell>
 <cell>0.330</cell>
 <cell>5.345</cell>
 <cell>5.015</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr[13]:EN</cell>
 <cell>0.384</cell>
 <cell>0.330</cell>
 <cell>5.355</cell>
 <cell>5.025</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.258</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.017</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.241</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.586</cell>
 <cell>1.586</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>1.678</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.220</cell>
 <cell>3.898</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>4.122</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.473</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.663</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.308</cell>
 <cell>4.971</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>5.023</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.235</cell>
 <cell>5.258</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.258</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.586</cell>
 <cell>1.586</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>1.678</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.220</cell>
 <cell>3.898</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>4.122</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.473</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.663</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.354</cell>
 <cell>5.017</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.017</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.017</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:ALn</cell>
 <cell>2.936</cell>
 <cell>2.880</cell>
 <cell>7.920</cell>
 <cell>5.040</cell>
 <cell>0.000</cell>
 <cell>-0.056</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[5]:ALn</cell>
 <cell>2.936</cell>
 <cell>2.880</cell>
 <cell>7.920</cell>
 <cell>5.040</cell>
 <cell>0.000</cell>
 <cell>-0.056</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[11]:ALn</cell>
 <cell>2.936</cell>
 <cell>2.880</cell>
 <cell>7.920</cell>
 <cell>5.040</cell>
 <cell>0.000</cell>
 <cell>-0.056</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[3]:ALn</cell>
 <cell>2.936</cell>
 <cell>2.880</cell>
 <cell>7.920</cell>
 <cell>5.040</cell>
 <cell>0.000</cell>
 <cell>-0.056</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[9]:ALn</cell>
 <cell>2.936</cell>
 <cell>2.880</cell>
 <cell>7.920</cell>
 <cell>5.040</cell>
 <cell>0.000</cell>
 <cell>-0.056</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.920</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.040</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.880</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.586</cell>
 <cell>1.586</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>1.678</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.220</cell>
 <cell>3.898</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>4.122</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.473</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.663</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.321</cell>
 <cell>4.984</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.052</cell>
 <cell>5.036</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.777</cell>
 <cell>6.813</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>7.037</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.350</cell>
 <cell>7.387</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>7.577</cell>
 <cell>15</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:ALn</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.343</cell>
 <cell>7.920</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.920</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.586</cell>
 <cell>1.586</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.092</cell>
 <cell>1.678</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.220</cell>
 <cell>3.898</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>4.122</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.473</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>4.663</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.377</cell>
 <cell>5.040</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/count_sdif0[1]:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.040</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.040</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/pwdata[15]:D</cell>
 <cell>0.888</cell>
 <cell>21.663</cell>
 <cell>0.888</cell>
 <cell>-20.775</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/paddr[7]:D</cell>
 <cell>0.911</cell>
 <cell>21.669</cell>
 <cell>0.911</cell>
 <cell>-20.758</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/paddr[5]:D</cell>
 <cell>0.920</cell>
 <cell>21.673</cell>
 <cell>0.920</cell>
 <cell>-20.753</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/pwdata[5]:D</cell>
 <cell>0.915</cell>
 <cell>21.680</cell>
 <cell>0.915</cell>
 <cell>-20.765</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/paddr[9]:D</cell>
 <cell>0.922</cell>
 <cell>21.682</cell>
 <cell>0.922</cell>
 <cell>-20.760</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORECONFIGP_0/pwdata[15]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.888</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-20.775</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>21.663</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PWDATA[15]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>0.443</cell>
 <cell>0.443</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/pwdata[15]:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.445</cell>
 <cell>0.888</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.888</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-24.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.114</cell>
 <cell>-21.886</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>-21.662</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.354</cell>
 <cell>-21.308</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>-21.118</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/pwdata[15]:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.343</cell>
 <cell>-20.775</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/pwdata[15]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-20.775</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-20.775</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_CLK</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D</cell>
 <cell>0.354</cell>
 <cell>0.965</cell>
 <cell>4.210</cell>
 <cell>3.245</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK</cell>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D</cell>
 <cell>0.367</cell>
 <cell>0.977</cell>
 <cell>4.228</cell>
 <cell>3.251</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.210</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.245</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.965</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.766</cell>
 <cell>2.766</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.120</cell>
 <cell>2.886</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.106</cell>
 <cell>2.992</cell>
 <cell>12</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>3.365</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>3.555</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.301</cell>
 <cell>3.856</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.064</cell>
 <cell>3.920</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/CORERESETP_0_SDIF_RELEASED</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>4.210</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.210</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.114</cell>
 <cell>2.114</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>2.338</cell>
 <cell>8</cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:An</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.354</cell>
 <cell>2.692</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>2.882</cell>
 <cell>32</cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:CLK</cell>
 <cell>net</cell>
 <cell>PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>3.245</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.245</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.245</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
