Timing Report Max Delay Analysis

SmartTime Version v11.6
Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)
Date: Wed Sep 23 14:26:21 2015


Design: PCIE_HPDMA_top
Family: SmartFusion2
Die: M2S150T
Package: 1152 FC
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               GL0                                                                             
Period (ns):                13.980                                                                          
Frequency (MHz):            71.531                                                                          
Required Period (ns):       12.500                                                                          
Required Frequency (MHz):   80.000                                                                          
External Setup (ns):        6.775                                                                           
External Hold (ns):         -2.274                                                                          
Min Clock-To-Out (ns):      6.609                                                                           
Max Clock-To-Out (ns):      11.291                                                                          

Clock Domain:               PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3                                     
Period (ns):                4.489                                                                           
Frequency (MHz):            222.767                                                                         
Required Period (ns):       7.955                                                                           
Required Frequency (MHz):   125.707                                                                         
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

Clock Domain:               PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                                   
Period (ns):                4.356                                                                           
Frequency (MHz):            229.568                                                                         
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

Clock Domain:               FIC2_APB                                                                        
Period (ns):                21.934                                                                          
Frequency (MHz):            45.591                                                                          
Required Period (ns):       50.000                                                                          
Required Frequency (MHz):   20.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain GL0

SET Register to Register

Path 1
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[22]
  Delay (ns):                  11.926                                                                          
  Slack (ns):                  -1.480                                                                          
  Arrival (ns):                13.998                                                                          
  Required (ns):               12.518                                                                          
  Setup (ns):                  2.108                                                                           
  Minimum Period (ns):         13.980                                                                          

Path 2
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[23]
  Delay (ns):                  11.820                                                                          
  Slack (ns):                  -1.367                                                                          
  Arrival (ns):                13.892                                                                          
  Required (ns):               12.525                                                                          
  Setup (ns):                  2.101                                                                           
  Minimum Period (ns):         13.867                                                                          

Path 3
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[11]
  Delay (ns):                  11.692                                                                          
  Slack (ns):                  -1.353                                                                          
  Arrival (ns):                13.764                                                                          
  Required (ns):               12.411                                                                          
  Setup (ns):                  2.215                                                                           
  Minimum Period (ns):         13.853                                                                          

Path 4
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[14]
  Delay (ns):                  11.744                                                                          
  Slack (ns):                  -1.299                                                                          
  Arrival (ns):                13.816                                                                          
  Required (ns):               12.517                                                                          
  Setup (ns):                  2.109                                                                           
  Minimum Period (ns):         13.799                                                                          

Path 5
  From:                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[30]
  Delay (ns):                  11.826                                                                          
  Slack (ns):                  -1.290                                                                          
  Arrival (ns):                13.898                                                                          
  Required (ns):               12.608                                                                          
  Setup (ns):                  2.018                                                                           
  Minimum Period (ns):         13.790                                                                          


Expanded Path 1
  From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE
  To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[22]
  data required time                             12.518    
  data arrival time                          -   13.998    
  slack                                          -1.480    
  ________________________________________________________
  Data arrival time calculation
  0.000                        GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  0.286                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  0.429                        PCIE_HPDMA_0/CCC_0/GL0_INST:YWn (f)
               +     0.570          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn
  0.999                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB35:An (f)
               +     0.317          cell: ADLIB:RGB
  1.316                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB35:YL (r)
               +     0.443          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB35_rgbl_net_1
  1.759                        SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_7:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  1.968                        SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_7:IPB (r)
               +     0.104          net: SERDES_IF_0/SERDESIF_INST/CLK_BASE_net
  2.072                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:CLK_BASE (r)
               +     0.580          cell: ADLIB:SERDESIF_120_IP
  2.652                        SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:M_AWADDR_HADDR[31] (f)
               +     6.386          net: SERDES_IF_0_AHB_MASTER_HADDR[31]
  9.038                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/HTRANS_i_o3:D (f)
               +     0.164          cell: ADLIB:CFG4
  9.202                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/HTRANS_i_o3:Y (f)
               +     0.222          net: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/N_202
  9.424                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2[0]:D (f)
               +     0.147          cell: ADLIB:CFG4
  9.571                        PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2[0]:Y (r)
               +     1.603          net: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/N_152
  11.174                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2_RNI7IFI[0]:D (r)
               +     0.074          cell: ADLIB:CFG4
  11.248                       PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/MASTERADDRINPROG_i_a2_0_a2_RNI7IFI[0]:Y (r)
               +     2.503          net: PCIE_HPDMA_0/N_118_i_0
  13.751                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_111:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  13.945                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_111:IPA (r)
               +     0.053          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/F_FM0_ADDR_net[22]
  13.998                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[22] (r)
                                    
  13.998                       data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       GL0
               +     0.000          Clock source
  12.500                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  12.786                       PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  12.929                       PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.611          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  13.540                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  13.856                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.448          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.304                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.513                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.626                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     2.108          Library setup time: ADLIB:MSS_120_IP
  12.518                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[22]
                                    
  12.518                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        GPIO_11_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11A_F2H_GPIN
  Delay (ns):                  7.108                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.108                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.591                                                                           
  External Setup (ns):         6.775                                                                           

Path 2
  From:                        GPIO_10_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10A_F2H_GPIN
  Delay (ns):                  6.982                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                6.982                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.705                                                                           
  External Setup (ns):         6.763                                                                           

Path 3
  From:                        GPIO_9_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO9A_F2H_GPIN
  Delay (ns):                  7.066                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.066                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.553                                                                           
  External Setup (ns):         6.695                                                                           

Path 4
  From:                        GPIO_8_F2M
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO8A_F2H_GPIN
  Delay (ns):                  7.071                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                7.071                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  1.459                                                                           
  External Setup (ns):         6.606                                                                           

Path 5
  From:                        SWITCH
  To:                          DEBOUNCE_0/DFF1:D
  Delay (ns):                  5.975                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.975                                                                           
  Required (ns):                                                                                               
  Setup (ns):                  0.174                                                                           
  External Setup (ns):         4.401                                                                           


Expanded Path 1
  From: GPIO_11_F2M
  To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11A_F2H_GPIN
  data required time                             N/C       
  data arrival time                          -   7.108     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        GPIO_11_F2M (f)
               +     0.000          net: GPIO_11_F2M
  0.000                        GPIO_11_F2M_ibuf/U0/U_IOPAD:PAD (f)
               +     1.835          cell: ADLIB:IOPAD_IN
  1.835                        GPIO_11_F2M_ibuf/U0/U_IOPAD:Y (f)
               +     0.000          net: GPIO_11_F2M_ibuf/U0/YIN1
  1.835                        GPIO_11_F2M_ibuf/U0/U_IOINFF:A (f)
               +     0.090          cell: ADLIB:IOINFF_BYPASS
  1.925                        GPIO_11_F2M_ibuf/U0/U_IOINFF:Y (f)
               +     4.903          net: GPIO_11_F2M_c
  6.828                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_218:A (f)
               +     0.199          cell: ADLIB:IP_INTERFACE
  7.027                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_218:IPA (f)
               +     0.081          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/MGPIO11A_F2H_GPIN_net
  7.108                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11A_F2H_GPIN (f)
                                    
  7.108                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          GL0
               +     0.000          Clock source
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.257          net: PCIE_HPDMA_0/CCC_0/GL0_net
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.129          cell: ADLIB:GBM
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.550          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.284          cell: ADLIB:RGB
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.403          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.188          cell: ADLIB:IP_INTERFACE
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     1.591          Library setup time: ADLIB:MSS_120_IP
  N/C                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11A_F2H_GPIN


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_6_M2F
  Delay (ns):                  9.152                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.291                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.291                                                                          

Path 2
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_5_M2F
  Delay (ns):                  9.059                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.198                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.198                                                                          

Path 3
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_4_M2F
  Delay (ns):                  9.031                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.170                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.170                                                                          

Path 4
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_7_M2F
  Delay (ns):                  9.023                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.162                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.162                                                                          

Path 5
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          GPIO_0_M2F
  Delay (ns):                  8.974                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                11.113                                                                          
  Required (ns):                                                                                               
  Clock to Out (ns):           11.113                                                                          


Expanded Path 1
  From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To: GPIO_6_M2F
  data required time                             N/C       
  data arrival time                          -   11.291    
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  0.286                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  0.429                        PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.611          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  1.040                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  1.356                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.448          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  1.804                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  2.013                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.126          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  2.139                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               +     0.844          cell: ADLIB:MSS_120_IP
  2.983                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_MGPIO6A_H2F_B (f)
               +     5.010          net: GPIO_6_M2F_c
  7.993                        GPIO_6_M2F_obuf/U0/U_IOOUTFF:A (f)
               +     0.343          cell: ADLIB:IOOUTFF_BYPASS
  8.336                        GPIO_6_M2F_obuf/U0/U_IOOUTFF:Y (f)
               +     0.000          net: GPIO_6_M2F_obuf/U0/DOUT
  8.336                        GPIO_6_M2F_obuf/U0/U_IOPAD:D (f)
               +     2.955          cell: ADLIB:IOPAD_TRI
  11.291                       GPIO_6_M2F_obuf/U0/U_IOPAD:PAD (f)
               +     0.000          net: GPIO_6_M2F
  11.291                       GPIO_6_M2F (f)
                                    
  11.291                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          GL0
               +     0.000          Clock source
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
                                    
  N/C                          GPIO_6_M2F (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[7]:ALn
  Delay (ns):                  4.363                                                                           
  Slack (ns):                  7.687                                                                           
  Arrival (ns):                6.256                                                                           
  Required (ns):               13.943                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.813                                                                           
  Skew (ns):                   0.097                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[6]:ALn
  Delay (ns):                  4.357                                                                           
  Slack (ns):                  7.687                                                                           
  Arrival (ns):                6.250                                                                           
  Required (ns):               13.937                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.813                                                                           
  Skew (ns):                   0.103                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[8]:ALn
  Delay (ns):                  4.361                                                                           
  Slack (ns):                  7.687                                                                           
  Arrival (ns):                6.254                                                                           
  Required (ns):               13.941                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.813                                                                           
  Skew (ns):                   0.099                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[9]:ALn
  Delay (ns):                  4.361                                                                           
  Slack (ns):                  7.687                                                                           
  Arrival (ns):                6.254                                                                           
  Required (ns):               13.941                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.813                                                                           
  Skew (ns):                   0.099                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[29]:ALn
  Delay (ns):                  4.361                                                                           
  Slack (ns):                  7.687                                                                           
  Arrival (ns):                6.254                                                                           
  Required (ns):               13.941                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.813                                                                           
  Skew (ns):                   0.099                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To: PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[7]:ALn
  data required time                             13.943    
  data arrival time                          -   6.256     
  slack                                          7.687     
  ________________________________________________________
  Data arrival time calculation
  0.000                        GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  0.286                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  0.429                        PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.615          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  1.044                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB15:An (f)
               +     0.316          cell: ADLIB:RGB
  1.360                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB15:YR (r)
               +     0.533          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB15_rgbr_net_1
  1.893                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK (r)
               +     0.087          cell: ADLIB:SLE
  1.980                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int:Q (r)
               +     2.475          net: PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int
  4.455                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6:An (f)
               +     0.357          cell: ADLIB:GBM
  4.812                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6:YWn (f)
               +     0.549          net: PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_YWn
  5.361                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1_RGB27:An (f)
               +     0.317          cell: ADLIB:RGB
  5.678                        PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1_RGB27:YL (r)
               +     0.578          net: PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1_RGB27_rgbl_net_1
  6.256                        PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[7]:ALn (r)
                                    
  6.256                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       GL0
               +     0.000          Clock source
  12.500                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  12.786                       PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  12.929                       PCIE_HPDMA_0/CCC_0/GL0_INST:YWn (f)
               +     0.551          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn
  13.480                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB33:An (f)
               +     0.317          cell: ADLIB:RGB
  13.797                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB33:YL (r)
               +     0.499          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB33_rgbl_net_1
  14.296                       PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[7]:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  13.943                       PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/arbRegSMCurrentState[7]:ALn
                                    
  13.943                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:ALn
  Delay (ns):                  5.051                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.051                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      3.703                                                                           

Path 2
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q3:ALn
  Delay (ns):                  5.051                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.051                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      3.703                                                                           

Path 3
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q2:ALn
  Delay (ns):                  5.051                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.051                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      3.695                                                                           

Path 4
  From:                        SDIF0_PERST_N
  To:                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_re:ALn
  Delay (ns):                  5.051                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                5.051                                                                           
  Required (ns):                                                                                               
  Recovery (ns):               0.353                                                                           
  External Recovery (ns):      3.695                                                                           


Expanded Path 1
  From: SDIF0_PERST_N
  To: PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:ALn
  data required time                             N/C       
  data arrival time                          -   5.051     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        SDIF0_PERST_N (r)
               +     0.000          net: SDIF0_PERST_N
  0.000                        SDIF0_PERST_N_ibuf/U0/U_IOPAD:PAD (r)
               +     2.430          cell: ADLIB:IOPAD_IN
  2.430                        SDIF0_PERST_N_ibuf/U0/U_IOPAD:Y (r)
               +     0.000          net: SDIF0_PERST_N_ibuf/U0/YIN1
  2.430                        SDIF0_PERST_N_ibuf/U0/U_IOINFF:A (r)
               +     0.083          cell: ADLIB:IOINFF_BYPASS
  2.513                        SDIF0_PERST_N_ibuf/U0/U_IOINFF:Y (r)
               +     2.538          net: SDIF0_PERST_N_c
  5.051                        PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:ALn (r)
                                    
  5.051                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          GL0
               +     0.000          Clock source
  N/C                          PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.257          net: PCIE_HPDMA_0/CCC_0/GL0_net
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.129          cell: ADLIB:GBM
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.554          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB14:An (f)
               +     0.284          cell: ADLIB:RGB
  N/C                          PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB14:YR (r)
               +     0.477          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB14_rgbr_net_1
  N/C                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  N/C                          PCIE_HPDMA_0/CORERESETP_0/SDIF0_PERST_N_q1:ALn


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path 

END SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 to GL0

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 to GL0

----------------------------------------------------

SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to GL0

No Path 

END SET PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to GL0

----------------------------------------------------

SET FIC2_APB to GL0

Path 1
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK
  To:                          PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N
  Delay (ns):                  2.400                                                                           
  Slack (ns):                  4.811                                                                           
  Arrival (ns):                9.064                                                                           
  Required (ns):               13.875                                                                          
  Setup (ns):                                                                                                  

Path 2
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG1_DONE_q1:D
  Delay (ns):                  2.461                                                                           
  Slack (ns):                  5.006                                                                           
  Arrival (ns):                9.113                                                                           
  Required (ns):               14.119                                                                          
  Setup (ns):                  0.254                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/control_reg_1[1]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/CONFIG2_DONE_q1:D
  Delay (ns):                  0.829                                                                           
  Slack (ns):                  6.601                                                                           
  Arrival (ns):                7.493                                                                           
  Required (ns):               14.094                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK
  To: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N
  data required time                             13.875    
  data arrival time                          -   9.064     
  slack                                          4.811     
  ________________________________________________________
  Data arrival time calculation
  0.000                        FIC2_APB
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.818          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK
  4.818                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An (f)
               +     0.357          cell: ADLIB:GBM
  5.175                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn (f)
               +     0.592          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast
  5.767                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  6.083                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB1:YR (r)
               +     0.581          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB1_rgbr_net_1
  6.664                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  6.772                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg[1]:Q (f)
               +     0.056          net: PCIE_HPDMA_0/CORECONFIGP_0/CORECONFIGP_0_SOFT_RESET_F2M
  6.828                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg_RNINJUE[1]:A (f)
               +     0.354          cell: ADLIB:CFG1
  7.182                        PCIE_HPDMA_0/CORECONFIGP_0/soft_reset_reg_RNINJUE[1]:Y (r)
               +     1.637          net: PCIE_HPDMA_0/CORECONFIGP_0_SOFT_RESET_F2M_i_0
  8.819                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  9.013                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_204:IPA (r)
               +     0.051          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/USER_MSS_RESET_N_net
  9.064                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N (r)
                                    
  9.064                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       GL0
               +     0.000          Clock source
  12.500                       PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  12.786                       PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  12.929                       PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.611          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  13.540                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  13.856                       PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1:YR (r)
               +     0.448          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_YR
  14.304                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  14.513                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  14.626                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     0.751          Library recovery time: ADLIB:MSS_120_IP
  13.875                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N
                                    
  13.875                       data required time


END SET FIC2_APB to GL0

----------------------------------------------------

Clock Domain PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

SET Register to Register

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[0]:D
  Delay (ns):                  2.386                                                                           
  Slack (ns):                  5.252                                                                           
  Arrival (ns):                7.654                                                                           
  Required (ns):               12.906                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.703                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[6]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  Delay (ns):                  2.384                                                                           
  Slack (ns):                  5.265                                                                           
  Arrival (ns):                7.646                                                                           
  Required (ns):               12.911                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.690                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:D
  Delay (ns):                  2.336                                                                           
  Slack (ns):                  5.307                                                                           
  Arrival (ns):                7.604                                                                           
  Required (ns):               12.911                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         2.648                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[6]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/hot_reset_n:EN
  Delay (ns):                  2.229                                                                           
  Slack (ns):                  5.339                                                                           
  Arrival (ns):                7.491                                                                           
  Required (ns):               12.830                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.616                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/hot_reset_n:EN
  Delay (ns):                  2.181                                                                           
  Slack (ns):                  5.381                                                                           
  Arrival (ns):                7.449                                                                           
  Required (ns):               12.830                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.574                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[0]:D
  data required time                             12.906    
  data arrival time                          -   7.654     
  slack                                          5.252     
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.346          Clock generation
  3.346                        
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  3.628                        PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.771                        PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.605          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  4.376                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  4.692                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0:YR (r)
               +     0.576          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB0_rgbr_net_1
  5.268                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  5.376                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/state[0]:Q (f)
               +     0.515          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/count
  5.891                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_s_303:B (f)
               +     0.200          cell: ADLIB:ARI1_CC
  6.091                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_s_303:P (f)
               +     0.000          net: NET_CC_CONFIG0
  6.091                        PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/count_s_303_CC_0:P[0] (f)
               +     0.260          cell: ADLIB:CC_CONFIG
  6.351                        PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/count_s_303_CC_0:CC[1] (r)
               +     0.000          net: NET_CC_CONFIG5
  6.351                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_cry[0]:CC (r)
               +     0.066          cell: ADLIB:ARI1_CC
  6.417                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count_cry[0]:S (r)
               +     1.237          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/count_s[0]
  7.654                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[0]:D (r)
                                    
  7.654                        data arrival time
  ________________________________________________________
  Data required time calculation
  7.955                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  7.955                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.346          Clock generation
  11.301                       
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  11.583                       PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  11.726                       PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.602          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  12.328                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  12.644                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1:YR (r)
               +     0.516          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_YR
  13.160                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[0]:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  12.906                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[0]:D
                                    
  12.906                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[5]:ALn
  Delay (ns):                  4.061                                                                           
  Slack (ns):                  3.466                                                                           
  Arrival (ns):                9.330                                                                           
  Required (ns):               12.796                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.489                                                                           
  Skew (ns):                   0.075                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[4]:ALn
  Delay (ns):                  4.061                                                                           
  Slack (ns):                  3.466                                                                           
  Arrival (ns):                9.330                                                                           
  Required (ns):               12.796                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.489                                                                           
  Skew (ns):                   0.075                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q2[4]:ALn
  Delay (ns):                  4.061                                                                           
  Slack (ns):                  3.466                                                                           
  Arrival (ns):                9.330                                                                           
  Required (ns):               12.796                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.489                                                                           
  Skew (ns):                   0.075                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/ltssm_q1[4]:ALn
  Delay (ns):                  4.061                                                                           
  Slack (ns):                  3.466                                                                           
  Arrival (ns):                9.330                                                                           
  Required (ns):               12.796                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.489                                                                           
  Skew (ns):                   0.075                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[1]:ALn
  Delay (ns):                  4.061                                                                           
  Slack (ns):                  3.466                                                                           
  Arrival (ns):                9.330                                                                           
  Required (ns):               12.796                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.489                                                                           
  Skew (ns):                   0.075                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[5]:ALn
  data required time                             12.796    
  data arrival time                          -   9.330     
  slack                                          3.466     
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.346          Clock generation
  3.346                        
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  3.628                        PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.771                        PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.606          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  4.377                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  4.693                        PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB1:YR (r)
               +     0.576          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_RGB1_rgbr_net_1
  5.269                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.356                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm:Q (r)
               +     2.107          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_0
  7.463                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm_RNIR4M6:An (f)
               +     0.357          cell: ADLIB:GBM
  7.820                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm_RNIR4M6:YEn (f)
               +     0.600          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_YWn_GEast
  8.420                        PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  8.736                        PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_RGB1:YR (r)
               +     0.594          net: PCIE_HPDMA_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIR4M6/U0_RGB1_YR
  9.330                        PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[5]:ALn (r)
                                    
  9.330                        data arrival time
  ________________________________________________________
  Data required time calculation
  7.955                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3
               +     0.000          Clock source
  7.955                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3 (r)
               +     3.346          Clock generation
  11.301                       
               +     0.282          net: PCIE_HPDMA_0/CCC_0/GL3_net
  11.583                       PCIE_HPDMA_0/CCC_0/GL3_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  11.726                       PCIE_HPDMA_0/CCC_0/GL3_INST:YEn (f)
               +     0.602          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_YWn_GEast
  12.328                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  12.644                       PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1:YR (r)
               +     0.505          net: PCIE_HPDMA_0/CCC_0/GL3_INST/U0_RGB1_YR
  13.149                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[5]:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  12.796                       PCIE_HPDMA_0/CORERESETP_0/genblk2.sdif0_phr/count[5]:ALn
                                    
  12.796                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

----------------------------------------------------

SET GL0 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

No Path 

END SET GL0 to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

----------------------------------------------------

SET FIC2_APB to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

No Path 

END SET FIC2_APB to PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL3

----------------------------------------------------

Clock Domain PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.690                                                                           
  Slack (ns):                  16.885                                                                          
  Arrival (ns):                11.118                                                                          
  Required (ns):               28.003                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         3.115                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[11]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.445                                                                           
  Slack (ns):                  17.130                                                                          
  Arrival (ns):                10.873                                                                          
  Required (ns):               28.003                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.870                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[7]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.356                                                                           
  Slack (ns):                  17.219                                                                          
  Arrival (ns):                10.784                                                                          
  Required (ns):               28.003                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.781                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[3]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.345                                                                           
  Slack (ns):                  17.231                                                                          
  Arrival (ns):                10.772                                                                          
  Required (ns):               28.003                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.769                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.326                                                                           
  Slack (ns):                  17.261                                                                          
  Arrival (ns):                10.742                                                                          
  Required (ns):               28.003                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.739                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
  data required time                             28.003    
  data arrival time                          -   11.118    
  slack                                          16.885    
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  1.392                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  1.544                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  6.588                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  6.945                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.595          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  7.540                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  7.856                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR (r)
               +     0.572          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1
  8.428                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  8.536                        PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]:Q (f)
               +     0.851          net: PCIE_HPDMA_0/CORERESETP_0/count_ddr[9]
  9.387                        PCIE_HPDMA_0/CORERESETP_0/ddr_settled4_7:B (f)
               +     0.287          cell: ADLIB:CFG4
  9.674                        PCIE_HPDMA_0/CORERESETP_0/ddr_settled4_7:Y (f)
               +     0.221          net: PCIE_HPDMA_0/CORERESETP_0/ddr_settled4_7
  9.895                        PCIE_HPDMA_0/CORERESETP_0/ddr_settled4:C (f)
               +     0.164          cell: ADLIB:CFG4
  10.059                       PCIE_HPDMA_0/CORERESETP_0/ddr_settled4:Y (f)
               +     1.059          net: PCIE_HPDMA_0/CORERESETP_0/ddr_settled4
  11.118                       PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN (f)
                                    
  11.118                       data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  21.392                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  21.544                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  26.588                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  26.945                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.593          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  27.538                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  27.854                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR (r)
               +     0.484          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR
  28.338                       PCIE_HPDMA_0/CORERESETP_0/ddr_settled:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  28.003                       PCIE_HPDMA_0/CORERESETP_0/ddr_settled:EN
                                    
  28.003                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:ALn
  Delay (ns):                  3.925                                                                           
  Slack (ns):                  15.644                                                                          
  Arrival (ns):                12.341                                                                          
  Required (ns):               27.985                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.356                                                                           
  Skew (ns):                   0.078                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/ddr_settled:ALn
  Delay (ns):                  3.925                                                                           
  Slack (ns):                  15.644                                                                          
  Arrival (ns):                12.341                                                                          
  Required (ns):               27.985                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.356                                                                           
  Skew (ns):                   0.078                                                                           

Path 3
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_rcosc:ALn
  Delay (ns):                  3.925                                                                           
  Slack (ns):                  15.644                                                                          
  Arrival (ns):                12.341                                                                          
  Required (ns):               27.985                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.356                                                                           
  Skew (ns):                   0.078                                                                           

Path 4
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_ddr[6]:ALn
  Delay (ns):                  3.939                                                                           
  Slack (ns):                  15.652                                                                          
  Arrival (ns):                12.355                                                                          
  Required (ns):               28.007                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.348                                                                           
  Skew (ns):                   0.056                                                                           

Path 5
  From:                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To:                          PCIE_HPDMA_0/CORERESETP_0/count_sdif0_enable_rcosc:ALn
  Delay (ns):                  3.925                                                                           
  Slack (ns):                  15.652                                                                          
  Arrival (ns):                12.341                                                                          
  Required (ns):               27.993                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         4.348                                                                           
  Skew (ns):                   0.070                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK
  To: PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:ALn
  data required time                             27.985    
  data arrival time                          -   12.341    
  slack                                          15.644    
  ________________________________________________________
  Data arrival time calculation
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  1.392                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  1.544                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  6.588                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  6.945                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.595          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  7.540                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  7.856                        PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR (r)
               +     0.560          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1
  8.416                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK (r)
               +     0.087          cell: ADLIB:SLE
  8.503                        PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc:Q (r)
               +     1.985          net: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc
  10.488                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3:An (f)
               +     0.357          cell: ADLIB:GBM
  10.845                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3:YEn (f)
               +     0.600          net: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_YWn_GEast
  11.445                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  11.761                       PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_RGB1:YR (r)
               +     0.580          net: PCIE_HPDMA_0/CORERESETP_0/sdif1_areset_n_rcosc_RNI09V3/U0_RGB1_YR
  12.341                       PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:ALn (r)
                                    
  12.341                       data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  20.000                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  21.392                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  21.544                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.044          net: PCIE_HPDMA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  26.588                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  26.945                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.593          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  27.538                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  27.854                       PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR (r)
               +     0.484          net: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR
  28.338                       PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  27.985                       PCIE_HPDMA_0/CORERESETP_0/count_ddr_enable_q1:ALn
                                    
  27.985                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

No Path 

END SET PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

----------------------------------------------------

SET GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

No Path 

END SET GL0 to PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

----------------------------------------------------

Clock Domain FIC2_APB

SET Register to Register

Path 1
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
  Delay (ns):                  3.027                                                                           
  Slack (ns):                  3.190                                                                           
  Arrival (ns):                3.027                                                                           
  Required (ns):               6.217                                                                           
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         -3.190                                                                          

Path 2
  From:                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/state[0]:D
  Delay (ns):                  2.335                                                                           
  Slack (ns):                  3.997                                                                           
  Arrival (ns):                2.335                                                                           
  Required (ns):               6.332                                                                           
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         -3.997                                                                          

Path 3
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/psel:CLK
  To:                          SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL
  Delay (ns):                  8.841                                                                           
  Slack (ns):                  14.033                                                                          
  Arrival (ns):                15.743                                                                          
  Required (ns):               29.776                                                                          
  Setup (ns):                  1.966                                                                           
  Minimum Period (ns):         21.934                                                                          

Path 4
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/SDIF0_PENABLE:CLK
  To:                          SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE
  Delay (ns):                  8.681                                                                           
  Slack (ns):                  15.975                                                                          
  Arrival (ns):                15.593                                                                          
  Required (ns):               31.568                                                                          
  Setup (ns):                  0.174                                                                           
  Minimum Period (ns):         18.050                                                                          

Path 5
  From:                        PCIE_HPDMA_0/CORECONFIGP_0/psel:CLK
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:D
  Delay (ns):                  3.330                                                                           
  Slack (ns):                  21.101                                                                          
  Arrival (ns):                10.232                                                                          
  Required (ns):               31.333                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         7.798                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To: PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
  data required time                             6.217     
  data arrival time                          -   3.027     
  slack                                          3.190     
  ________________________________________________________
  Data arrival time calculation
  0.000                        FIC2_APB
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     0.310          cell: ADLIB:MSS_120_IP
  0.310                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE (r)
               +     1.910          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE
  2.220                        PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_a2:A (r)
               +     0.074          cell: ADLIB:CFG4
  2.294                        PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_a2:Y (r)
               +     0.092          net: PCIE_HPDMA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_a2
  2.386                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:C (r)
               +     0.100          cell: ADLIB:CFG4
  2.486                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:Y (f)
               +     0.541          net: PCIE_HPDMA_0/CORECONFIGP_0/N_1327_i_0
  3.027                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN (f)
                                    
  3.027                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        FIC2_APB
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.818          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK
  4.818                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An (f)
               +     0.357          cell: ADLIB:GBM
  5.175                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn (f)
               +     0.593          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast
  5.768                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:An (f)
               +     0.316          cell: ADLIB:RGB
  6.084                        PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4:YR (r)
               +     0.468          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB4_rgbr_net_1
  6.552                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  6.217                        PCIE_HPDMA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
                                    
  6.217                        data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET GL0 to FIC2_APB

Path 1
  From:                        PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D
  Delay (ns):                  5.388                                                                           
  Slack (ns):                  11.629                                                                          
  Arrival (ns):                7.302                                                                           
  Required (ns):               18.931                                                                          
  Setup (ns):                  0.174                                                                           

Path 2
  From:                        PCIE_HPDMA_0/CORERESETP_0/SDIF_RELEASED_int:CLK
  To:                          PCIE_HPDMA_0/CORECONFIGP_0/SDIF_RELEASED_q1:D
  Delay (ns):                  4.994                                                                           
  Slack (ns):                  11.991                                                                          
  Arrival (ns):                6.908                                                                           
  Required (ns):               18.899                                                                          
  Setup (ns):                  0.165                                                                           


Expanded Path 1
  From: PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK
  To: PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D
  data required time                             18.931    
  data arrival time                          -   7.302     
  slack                                          11.629    
  ________________________________________________________
  Data arrival time calculation
  0.000                        GL0
               +     0.000          Clock source
  0.000                        PCIE_HPDMA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     0.286          net: PCIE_HPDMA_0/CCC_0/GL0_net
  0.286                        PCIE_HPDMA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  0.429                        PCIE_HPDMA_0/CCC_0/GL0_INST:YEn (f)
               +     0.609          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_YWn_GEast
  1.038                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  1.354                        PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR (r)
               +     0.560          net: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1
  1.914                        PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:CLK (r)
               +     0.108          cell: ADLIB:SLE
  2.022                        PCIE_HPDMA_0/CORERESETP_0/INIT_DONE_int:Q (f)
               +     0.604          net: PCIE_HPDMA_0/INIT_DONE_int
  2.626                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST2:A (f)
               +     0.209          cell: ADLIB:CFG1C_TEST
  2.835                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST2:Y (f)
               +     0.301          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST_net2
  3.136                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST2:A (f)
               +     0.372          cell: ADLIB:CFG1D_TEST
  3.508                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST2:Y (f)
               +     0.229          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST_net2
  3.737                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST1:A (f)
               +     0.209          cell: ADLIB:CFG1C_TEST
  3.946                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST1:Y (f)
               +     0.221          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST_net1
  4.167                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST0:A (f)
               +     0.209          cell: ADLIB:CFG1C_TEST
  4.376                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST0:Y (f)
               +     0.205          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST_net0
  4.581                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST1:A (f)
               +     0.372          cell: ADLIB:CFG1D_TEST
  4.953                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST1:Y (f)
               +     0.221          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST_net1
  5.174                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST:A (f)
               +     0.209          cell: ADLIB:CFG1C_TEST
  5.383                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST:Y (f)
               +     0.304          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1C_TEST_net
  5.687                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST0:A (f)
               +     0.372          cell: ADLIB:CFG1D_TEST
  6.059                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST0:Y (f)
               +     0.205          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST_net0
  6.264                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST:A (f)
               +     0.372          cell: ADLIB:CFG1D_TEST
  6.636                        mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST:Y (f)
               +     0.666          net: mdr_PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1_CFG1D_TEST_net
  7.302                        PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D (f)
                                    
  7.302                        data arrival time
  ________________________________________________________
  Data required time calculation
  12.500                       FIC2_APB
               +     0.000          Clock source
  12.500                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.818          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK
  17.318                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:An (f)
               +     0.357          cell: ADLIB:GBM
  17.675                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F:YEn (f)
               +     0.590          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_YWn_GEast
  18.265                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:An (f)
               +     0.316          cell: ADLIB:RGB
  18.581                       PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5:YR (r)
               +     0.524          net: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1_RGB5_rgbr_net_1
  19.105                       PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:CLK (r)
               -     0.174          Library setup time: ADLIB:SLE
  18.931                       PCIE_HPDMA_0/CORECONFIGP_0/INIT_DONE_q1:D
                                    
  18.931                       data required time


END SET GL0 to FIC2_APB

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

----------------------------------------------------

Path set User Sets

