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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Fri Feb 19 14:13:07 2016
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>3.3V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>PCIE_HPDMA_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\synthesis\PCIE_HPDMA_top.edn</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\constraint\fic_sdc.sdc</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>D:\11.7_Upload\ADV_MSS_HPDMA\PCIE_HPDMA\constraint\io\PCIE_HPDMA_top.io.pdc</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>1238</cell>
 <cell>86184</cell>
 <cell>1.44</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>966</cell>
 <cell>86184</cell>
 <cell>1.12</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>795</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>66</cell>
 <cell>265</cell>
 <cell>24.91</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>62</cell>
 <cell>265</cell>
 <cell>23.40</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>2</cell>
 <cell>132</cell>
 <cell>1.52</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>112</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>16</cell>
 <cell>109</cell>
 <cell>14.68</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>84</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>7</cell>
 <cell>16</cell>
 <cell>43.75</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>6</cell>
 <cell>16.67</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>1</cell>
 <cell>4</cell>
 <cell>25.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>662</cell>
 <cell>390</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>576</cell>
 <cell>576</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>1238</cell>
 <cell>966</cell>
</row>
</table>
<section><name>MSS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Cortex-M3*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eNVM (512KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>TIMER*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>CAN</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>I2C</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>UART</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>USB</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MAC</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the MSS</text>
<text></text>
<section><name>SERDESIF Lanes Usage</name></section>
<table>
<header>
 <cell>SERDESIF</cell>
 <cell>Lane0</cell>
 <cell>Lane1</cell>
 <cell>Lane2</cell>
 <cell>Lane3</cell>
</header>
<row>
 <cell>SERDESIF_0</cell>
 <cell>PCIE1 (Gen2)</cell>
 <cell>----</cell>
 <cell>----</cell>
 <cell>----</cell>
</row>
</table>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>13</cell>
 <cell>1</cell>
</row>
<row>
 <cell>14</cell>
 <cell>1</cell>
</row>
<row>
 <cell>17</cell>
 <cell>1</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>3</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>7</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>35</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>20</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS18</cell>
 <cell> 1.80v</cell>
 <cell> N/A</cell>
 <cell> 1</cell>
 <cell> 27</cell>
 <cell> 20</cell>
</row>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 6</cell>
 <cell> 8</cell>
 <cell> 0</cell>
</row>
<row>
 <cell>LPDDRI (Output)</cell>
 <cell> 1.80v</cell>
 <cell> N/A</cell>
 <cell> 0</cell>
 <cell> 2</cell>
 <cell> 0</cell>
</row>
<row>
 <cell>LVDS</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 2</cell>
 <cell> 0</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 66</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>279</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0_FIC_0_CLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>218</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0_MSS_READY</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORERESETP_0/MSS_HPMS_READY_int_RNI83M6/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>113</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0_INIT_APB_S_PRESET_N</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/MSS_ADLIB_INST_RNIBVN5/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>111</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0_INIT_APB_S_PCLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/PCIE_HPDMA_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNI3E2F/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>36</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/FABOSC_0_RCOSC_25_50MHZ_O2F</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>34</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_rcosc</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIVPL9/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>29</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CORERESETP_0/sm0_areset_n_clk_base</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORERESETP_0/sdif0_areset_n_clk_base_RNIPQFE/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>72</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[14]</cell>
</row>
<row>
 <cell>53</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>47</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CORECONFIGP_0/state_347_d</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORECONFIGP_0/state_s0_0_a2_0_a2</cell>
</row>
<row>
 <cell>44</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>41</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[13]</cell>
</row>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[15]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[15]</cell>
</row>
<row>
 <cell>38</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/m7</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/N_42</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/N_22_1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNIEEMI[0]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>72</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[14]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[14]</cell>
</row>
<row>
 <cell>53</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>47</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CORECONFIGP_0/state_347_d</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORECONFIGP_0/state_s0_0_a2_0_a2</cell>
</row>
<row>
 <cell>44</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterRegAddrSel</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/masterRegAddrSel</cell>
</row>
<row>
 <cell>41</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CORECONFIGP_0/state[1]</cell>
</row>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[13]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[13]</cell>
</row>
<row>
 <cell>40</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREAHBLSRAM_0/ahbsram_addr[15]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREAHBLSRAM_0/U_PCIE_HPDMA_top_COREAHBLSRAM_0_AHBLSramIf/HADDR_d[15]</cell>
</row>
<row>
 <cell>38</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/N_152</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_0/matrix4x16/slavestage_1/m7</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/N_42</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMNextState_i_a2</cell>
</row>
<row>
 <cell>37</cell>
 <cell>INT_NET</cell>
 <cell>Net   : PCIE_HPDMA_0/N_22_1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: PCIE_HPDMA_0/CoreAHBLite_1/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_RNIEEMI[0]</cell>
</row>
</table>
</doc>
