#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Tue Apr 20 18:41:38 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\CCC_0\demo_CCC_0_FCCC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\FABOSC_0\demo_FABOSC_0_OSC.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo_MSS\demo_MSS_syn.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo_MSS\demo_MSS.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\demo.v" (library work) @I::"C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... @N:CG364 : demo_CCC_0_FCCC.v(5) | Synthesizing module demo_CCC_0_FCCC in library work. Running optimization stage 1 on demo_CCC_0_FCCC ....... @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z1 Running optimization stage 1 on CoreResetP_Z1 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work. Running optimization stage 1 on OUTBUF ....... @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... @N:CG364 : demo_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... @N:CG364 : demo_MSS.v(9) | Synthesizing module demo_MSS in library work. Running optimization stage 1 on demo_MSS ....... @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... @N:CG364 : demo_FABOSC_0_OSC.v(5) | Synthesizing module demo_FABOSC_0_OSC in library work. Running optimization stage 1 on demo_FABOSC_0_OSC ....... @W:CL318 : demo_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : demo_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : demo_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : demo_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... @N:CG364 : demo.v(9) | Synthesizing module demo in library work. Running optimization stage 1 on demo ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on demo ....... Running optimization stage 2 on SYSRESET ....... Running optimization stage 2 on demo_FABOSC_0_OSC ....... @N:CL159 : demo_FABOSC_0_OSC.v(14) | Input XTL is unused. Running optimization stage 2 on RCOSC_25_50MHZ ....... Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Running optimization stage 2 on demo_MSS ....... Running optimization stage 2 on BIBUF ....... Running optimization stage 2 on MSS_075 ....... Running optimization stage 2 on TRIBUFF ....... Running optimization stage 2 on INBUF ....... Running optimization stage 2 on OUTBUF ....... Running optimization stage 2 on CoreResetP_Z1 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused. Running optimization stage 2 on demo_CCC_0_FCCC ....... Running optimization stage 2 on CCC ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 93MB peak: 94MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime Process completed successfully. # Tue Apr 20 18:41:42 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 92MB peak: 93MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Apr 20 18:41:42 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 23MB peak: 24MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime Process completed successfully. # Tue Apr 20 18:41:42 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 93MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Apr 20 18:41:43 2021 ###########################################################] Premap Report # Tue Apr 20 18:41:44 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Reading constraint file: C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(8) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 130MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 130MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 132MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance demo_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : demo_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance demo_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance demo_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance demo_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance demo_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance demo_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance demo_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance demo_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance demo_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance demo_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance demo_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance demo_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance demo_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance demo_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance demo_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance demo_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 165MB) @W:MT688 : synthesis.fdc(8) | No path from master pin (-source) to source of clock demo_0/CCC_0/GL0 due to black box demo_0.CCC_0.CCC_INST Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 15 1 . demo_0/CCC_0/GL0 100.0 MHz 10.000 generated (from demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 36 ========================================================================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 15 demo_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) demo_0.CORERESETP_0.release_sdif0_core.C - demo_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) demo_0/CCC_0/GL0 36 demo_0.CCC_0.CCC_INST.GL0(CCC) demo_0.demo_MSS_0.MSS_ADLIB_INST.CLK_BASE - demo_0.CCC_0.GL0_INST.I(BUFG) ============================================================================================================================================================================================================================================ @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 166MB peak: 166MB) Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 168MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 168MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 82MB peak: 169MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Apr 20 18:41:46 2021 ###########################################################] Map & Optimize Report # Tue Apr 20 18:41:46 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 161MB peak: 161MB) @N:MO111 : demo_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : demo_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.demo_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance demo_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance demo_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance demo_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance demo_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance demo_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance demo_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(929) | Removing sequential instance demo_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance demo_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 165MB peak: 165MB) Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 166MB peak: 166MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.INIT_DONE_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[6] (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 167MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 168MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 168MB) @W:BN114 : demo.v(304) | Removing instance demo_0.SYSRESET_POR (in view: work.top(verilog)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances. @N:BN362 : coreresetp.v(1549) | Removing sequential instance demo_0.CORERESETP_0.release_sdif2_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1517) | Removing sequential instance demo_0.CORERESETP_0.release_sdif1_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1485) | Removing sequential instance demo_0.CORERESETP_0.release_sdif0_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(526) | Removing sequential instance demo_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(511) | Removing sequential instance demo_0.CORERESETP_0.RESET_N_M2F_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(496) | Removing sequential instance demo_0.CORERESETP_0.POWER_ON_RESET_N_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif3_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif2_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif1_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif0_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.ddr_settled_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(963) | Removing sequential instance demo_0.CORERESETP_0.sdif3_spll_lock_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(929) | Removing sequential instance demo_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance demo_0.CORERESETP_0.sm0_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance demo_0.CORERESETP_0.sm0_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance demo_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance demo_0.CORERESETP_0.sm0_areset_n_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(526) | Removing sequential instance demo_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(511) | Removing sequential instance demo_0.CORERESETP_0.RESET_N_M2F_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(496) | Removing sequential instance demo_0.CORERESETP_0.POWER_ON_RESET_N_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif3_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif2_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif1_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.release_sdif0_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance demo_0.CORERESETP_0.ddr_settled_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1613) | Removing sequential instance demo_0.CORERESETP_0.ddr_settled (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1581) | Removing sequential instance demo_0.CORERESETP_0.release_sdif3_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(912) | Removing sequential instance demo_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(912) | Removing sequential instance demo_0.CORERESETP_0.sdif3_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(898) | Removing sequential instance demo_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(898) | Removing sequential instance demo_0.CORERESETP_0.sdif2_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(884) | Removing sequential instance demo_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(884) | Removing sequential instance demo_0.CORERESETP_0.sdif1_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance demo_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance demo_0.CORERESETP_0.sdif0_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(565) | Removing sequential instance demo_0.CORERESETP_0.MSS_HPMS_READY_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance demo_0.CORERESETP_0.sm0_state[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(545) | Removing sequential instance demo_0.CORERESETP_0.mss_ready_state (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(545) | Removing sequential instance demo_0.CORERESETP_0.mss_ready_select (in view: work.top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 168MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 168MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 100000.00ns 13 / 0 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 168MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 168MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 1 clock pin(s) of sequential element(s) 0 instances converted, 1 sequential instance remains driven by gated/generated clocks =========================================================================== Gated/Generated Clocks =========================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 demo_0.CCC_0.CCC_INST CCC 1 demo_0.demo_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ============================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 169MB) Writing Analyst data base C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 169MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 169MB) Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 168MB peak: 169MB) @W:MT246 : demo_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock demo_0/CCC_0/GL0 with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Tue Apr 20 18:41:49 2021 # Top view: top Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: NA Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- demo_0/CCC_0/GL0 100.0 MHz NA 10.000 NA NA generated (from demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz NA 20.000 NA NA declared default_clkgroup =========================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------- ======================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(9) | Timing constraint (through [get_nets { demo_0.CORERESETP_0.ddr_settled demo_0.CORERESETP_0.count_ddr_enable demo_0.CORERESETP_0.release_sdif*_core demo_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(10) | Timing constraint (from [get_cells { demo_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { demo_0.CORERESETP_0.sm0_areset_n_rcosc demo_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(11) | Timing constraint (from [get_cells { demo_0.CORERESETP_0.MSS_HPMS_READY_int demo_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { demo_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(12) | Timing constraint (through [get_nets { demo_0.CORERESETP_0.CONFIG1_DONE demo_0.CORERESETP_0.CONFIG2_DONE demo_0.CORERESETP_0.SDIF*_PERST_N demo_0.CORERESETP_0.SDIF*_PSEL demo_0.CORERESETP_0.SDIF*_PWRITE demo_0.CORERESETP_0.SDIF*_PRDATA[*] demo_0.CORERESETP_0.SOFT_EXT_RESET_OUT demo_0.CORERESETP_0.SOFT_RESET_F2M demo_0.CORERESETP_0.SOFT_M3_RESET demo_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET demo_0.CORERESETP_0.SOFT_FDDR_CORE_RESET demo_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET demo_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET demo_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET demo_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_pins { demo_0.demo_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (through [get_pins { demo_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 169MB) Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 169MB peak: 169MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 1 use MSS_075 1 use RCOSC_25_50MHZ 1 use Sequential Cells: SLE 0 uses DSP Blocks: 0 of 84 (0%) I/O ports: 21 I/O primitives: 20 BIBUF 10 uses INBUF 5 uses OUTBUF 2 uses TRIBUFF 3 uses Global Clock Buffers: 1 Total LUTs: 0 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 0 + 0 + 0 + 0 = 0; Total number of LUTs after P&R: 0 + 0 + 0 + 0 = 0; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 63MB peak: 169MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Apr 20 18:41:50 2021 ###########################################################]