@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance demo_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance demo_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance demo_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance demo_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance demo_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance demo_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance demo_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance demo_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN114 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\work\demo\demo.v":304:9:304:20|Removing instance demo_0.SYSRESET_POR (in view: work.top(verilog)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.
@W: MT246 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\work\demo\ccc_0\demo_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":9:0:9:0|Timing constraint (through [get_nets { demo_0.CORERESETP_0.ddr_settled demo_0.CORERESETP_0.count_ddr_enable demo_0.CORERESETP_0.release_sdif*_core demo_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":10:0:10:0|Timing constraint (from [get_cells { demo_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { demo_0.CORERESETP_0.sm0_areset_n_rcosc demo_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":11:0:11:0|Timing constraint (from [get_cells { demo_0.CORERESETP_0.MSS_HPMS_READY_int demo_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { demo_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":12:0:12:0|Timing constraint (through [get_nets { demo_0.CORERESETP_0.CONFIG1_DONE demo_0.CORERESETP_0.CONFIG2_DONE demo_0.CORERESETP_0.SDIF*_PERST_N demo_0.CORERESETP_0.SDIF*_PSEL demo_0.CORERESETP_0.SDIF*_PWRITE demo_0.CORERESETP_0.SDIF*_PRDATA[*] demo_0.CORERESETP_0.SOFT_EXT_RESET_OUT demo_0.CORERESETP_0.SOFT_RESET_F2M demo_0.CORERESETP_0.SOFT_M3_RESET demo_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET demo_0.CORERESETP_0.SOFT_FDDR_CORE_RESET demo_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET demo_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET demo_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET demo_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":13:0:13:0|Timing constraint (through [get_pins { demo_0.demo_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":14:0:14:0|Timing constraint (through [get_pins { demo_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
