Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Tue Apr 20 18:45:34 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S090TS
Package: 484 FBGA
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 125.997 100.0%
Static Power 22.801 18.1%
Dynamic Power 103.197 81.9%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 95.231 1.200 79.360
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038
Rail VDDI 2.5 3.441 2.500 1.376
Rail CCC_NW1_PLL_VDDA 9.000 3.300 2.727

Breakdown by Clock

Power (mW) Percentage
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 72.164 100.0%
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.000 0.0%
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.000 0.0%
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SCK_USBA_XCLK_OUT (clocks) 0.000 0.0%
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SCK_USBA_XCLK_OUT (register outputs) 0.000 0.0%
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SCK_USBA_XCLK_OUT (primary inputs) 0.000 0.0%
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SCK_USBA_XCLK_OUT (combinational outputs) 0.000 0.0%
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:SPI0_SCK_USBA_XCLK_OUT (set/reset nets) 0.000 0.0%
demo_0/demo_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (clocks) 0.000 0.0%
demo_0/demo_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (register outputs) 0.000 0.0%
demo_0/demo_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (primary inputs) 0.000 0.0%
demo_0/demo_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (combinational outputs) 0.000 0.0%
demo_0/demo_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (set/reset nets) 0.000 0.0%
USB_ULPI_XCLK (clocks) 0.000 0.0%
USB_ULPI_XCLK (register outputs) 0.000 0.0%
USB_ULPI_XCLK (primary inputs) 0.000 0.0%
USB_ULPI_XCLK (combinational outputs) 0.000 0.0%
USB_ULPI_XCLK (set/reset nets) 0.000 0.0%
demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.000 0.0%
demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.011 0.0%
demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.000 0.0%
demo_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
Input to Output 0.000 0.0%

Breakdown by Type

Power (mW) Percentage
Type Net 0.214 0.2%
Type Gate 9.215 7.3%
Type Core Static 18.535 14.7%
Type Banks Static 3.441 2.7%
Type VPP Static 0.825 0.7%
Type Built-in Blocks 93.768 74.4%