Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Tue Apr 20 18:45:08 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
demo_0/CCC_0/GL0 10.000 100.000
demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain demo_0/CCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE GPIO_0_M2F 8.338 14.587 14.587 WORST
Path 2 demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE USB_ULPI_DATA[7] 8.042 14.291 14.291 WORST
Path 3 demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE USB_ULPI_DATA[3] 8.029 14.278 14.278 WORST
Path 4 demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE USB_ULPI_DATA[2] 8.011 14.260 14.260 WORST
Path 5 demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE USB_ULPI_DATA[4] 7.977 14.226 14.226 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: GPIO_0_M2F
data required time N/C
data arrival time - 14.587
slack N/C
Data arrival time calculation
demo_0/CCC_0/GL0 0.000 0.000
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
demo_0/CCC_0/GL0_INST:An net demo_0/CCC_0/GL0_net + 0.461 4.320 r
demo_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 1 f
demo_0/CCC_0/GL0_INST/U0_RGB1:An net demo_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.603 5.101 f
demo_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 5.417 1 r
demo_0/demo_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net demo_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 5.824 r
demo_0/demo_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 6.033 1 r
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net demo_0/demo_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 6.249 r
demo_0/demo_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:I2C1_SDA_MGPIO0A_H2F_B cell ADLIB:MSS_075_IP + 1.453 7.702 1 f
GPIO_0_M2F_obuf/U0/U_IOOUTFF:A net GPIO_0_M2F_c + 3.445 11.147 f
GPIO_0_M2F_obuf/U0/U_IOOUTFF:Y cell ADLIB:IOOUTFF_BYPASS + 0.330 11.477 1 f
GPIO_0_M2F_obuf/U0/U_IOPAD:D net GPIO_0_M2F_obuf/U0/DOUT + 0.408 11.885 f
GPIO_0_M2F_obuf/U0/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.702 14.587 0 f
GPIO_0_M2F net GPIO_0_M2F + 0.000 14.587 f
data arrival time 14.587
Data required time calculation
demo_0/CCC_0/GL0 N/C N/C
demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.859 N/C
GPIO_0_M2F N/C f
Operating Conditions WORST

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain demo_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets