@W: BN544 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":8:0:8:0|create_generated_clock with both -multiply_by and -divide_by not supported for this target technology
@W: BN132 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance demo_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance demo_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance demo_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance demo_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance demo_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance demo_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance demo_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance demo_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance demo_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance demo_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance demo_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance demo_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance demo_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance demo_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance demo_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance demo_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\igloo2_task_feb_2021\sf2\dg0476_sf2_usb_otg\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance demo_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@W: MT688 :"c:/igloo2_task_feb_2021/sf2/dg0476_sf2_usb_otg/libero_project/designer/top/synthesis.fdc":8:0:8:0|No path from master pin (-source) to source of clock demo_0/CCC_0/GL0 due to black box demo_0.CCC_0.CCC_INST 
@W: MF511 |Found issues with constraints. Please check constraint checker report "C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\synthesis\top_cck.rpt" .
