set_device -family {SmartFusion2} -die {M2S090TS} -speed {-1}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\CCC_0\demo_CCC_0_FCCC.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\FABOSC_0\demo_FABOSC_0_OSC.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo_MSS\demo_MSS.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\demo.v}
read_verilog -mode system_verilog {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\top\top.v}
set_top_level {top}
read_sdc -component {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\CCC_0\demo_CCC_0_FCCC.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo\FABOSC_0\demo_FABOSC_0_OSC.sdc}
read_sdc -component {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\component\work\demo_MSS\demo_MSS.sdc}
derive_constraints
write_sdc {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\constraint\top_derived_constraints.sdc}
write_pdc {C:\igloo2_task_feb_2021\SF2\DG0476_SF2_USB_OTG\Libero_Project\constraint\fp\top_derived_constraints.pdc}
