Project Settings Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S150TS Implementation Name synthesis Top Module top Retiming 0 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 53 33 0 - 00m:05s - 22-04-2021 3.42.41 PM (premap) Complete 33 28 0 0m:01s 0m:01s 172MB 22-04-2021 3.42.45 PM (fpga_mapper) Complete 72 13 0 0m:04s 0m:04s 174MB 22-04-2021 3.42.49 PM Multi-srs Generator Complete 00m:01s 22-04-2021 3.42.43 PM Area Summary Carry Cells 27 Sequential Cells 199 DSP Blocks (dsp_used) 0 I/O Cells 98 Global Clock Buffers 11 LUTs (total_luts) 138 Timing Summary Clock Name Req Freq Est Freq Slack CLK0_PAD 50.0 MHz NA NA FCCC_0/GL0 62.5 MHz NA NA FCCC_0/GL1 62.5 MHz NA NA FCCC_1/GL0 125.0 MHz NA NA SB_sb_0/CCC_0/GL0 100.0 MHz 390.9 MHz 7.442 SB_sb_0/CCC_0/GL3 125.0 MHz NA NA SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 502.7 MHz 18.011 SB_sb_0/SB_sb_MSS_0/CLK_CONFIG_APB 20.0 MHz 113.8 MHz 20.794 SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA NA SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA NA top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz NA NA System 100.0 MHz NA NA Optimizations Summary Combined Clock Conversion 3 / 4