@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\work\sb_sb\fabosc_0\sb_sb_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC (in view: work.SB_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.SB_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\work\sb_sb\fabosc_0\sb_sb_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F (in view: work.SB_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.SB_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\work\sb_sb\fabosc_0\sb_sb_fabosc_0_osc.v":15:7:15:24|Tristate driver RCOSC_25_50MHZ_CCC (in view: work.SB_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.SB_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\work\sb_sb\fabosc_0\sb_sb_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC (in view: work.SB_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.SB_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: MO111 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\work\sb_sb\fabosc_0\sb_sb_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F (in view: work.SB_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.SB_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=236 on top level netlist top 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file C:\tcl_update\sf2\dg0472\472_v4\Libero_Project\synthesis\top.sap.
@N: MO225 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required.
@N: MO225 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|There are no possible illegal states for state machine sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required.
