@W: BN132 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance SB_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance SB_sb_0.CORERESETP_0.sdif2_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance SB_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance SB_sb_0.CORERESETP_0.sdif2_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing instance SB_sb_0.CORERESETP_0.SDIF_READY_int because it is equivalent to instance SB_sb_0.CORERESETP_0.sm0_state[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT246 :"c:\tcl_update\sf2\dg0472\472_v4\libero_project\component\work\sb_sb\ccc_0\sb_sb_ccc_0_fccc.v":23:36:23:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on net SERDES_IF_0.REFCLK1_OUT.
@W: MT447 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":19:0:19:0|Timing constraint (from [get_cells { SB_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { SB_sb_0.CORERESETP_0.sm0_areset_n_rcosc SB_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { SB_sb_0.CORERESETP_0.MSS_HPMS_READY_int SB_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { SB_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":21:0:21:0|Timing constraint (through [get_nets { SB_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n SB_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":22:0:22:0|Timing constraint (to [get_cells { SB_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] SB_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 SB_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":24:0:24:0|Timing constraint (through [get_pins { SB_sb_0.SB_sb_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (through [get_pins { SB_sb_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"c:/tcl_update/sf2/dg0472/472_v4/libero_project/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (through [get_nets { SB_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL SB_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { SB_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* SB_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
