Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Thu Apr 22 15:47:43 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S150TS
Package: 1152 FC
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 791.819 100.0%
Static Power 553.220 69.9%
Dynamic Power 238.599 30.1%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 209.468 1.200 174.556
Rail VDDI 1.5 494.549 1.500 329.700
Rail VDDI 2.5 13.260 2.500 5.304
Rail CCC_NE0_PLL_VDDA 9.000 3.300 2.727
Rail CCC_SE1_PLL_VDDA 9.000 3.300 2.727
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038
Rail CCC_SE0_PLL_VDDA 9.000 3.300 2.727
Rail SERDES_3_L23_VDDAPLL 3.125 2.500 1.250
Rail SERDES_3_L23_VDDAIO 26.092 1.200 21.744

Breakdown by Clock

Power (mW) Percentage
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (clocks) 0.340 0.2%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (register outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (primary inputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (combinational outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL1 (set/reset nets) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 0.336 0.2%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.000 0.0%
FCCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 137.680 92.4%
SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.112 0.1%
SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.196 0.1%
SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
CLK0_PAD (clocks) 1.943 1.3%
CLK0_PAD (register outputs) 0.001 0.0%
CLK0_PAD (primary inputs) 0.000 0.0%
CLK0_PAD (combinational outputs) 0.000 0.0%
CLK0_PAD (set/reset nets) 0.000 0.0%
SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.522 0.4%
SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.081 0.1%
SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.089 0.1%
SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (clocks) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (register outputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (primary inputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (combinational outputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (set/reset nets) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OUT (clocks) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OUT (register outputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OUT (primary inputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OUT (combinational outputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OUT (set/reset nets) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (clocks) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (register outputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (primary inputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (combinational outputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/SPI_0_CLK_PAD/U_IOPAD:PAD (set/reset nets) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (clocks) 5.368 3.6%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (register outputs) 0.276 0.2%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (combinational outputs) 0.266 0.2%
SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (clocks) 0.666 0.4%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.000 0.0%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.000 0.0%
FCCC_1/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
REFCLK1_P (clocks) 0.000 0.0%
REFCLK1_P (register outputs) 0.000 0.0%
REFCLK1_P (primary inputs) 0.000 0.0%
REFCLK1_P (combinational outputs) 0.000 0.0%
REFCLK1_P (set/reset nets) 0.000 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (clocks) 0.106 0.1%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (register outputs) 0.002 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (primary inputs) 0.000 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (combinational outputs) 0.815 0.5%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] (set/reset nets) 0.000 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (clocks) 0.109 0.1%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (register outputs) 0.004 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (primary inputs) 0.000 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (combinational outputs) 0.000 0.0%
SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] (set/reset nets) 0.000 0.0%
Input to Output 0.039 0.0%

Breakdown by Type

Power (mW) Percentage
Type Net 2.489 0.3%
Type Gate 31.003 3.9%
Type I/O 519.765 65.6%
Type Core Static 32.949 4.2%
Type Banks Static 2.410 0.3%
Type VPP Static 0.825 0.1%
Type Built-in Blocks 168.427 21.3%
Type SERDES 33.951 4.3%