SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Thu Apr 22 15:47:21 2021
| Design | top |
| Family | SmartFusion2 |
| Die | M2S150TS |
| Package | 1152 FC |
| Temperature Range | 0 - 85 C |
| Voltage Range | 1.14 - 1.26 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST |
| Scenario for Timing Analysis | timing_analysis |
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| CLK0_PAD | 20.000 | 50.000 | ||
| FCCC_0/GL0 | 16.000 | 62.500 | 5.446 | WORST |
| FCCC_0/GL1 | 16.000 | 62.500 | 5.177 | WORST |
| FCCC_1/GL0 | 8.000 | 125.000 | ||
| SB_sb_0/CCC_0/GL0 | 10.000 | 100.000 | 6.338 | WORST |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 | 50.000 | 8.241 | WORST |
| SB_sb_0/SB_sb_MSS_0/CLK_CONFIG_APB | 50.000 | 20.000 | 3.247 | BEST |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF | N/A | N/A | ||
| SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] | 8.000 | 125.000 | ||
| SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 8.000 | 125.000 | 10.913 | WORST |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin SB_sb_0/CCC_0/CLK0_PAD_INST/U_IOPAD:PAD
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/GL0_INST/U0_RGB1:An
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | 6.381 | 5.446 | 6.381 | 11.827 | 0.653 | WORST |
| Path 2 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[8] | 6.317 | 5.642 | 6.317 | 11.959 | 0.521 | WORST |
| Path 3 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[9] | 6.370 | 5.664 | 6.370 | 12.034 | 0.446 | WORST |
| Path 4 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[1] | 6.214 | 5.664 | 6.214 | 11.878 | 0.602 | WORST |
| Path 5 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] | 6.201 | 5.668 | 6.201 | 11.869 | 0.611 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | ||||||||
| To: SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | ||||||||
| data required time | 11.827 | |||||||
| data arrival time | - | 6.381 | ||||||
| slack | 5.446 | |||||||
| Data arrival time calculation | ||||||||
| SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] | 0.000 | 0.000 | ||||||
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | Clock source | + | 0.000 | 0.000 | r | |||
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[34] | cell | ADLIB:SERDESIF_120_IP | + | 0.945 | 0.945 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_175:A | net | SERDES_IF_0_EPCS_3_RX_DATA[4] | + | 5.029 | 5.974 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_175:IPA | cell | ADLIB:IP_INTERFACE | + | 0.194 | 6.168 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[4] | + | 0.213 | 6.381 | r | ||
| data arrival time | 6.381 | |||||||
| Data required time calculation | ||||||||
| FCCC_0/GL0 | Clock Constraint | 8.000 | 8.000 | |||||
| FCCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 8.000 | r | |||
| Clock generation | + | 2.348 | 10.348 | |||||
| FCCC_0/GL0_INST:An | net | FCCC_0/GL0_net | + | 0.554 | 10.902 | r | ||
| FCCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 11.045 | 1 | f | |
| FCCC_0/GL0_INST/U0_RGB1:An | net | FCCC_0/GL0_INST/U0_YWn_GEast | + | 0.594 | 11.639 | f | ||
| FCCC_0/GL0_INST/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.316 | 11.955 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_164:A | net | FCCC_0/GL0_INST/U0_RGB1_YR | + | 0.449 | 12.404 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_164:IPA | cell | ADLIB:IP_INTERFACE | + | 0.194 | 12.598 | 0 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RX_CLKPF | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/RX_CLKPF_net | + | 0.202 | 12.800 | r | ||
| clock-to-clock uncertainty | - | 0.320 | 12.480 | |||||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | Library setup time | ADLIB:MSS_120_IP | - | 0.653 | 11.827 | |||
| data required time | 11.827 | |||||||
| Operating Conditions | WORST |
Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin FCCC_0/GL1_INST/U0_RGB1:An
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | 6.381 | 5.177 | 6.381 | 11.558 | 0.966 | WORST |
| Path 2 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[8] | 6.317 | 5.320 | 6.317 | 11.637 | 0.887 | WORST |
| Path 3 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[9] | 6.370 | 5.361 | 6.370 | 11.731 | 0.793 | WORST |
| Path 4 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[1] | 6.214 | 5.396 | 6.214 | 11.610 | 0.914 | WORST |
| Path 5 | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0] | 6.201 | 5.399 | 6.201 | 11.600 | 0.924 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | ||||||||
| To: SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | ||||||||
| data required time | 11.558 | |||||||
| data arrival time | - | 6.381 | ||||||
| slack | 5.177 | |||||||
| Data arrival time calculation | ||||||||
| SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] | 0.000 | 0.000 | ||||||
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1] | Clock source | + | 0.000 | 0.000 | r | |||
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXDATA[34] | cell | ADLIB:SERDESIF_120_IP | + | 0.945 | 0.945 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_175:A | net | SERDES_IF_0_EPCS_3_RX_DATA[4] | + | 5.029 | 5.974 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_175:IPA | cell | ADLIB:IP_INTERFACE | + | 0.194 | 6.168 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/RCGF_net[4] | + | 0.213 | 6.381 | r | ||
| data arrival time | 6.381 | |||||||
| Data required time calculation | ||||||||
| FCCC_0/GL1 | Clock Constraint | 8.000 | 8.000 | |||||
| FCCC_0/CCC_INST/INST_CCC_IP:GL1 | Clock source | + | 0.000 | 8.000 | r | |||
| Clock generation | + | 2.381 | 10.381 | |||||
| FCCC_0/GL1_INST:An | net | FCCC_0/GL1_net | + | 0.559 | 10.940 | r | ||
| FCCC_0/GL1_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 11.083 | 1 | f | |
| FCCC_0/GL1_INST/U0_RGB1:An | net | FCCC_0/GL1_INST/U0_YWn_GEast | + | 0.597 | 11.680 | f | ||
| FCCC_0/GL1_INST/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.316 | 11.996 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_163:A | net | FCCC_0/GL1_INST/U0_RGB1_YR | + | 0.454 | 12.450 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_163:IPA | cell | ADLIB:IP_INTERFACE | + | 0.194 | 12.644 | 0 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:TX_CLKPF | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/TX_CLKPF_net | + | 0.200 | 12.844 | r | ||
| clock-to-clock uncertainty | - | 0.320 | 12.524 | |||||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4] | Library setup time | ADLIB:MSS_120_IP | - | 0.966 | 11.558 | |||
| data required time | 11.558 | |||||||
| Operating Conditions | WORST |
Info: The maximum frequency of this clock domain is limited by the period of pin SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/CORERESETP_0/sdif2_spll_lock_q2:CLK | SB_sb_0/CORERESETP_0/SDIF3_PHY_RESET_N_int:EN | 2.302 | 7.337 | 8.107 | 15.444 | 0.308 | 2.663 | WORST |
| Path 2 | SB_sb_0/CORERESETP_0/CONFIG1_DONE_clk_base:CLK | SB_sb_0/CORERESETP_0/SDIF3_PHY_RESET_N_int:EN | 2.262 | 7.377 | 8.067 | 15.444 | 0.308 | 2.623 | WORST |
| Path 3 | SB_sb_0/CORERESETP_0/ddr_settled_clk_base:CLK | SB_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN | 1.919 | 7.720 | 7.719 | 15.439 | 0.308 | 2.280 | WORST |
| Path 4 | SB_sb_0/CORERESETP_0/release_sdif3_core_clk_base:CLK | SB_sb_0/CORERESETP_0/SDIF_RELEASED_int:EN | 1.905 | 7.734 | 7.705 | 15.439 | 0.308 | 2.266 | WORST |
| Path 5 | SB_sb_0/CORERESETP_0/sm0_state[3]:CLK | SB_sb_0/CORERESETP_0/count_ddr_enable:EN | 1.894 | 7.769 | 7.699 | 15.468 | 0.308 | 2.231 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/CORERESETP_0/sdif2_spll_lock_q2:CLK | ||||||||
| To: SB_sb_0/CORERESETP_0/SDIF3_PHY_RESET_N_int:EN | ||||||||
| data required time | 15.444 | |||||||
| data arrival time | - | 8.107 | ||||||
| slack | 7.337 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.610 | 3.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 4.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 4.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.605 | 4.903 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL | cell | ADLIB:RGB | + | 0.317 | 5.220 | 23 | r | |
| SB_sb_0/CORERESETP_0/sdif2_spll_lock_q2:CLK | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 | + | 0.585 | 5.805 | r | ||
| SB_sb_0/CORERESETP_0/sdif2_spll_lock_q2:Q | cell | ADLIB:SLE | + | 0.108 | 5.913 | 3 | f | |
| SB_sb_0/CORERESETP_0/next_sdif3_state9_i_0:B | net | SB_sb_0/CORERESETP_0/next_sm0_state18 | + | 0.368 | 6.281 | f | ||
| SB_sb_0/CORERESETP_0/next_sdif3_state9_i_0:Y | cell | ADLIB:CFG2 | + | 0.147 | 6.428 | 3 | r | |
| SB_sb_0/CORERESETP_0/un1_next_sdif3_core_reset_n_0_sqmuxa_i_i_a3:C | net | SB_sb_0/CORERESETP_0/N_234_i | + | 0.524 | 6.952 | r | ||
| SB_sb_0/CORERESETP_0/un1_next_sdif3_core_reset_n_0_sqmuxa_i_i_a3:Y | cell | ADLIB:CFG3 | + | 0.100 | 7.052 | 1 | f | |
| SB_sb_0/CORERESETP_0/SDIF3_PHY_RESET_N_int:EN | net | SB_sb_0/CORERESETP_0/next_sdif3_phy_reset_n_0_sqmuxa | + | 1.055 | 8.107 | f | ||
| data arrival time | 8.107 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | Clock Constraint | 10.000 | 10.000 | |||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 10.000 | r | |||
| Clock generation | + | 3.610 | 13.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 14.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 14.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.606 | 14.904 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.317 | 15.221 | 9 | r | |
| SB_sb_0/CORERESETP_0/SDIF3_PHY_RESET_N_int:CLK | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.531 | 15.752 | r | ||
| SB_sb_0/CORERESETP_0/SDIF3_PHY_RESET_N_int:EN | Library setup time | ADLIB:SLE | - | 0.308 | 15.444 | |||
| data required time | 15.444 | |||||||
| Operating Conditions | WORST |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | GPIO_6_M2F | 9.406 | 15.588 | 15.588 | WORST | ||
| Path 2 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | GPIO_4_M2F | 9.333 | 15.515 | 15.515 | WORST | ||
| Path 3 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | GPIO_7_M2F | 9.283 | 15.465 | 15.465 | WORST | ||
| Path 4 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | GPIO_5_M2F | 9.265 | 15.447 | 15.447 | WORST | ||
| Path 5 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | GPIO_0_M2F | 9.085 | 15.267 | 15.267 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | ||||||||
| To: GPIO_6_M2F | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 15.588 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.610 | 3.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 4.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 4.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.601 | 4.899 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.316 | 5.215 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_YR | + | 0.448 | 5.663 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB | cell | ADLIB:IP_INTERFACE | + | 0.209 | 5.872 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/CLK_BASE_net | + | 0.310 | 6.182 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_MGPIO6A_H2F_B | cell | ADLIB:MSS_120_IP | + | 0.844 | 7.026 | 1 | f | |
| GPIO_6_M2F_obuf/U0/U_IOOUTFF:A | net | GPIO_6_M2F_c | + | 5.197 | 12.223 | f | ||
| GPIO_6_M2F_obuf/U0/U_IOOUTFF:Y | cell | ADLIB:IOOUTFF_BYPASS | + | 0.330 | 12.553 | 1 | f | |
| GPIO_6_M2F_obuf/U0/U_IOPAD:D | net | GPIO_6_M2F_obuf/U0/DOUT | + | 0.080 | 12.633 | f | ||
| GPIO_6_M2F_obuf/U0/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.955 | 15.588 | 0 | f | |
| GPIO_6_M2F | net | GPIO_6_M2F | + | 0.000 | 15.588 | f | ||
| data arrival time | 15.588 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | N/C | N/C | ||||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 3.610 | N/C | |||||
| GPIO_6_M2F | N/C | f | ||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SB_sb_0/CORERESETP_0/sdif3_areset_n_clk_base:ALn | 3.289 | 6.338 | 9.051 | 15.389 | 0.353 | 3.662 | 0.020 | WORST |
| Path 2 | SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SB_sb_0/CORERESETP_0/sdif3_areset_n_q1:ALn | 3.245 | 6.387 | 9.007 | 15.394 | 0.353 | 3.613 | 0.015 | WORST |
| Path 3 | SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SB_sb_0/CORERESETP_0/sm0_areset_n_q1:ALn | 3.245 | 6.395 | 9.007 | 15.402 | 0.353 | 3.605 | 0.007 | WORST |
| Path 4 | SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | SB_sb_0/CORERESETP_0/sm0_areset_n_clk_base:ALn | 3.245 | 6.397 | 9.007 | 15.404 | 0.353 | 3.603 | 0.005 | WORST |
| Path 5 | SB_sb_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | SB_sb_0/CORERESETP_0/CONFIG2_DONE_clk_base:ALn | 2.677 | 6.972 | 8.451 | 15.423 | 0.353 | 3.028 | -0.002 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | ||||||||
| To: SB_sb_0/CORERESETP_0/sdif3_areset_n_clk_base:ALn | ||||||||
| data required time | 15.389 | |||||||
| data arrival time | - | 9.051 | ||||||
| slack | 6.338 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.610 | 3.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 4.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 4.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.606 | 4.904 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.317 | 5.221 | 9 | r | |
| SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.541 | 5.762 | r | ||
| SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int:Q | cell | ADLIB:SLE | + | 0.087 | 5.849 | 1 | r | |
| SB_sb_0/CORERESETP_0/sdif0_areset_n:B | net | SB_sb_0/CORERESETP_0/MSS_HPMS_READY_int_Z | + | 0.307 | 6.156 | r | ||
| SB_sb_0/CORERESETP_0/sdif0_areset_n:Y | cell | ADLIB:CFG2 | + | 0.074 | 6.230 | 1 | r | |
| SB_sb_0/CORERESETP_0/sdif0_areset_n_RNI5S31:An | net | SB_sb_0/CORERESETP_0/sm0_areset_n | + | 0.945 | 7.175 | f | ||
| SB_sb_0/CORERESETP_0/sdif0_areset_n_RNI5S31:YEn | cell | ADLIB:GBM | + | 0.357 | 7.532 | 2 | f | |
| SB_sb_0/CORERESETP_0/sdif0_areset_n_RNI5S31/U0_RGB1:An | net | SB_sb_0/CORERESETP_0/sdif0_areset_n_RNI5S31/U0_YWn_GEast | + | 0.603 | 8.135 | f | ||
| SB_sb_0/CORERESETP_0/sdif0_areset_n_RNI5S31/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 8.452 | 11 | r | |
| SB_sb_0/CORERESETP_0/sdif3_areset_n_clk_base:ALn | net | SB_sb_0/CORERESETP_0/sm0_areset_n_arst | + | 0.599 | 9.051 | r | ||
| data arrival time | 9.051 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | Clock Constraint | 10.000 | 10.000 | |||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 10.000 | r | |||
| Clock generation | + | 3.610 | 13.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 14.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 14.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.606 | 14.904 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL | cell | ADLIB:RGB | + | 0.317 | 15.221 | 9 | r | |
| SB_sb_0/CORERESETP_0/sdif3_areset_n_clk_base:CLK | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 | + | 0.521 | 15.742 | r | ||
| SB_sb_0/CORERESETP_0/sdif3_areset_n_clk_base:ALn | Library recovery time | ADLIB:SLE | - | 0.353 | 15.389 | |||
| data required time | 15.389 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/CORERESETP_0/release_sdif2_core:CLK | SB_sb_0/CORERESETP_0/release_sdif2_core_q1:D | 0.837 | 7.025 | 8.492 | 15.517 | 0.254 | WORST |
| Path 2 | SB_sb_0/CORERESETP_0/release_sdif0_core:CLK | SB_sb_0/CORERESETP_0/release_sdif0_core_q1:D | 0.806 | 7.080 | 8.453 | 15.533 | 0.254 | WORST |
| Path 3 | SB_sb_0/CORERESETP_0/ddr_settled:CLK | SB_sb_0/CORERESETP_0/ddr_settled_q1:D | 0.790 | 7.087 | 8.430 | 15.517 | 0.254 | WORST |
| Path 4 | SB_sb_0/CORERESETP_0/release_sdif1_core:CLK | SB_sb_0/CORERESETP_0/release_sdif1_core_q1:D | 0.793 | 7.089 | 8.440 | 15.529 | 0.254 | WORST |
| Path 5 | SB_sb_0/CORERESETP_0/release_sdif3_core:CLK | SB_sb_0/CORERESETP_0/release_sdif3_core_q1:D | 0.781 | 7.127 | 8.402 | 15.529 | 0.254 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/CORERESETP_0/release_sdif2_core:CLK | ||||||||
| To: SB_sb_0/CORERESETP_0/release_sdif2_core_q1:D | ||||||||
| data required time | 15.517 | |||||||
| data arrival time | - | 8.492 | ||||||
| slack | 7.025 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 0.739 | 0.739 | r | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 0.891 | 1 | r | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 4.907 | 5.798 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.357 | 6.155 | 2 | f | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.595 | 6.750 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 7.067 | 26 | r | |
| SB_sb_0/CORERESETP_0/release_sdif2_core:CLK | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.588 | 7.655 | r | ||
| SB_sb_0/CORERESETP_0/release_sdif2_core:Q | cell | ADLIB:SLE | + | 0.087 | 7.742 | 1 | r | |
| SB_sb_0/CORERESETP_0/release_sdif2_core_q1:D | net | SB_sb_0/CORERESETP_0/release_sdif2_core_Z | + | 0.750 | 8.492 | r | ||
| data arrival time | 8.492 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | Clock Constraint | 10.000 | 10.000 | |||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 10.000 | r | |||
| Clock generation | + | 3.610 | 13.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 14.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 14.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.605 | 14.903 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL | cell | ADLIB:RGB | + | 0.317 | 15.220 | 23 | r | |
| SB_sb_0/CORERESETP_0/release_sdif2_core_q1:CLK | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 | + | 0.551 | 15.771 | r | ||
| SB_sb_0/CORERESETP_0/release_sdif2_core_q1:D | Library setup time | ADLIB:SLE | - | 0.254 | 15.517 | |||
| data required time | 15.517 | |||||||
| Operating Conditions | WORST |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/CORERESETP_0/count_sdif3[2]:CLK | SB_sb_0/CORERESETP_0/release_sdif3_core:EN | 2.892 | 16.757 | 10.539 | 27.296 | 0.308 | 3.243 | WORST |
| Path 2 | SB_sb_0/CORERESETP_0/count_sdif3[6]:CLK | SB_sb_0/CORERESETP_0/release_sdif3_core:EN | 2.885 | 16.764 | 10.532 | 27.296 | 0.308 | 3.236 | WORST |
| Path 3 | SB_sb_0/CORERESETP_0/count_ddr[2]:CLK | SB_sb_0/CORERESETP_0/ddr_settled:EN | 2.813 | 16.855 | 10.460 | 27.315 | 0.308 | 3.145 | WORST |
| Path 4 | SB_sb_0/CORERESETP_0/count_sdif3[5]:CLK | SB_sb_0/CORERESETP_0/release_sdif3_core:EN | 2.753 | 16.884 | 10.412 | 27.296 | 0.308 | 3.116 | WORST |
| Path 5 | SB_sb_0/CORERESETP_0/count_sdif3[11]:CLK | SB_sb_0/CORERESETP_0/release_sdif3_core:EN | 2.749 | 16.888 | 10.408 | 27.296 | 0.308 | 3.112 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/CORERESETP_0/count_sdif3[2]:CLK | ||||||||
| To: SB_sb_0/CORERESETP_0/release_sdif3_core:EN | ||||||||
| data required time | 27.296 | |||||||
| data arrival time | - | 10.539 | ||||||
| slack | 16.757 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 0.739 | 0.739 | r | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 0.891 | 1 | r | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 4.907 | 5.798 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.357 | 6.155 | 2 | f | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.595 | 6.750 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 7.067 | 26 | r | |
| SB_sb_0/CORERESETP_0/count_sdif3[2]:CLK | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.580 | 7.647 | r | ||
| SB_sb_0/CORERESETP_0/count_sdif3[2]:Q | cell | ADLIB:SLE | + | 0.108 | 7.755 | 2 | f | |
| SB_sb_0/CORERESETP_0/release_sdif3_core4_1:C | net | SB_sb_0/CORERESETP_0/count_sdif3_Z[2] | + | 0.669 | 8.424 | f | ||
| SB_sb_0/CORERESETP_0/release_sdif3_core4_1:Y | cell | ADLIB:CFG4 | + | 0.287 | 8.711 | 1 | f | |
| SB_sb_0/CORERESETP_0/release_sdif3_core4:C | net | SB_sb_0/CORERESETP_0/release_sdif3_core4_1_Z | + | 0.227 | 8.938 | f | ||
| SB_sb_0/CORERESETP_0/release_sdif3_core4:Y | cell | ADLIB:CFG4 | + | 0.209 | 9.147 | 1 | f | |
| SB_sb_0/CORERESETP_0/release_sdif3_core:EN | net | SB_sb_0/CORERESETP_0/release_sdif3_core4_Z | + | 1.392 | 10.539 | f | ||
| data arrival time | 10.539 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 0.739 | 20.739 | r | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 20.891 | 1 | r | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 4.907 | 25.798 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.357 | 26.155 | 2 | f | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.595 | 26.750 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 27.067 | 26 | r | |
| SB_sb_0/CORERESETP_0/release_sdif3_core:CLK | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.537 | 27.604 | r | ||
| SB_sb_0/CORERESETP_0/release_sdif3_core:EN | Library setup time | ADLIB:SLE | - | 0.308 | 27.296 | |||
| data required time | 27.296 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | SB_sb_0/CORERESETP_0/count_sdif3[8]:ALn | 3.360 | 16.262 | 11.015 | 27.277 | 0.353 | 3.738 | 0.025 | WORST |
| Path 2 | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | SB_sb_0/CORERESETP_0/count_sdif3[6]:ALn | 3.360 | 16.262 | 11.015 | 27.277 | 0.353 | 3.738 | 0.025 | WORST |
| Path 3 | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | SB_sb_0/CORERESETP_0/count_sdif3[4]:ALn | 3.360 | 16.262 | 11.015 | 27.277 | 0.353 | 3.738 | 0.025 | WORST |
| Path 4 | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | SB_sb_0/CORERESETP_0/count_sdif3[2]:ALn | 3.360 | 16.262 | 11.015 | 27.277 | 0.353 | 3.738 | 0.025 | WORST |
| Path 5 | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | SB_sb_0/CORERESETP_0/count_sdif3[10]:ALn | 3.360 | 16.262 | 11.015 | 27.277 | 0.353 | 3.738 | 0.025 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | ||||||||
| To: SB_sb_0/CORERESETP_0/count_sdif3[8]:ALn | ||||||||
| data required time | 27.277 | |||||||
| data arrival time | - | 11.015 | ||||||
| slack | 16.262 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 0.739 | 0.739 | r | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 0.891 | 1 | r | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 4.907 | 5.798 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.357 | 6.155 | 2 | f | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.595 | 6.750 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 7.067 | 26 | r | |
| SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.588 | 7.655 | r | ||
| SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc:Q | cell | ADLIB:SLE | + | 0.087 | 7.742 | 1 | r | |
| SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI1OV3:An | net | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_0 | + | 1.408 | 9.150 | f | ||
| SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI1OV3:YEn | cell | ADLIB:GBM | + | 0.357 | 9.507 | 1 | f | |
| SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI1OV3/U0_RGB1:An | net | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI1OV3/U0_YWn_GEast | + | 0.597 | 10.104 | f | ||
| SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_RNI1OV3/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 10.421 | 14 | r | |
| SB_sb_0/CORERESETP_0/count_sdif3[8]:ALn | net | SB_sb_0/CORERESETP_0/sdif3_areset_n_rcosc_Z | + | 0.594 | 11.015 | r | ||
| data arrival time | 11.015 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 20.000 | 20.000 | |||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 20.000 | r | |||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 0.739 | 20.739 | r | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 20.891 | 1 | r | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 4.907 | 25.798 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.357 | 26.155 | 2 | f | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.595 | 26.750 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YL | cell | ADLIB:RGB | + | 0.317 | 27.067 | 26 | r | |
| SB_sb_0/CORERESETP_0/count_sdif3[8]:CLK | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbl_net_1 | + | 0.563 | 27.630 | r | ||
| SB_sb_0/CORERESETP_0/count_sdif3[8]:ALn | Library recovery time | ADLIB:SLE | - | 0.353 | 27.277 | |||
| data required time | 27.277 | |||||||
| Operating Conditions | WORST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/CORERESETP_0/count_ddr_enable:CLK | SB_sb_0/CORERESETP_0/count_ddr_enable_q1:D | 3.326 | 8.241 | 9.119 | 17.360 | 0.254 | WORST |
| Path 2 | SB_sb_0/CORERESETP_0/count_sdif3_enable:CLK | SB_sb_0/CORERESETP_0/count_sdif3_enable_q1:D | 2.263 | 9.338 | 8.031 | 17.369 | 0.254 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/CORERESETP_0/count_ddr_enable:CLK | ||||||||
| To: SB_sb_0/CORERESETP_0/count_ddr_enable_q1:D | ||||||||
| data required time | 17.360 | |||||||
| data arrival time | - | 9.119 | ||||||
| slack | 8.241 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| SB_sb_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.610 | 3.610 | |||||
| SB_sb_0/CCC_0/GL0_INST:An | net | SB_sb_0/CCC_0/GL0_net | + | 0.545 | 4.155 | r | ||
| SB_sb_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 4.298 | 6 | f | |
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | SB_sb_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.605 | 4.903 | f | ||
| SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YL | cell | ADLIB:RGB | + | 0.317 | 5.220 | 23 | r | |
| SB_sb_0/CORERESETP_0/count_ddr_enable:CLK | net | SB_sb_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbl_net_1 | + | 0.573 | 5.793 | r | ||
| SB_sb_0/CORERESETP_0/count_ddr_enable:Q | cell | ADLIB:SLE | + | 0.087 | 5.880 | 1 | r | |
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1A_TEST:A | net | SB_sb_0/CORERESETP_0/count_ddr_enable_Z | + | 0.452 | 6.332 | r | ||
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1A_TEST:Y | cell | ADLIB:CFG1A_TEST | + | 0.074 | 6.406 | 1 | r | |
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST1:A | net | mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1A_TEST_net | + | 0.232 | 6.638 | r | ||
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST1:Y | cell | ADLIB:CFG1C_TEST | + | 0.202 | 6.840 | 1 | r | |
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST0:A | net | mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net1 | + | 0.232 | 7.072 | r | ||
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST0:Y | cell | ADLIB:CFG1C_TEST | + | 0.202 | 7.274 | 1 | r | |
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:A | net | mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net0 | + | 0.433 | 7.707 | r | ||
| mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:Y | cell | ADLIB:CFG1C_TEST | + | 0.202 | 7.909 | 1 | r | |
| SB_sb_0/CORERESETP_0/count_ddr_enable_q1:D | net | mdr_SB_sb_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net | + | 1.210 | 9.119 | r | ||
| data arrival time | 9.119 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 10.000 | 10.000 | |||||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 10.000 | r | |||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKOUT | + | 0.739 | 10.739 | r | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.152 | 10.891 | 1 | r | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | SB_sb_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 4.907 | 15.798 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.357 | 16.155 | 2 | f | |
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.595 | 16.750 | f | ||
| SB_sb_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YL | cell | ADLIB:RGB | + | 0.317 | 17.067 | 20 | r | |
| SB_sb_0/CORERESETP_0/count_ddr_enable_q1:CLK | net | SB_sb_0/FABOSC_0_RCOSC_25_50MHZ_O2F | + | 0.547 | 17.614 | r | ||
| SB_sb_0/CORERESETP_0/count_ddr_enable_q1:D | Library setup time | ADLIB:SLE | - | 0.254 | 17.360 | |||
| data required time | 17.360 | |||||||
| Operating Conditions | WORST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB | SB_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | 1.297 | 3.247 | 1.297 | 4.544 | 0.245 | -3.247 | BEST |
| Path 2 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB | SB_sb_0/CORECONFIGP_0/state[0]:D | 0.940 | 3.643 | 0.940 | 4.583 | 0.201 | -3.643 | BEST |
| Path 3 | SB_sb_0/CORECONFIGP_0/psel:CLK | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PSEL | 5.191 | 17.931 | 12.320 | 30.251 | 1.966 | 14.138 | WORST |
| Path 4 | SB_sb_0/CORECONFIGP_0/SDIF3_PENABLE:CLK | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:APB_PENABLE | 4.650 | 19.973 | 11.779 | 31.752 | 0.465 | 10.054 | WORST |
| Path 5 | SB_sb_0/CORECONFIGP_0/psel:CLK | SB_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | 3.284 | 21.216 | 10.413 | 31.629 | 0.308 | 7.568 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB | ||||||||
| To: SB_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | ||||||||
| data required time | 4.544 | |||||||
| data arrival time | - | 1.297 | ||||||
| slack | 3.247 | |||||||
| Data arrival time calculation | ||||||||
| SB_sb_0/SB_sb_MSS_0/CLK_CONFIG_APB | 0.000 | 0.000 | ||||||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB | Clock source | + | 0.000 | 0.000 | r | |||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE | cell | ADLIB:MSS_120_IP | + | 0.215 | 0.215 | 2 | r | |
| SB_sb_0/CORECONFIGP_0/next_state4:A | net | SB_sb_0/SB_sb_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE | + | 0.484 | 0.699 | r | ||
| SB_sb_0/CORECONFIGP_0/next_state4:Y | cell | ADLIB:CFG2 | + | 0.098 | 0.797 | 2 | f | |
| SB_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_1:C | net | SB_sb_0/CORECONFIGP_0/next_state4_Z | + | 0.068 | 0.865 | f | ||
| SB_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_1:Y | cell | ADLIB:CFG4 | + | 0.060 | 0.925 | 1 | f | |
| SB_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | net | SB_sb_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_1_Z | + | 0.372 | 1.297 | f | ||
| data arrival time | 1.297 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/SB_sb_MSS_0/CLK_CONFIG_APB | Max Delay Constraint | 0.000 | 0.000 | |||||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB | Clock source | + | 0.000 | 0.000 | r | |||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST_RNI9KE2:An | net | SB_sb_0/SB_sb_MSS_0/CLK_CONFIG_APB | + | 3.542 | 3.542 | f | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST_RNI9KE2:YEn | cell | ADLIB:GBM | + | 0.245 | 3.787 | 7 | f | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST_RNI9KE2/U0_RGB1_RGB2:An | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST_RNI9KE2/U0_YWn_GEast | + | 0.421 | 4.208 | f | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST_RNI9KE2/U0_RGB1_RGB2:YR | cell | ADLIB:RGB | + | 0.218 | 4.426 | 52 | r | |
| SB_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST_RNI9KE2/U0_RGB1_RGB2_rgbr_net_1 | + | 0.363 | 4.789 | r | ||
| SB_sb_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN | Library setup time | ADLIB:SLE | - | 0.245 | 4.544 | |||
| data required time | 4.544 | |||||||
| Operating Conditions | BEST |
No Path
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | External Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | PAD | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF | 4.466 | 4.466 | -0.503 | 3.963 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: PAD | ||||||||
| To: SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 4.466 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| PAD | 0.000 | 0.000 | f | |||||
| BIBUF_0/U0/U_IOPAD:PAD | net | PAD | + | 0.000 | 0.000 | f | ||
| BIBUF_0/U0/U_IOPAD:Y | cell | ADLIB:IOPAD_BI | + | 1.403 | 1.403 | 1 | f | |
| BIBUF_0/U0/U_IOINFF:A | net | BIBUF_0/U0/YIN1 | + | 0.893 | 2.296 | f | ||
| BIBUF_0/U0/U_IOINFF:Y | cell | ADLIB:IOINFF_BYPASS | + | 0.142 | 2.438 | 1 | f | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_161:B | net | BIBUF_0_Y | + | 1.582 | 4.020 | f | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_161:IPB | cell | ADLIB:IP_INTERFACE | + | 0.224 | 4.244 | 1 | f | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/MDIF_net | + | 0.222 | 4.466 | f | ||
| data arrival time | 4.466 | |||||||
| Data required time calculation | ||||||||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF | N/C | N/C | ||||||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDCF | Clock source | + | 0.000 | N/C | r | |||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDIF | Library setup time | ADLIB:MSS_120_IP | - | -0.503 | N/C | |||
| Operating Conditions | WORST |
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_RXCLK[1]
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1]
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[21] | 6.855 | 10.913 | 11.670 | 22.583 | 1.417 | WORST |
| Path 2 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[29] | 6.785 | 10.944 | 11.600 | 22.544 | 1.456 | WORST |
| Path 3 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[26] | 6.819 | 10.965 | 11.634 | 22.599 | 1.401 | WORST |
| Path 4 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[24] | 6.756 | 10.997 | 11.571 | 22.568 | 1.432 | WORST |
| Path 5 | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[28] | 6.727 | 11.023 | 11.542 | 22.565 | 1.435 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | ||||||||
| To: SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[21] | ||||||||
| data required time | 22.583 | |||||||
| data arrival time | - | 11.670 | ||||||
| slack | 10.913 | |||||||
| Data arrival time calculation | ||||||||
| FCCC_1/GL0 | 0.000 | 0.000 | ||||||
| FCCC_1/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.304 | 2.304 | |||||
| FCCC_1/GL0_INST:An | net | FCCC_1/GL0_net | + | 0.586 | 2.890 | r | ||
| FCCC_1/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.143 | 3.033 | 1 | f | |
| FCCC_1/GL0_INST/U0_RGB1:An | net | FCCC_1/GL0_INST/U0_YWn_GEast | + | 0.588 | 3.621 | f | ||
| FCCC_1/GL0_INST/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.316 | 3.937 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_162:B | net | FCCC_1/GL0_INST/U0_RGB1_YR | + | 0.445 | 4.382 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_162:IPB | cell | ADLIB:IP_INTERFACE | + | 0.209 | 4.591 | 1 | r | |
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF | net | SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/GTX_CLKPF_net | + | 0.224 | 4.815 | r | ||
| SB_sb_0/SB_sb_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:TCGF[1] | cell | ADLIB:MSS_120_IP | + | 1.561 | 6.376 | 1 | f | |
| SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_200:B | net | SB_sb_0_MAC_TBI_TCGF[1] | + | 4.820 | 11.196 | f | ||
| SERDES_IF_0/SERDESIF_INST/IP_INTERFACE_200:IPB | cell | ADLIB:IP_INTERFACE | + | 0.224 | 11.420 | 1 | f | |
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[21] | net | SERDES_IF_0/SERDESIF_INST/EPCS_TXDATA_net[21] | + | 0.250 | 11.670 | f | ||
| data arrival time | 11.670 | |||||||
| Data required time calculation | ||||||||
| SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | Multicyle Constraint | 24.000 | 24.000 | |||||
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXCLK[1] | Clock source | + | 0.000 | 24.000 | r | |||
| SERDES_IF_0/SERDESIF_INST/INST_SERDESIF_IP:EPCS_TXDATA[21] | Library setup time | ADLIB:SERDESIF_120_IP | - | 1.417 | 22.583 | |||
| data required time | 22.583 | |||||||
| Operating Conditions | WORST |
No Path