#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016
#install: D:\cap\sympify_bug_fix\synplify_L201609M-2_W
#OS: Windows 8 6.2
#Hostname: W764D-ATHULDEEP

# Mon Sep 11 19:35:44 2017

#Implementation: synthesis

Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\generic\smartfusion2.v" (library work)
@I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\cap\sympify_bug_fix\synplify_L201609M-2_W\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR\CCC_0\Adaptive_FIR_CCC_0_FCCC.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR\FABOSC_0\Adaptive_FIR_FABOSC_0_OSC.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS_syn.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR\Adaptive_FIR.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\TPSRAM_0\Adaptive_FIR_top_TPSRAM_0_TPSRAM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\TPSRAM_1\Adaptive_FIR_top_TPSRAM_1_TPSRAM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\TPSRAM_2\Adaptive_FIR_top_TPSRAM_2_TPSRAM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\TPSRAM_3\Adaptive_FIR_top_TPSRAM_3_TPSRAM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\hdl\DATAHANDLE_FSM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\hdl\FILTERCONTROL_FSM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\hdl\LMS_ALGO.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\hdl\LMS_CONTROL_FSM.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac_lib.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v" (library COREFIR_LIB)
@I:"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v":"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\LMS_FIR_TOP_COREFIR_0_coef.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_COREFIR.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\top\COREFIR.v" (library COREFIR_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\LMS_FIR_TOP\LMS_FIR_TOP.v" (library work)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\Adaptive_FIR_top_COREFFT_0_ram_smGen.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\COREFFT_0\twiddle32.v" (library COREFFT_LIB)
@N:CG347 : twiddle32.v(35) | Read a parallel_case directive.
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\mac_lib.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v" (library COREFFT_LIB)
@I::"D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\Adaptive_FIR_top.v" (library work)
Verilog syntax check successful!
Selecting top level module Adaptive_FIR_top
@N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work.

@N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work.

@N:CG364 : Adaptive_FIR_MSS_syn.v(5) | Synthesizing module MSS_010 in library work.

@N:CG364 : Adaptive_FIR_MSS.v(9) | Synthesizing module Adaptive_FIR_MSS in library work.

@N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work.

@N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work.

@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work.

@N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work.

@N:CG364 : Adaptive_FIR_CCC_0_FCCC.v(5) | Synthesizing module Adaptive_FIR_CCC_0_FCCC in library work.

@W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.

@N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB.

	APB_DWIDTH=6'b100000
	IADDR_OPTION=32'b00000000000000000000000000000000
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	MADDR_BITS=6'b010000
	UPR_NIBBLE_POSN=4'b0011
	FAMILY=32'b00000000000000000000000000010011
	SYNC_RESET=32'b00000000000000000000000000000000
	IADDR_NOTINUSE=32'b00000000000000000000000000000000
	IADDR_EXTERNAL=32'b00000000000000000000000000000001
	IADDR_SLOT0=32'b00000000000000000000000000000010
	IADDR_SLOT1=32'b00000000000000000000000000000011
	IADDR_SLOT2=32'b00000000000000000000000000000100
	IADDR_SLOT3=32'b00000000000000000000000000000101
	IADDR_SLOT4=32'b00000000000000000000000000000110
	IADDR_SLOT5=32'b00000000000000000000000000000111
	IADDR_SLOT6=32'b00000000000000000000000000001000
	IADDR_SLOT7=32'b00000000000000000000000000001001
	IADDR_SLOT8=32'b00000000000000000000000000001010
	IADDR_SLOT9=32'b00000000000000000000000000001011
	IADDR_SLOT10=32'b00000000000000000000000000001100
	IADDR_SLOT11=32'b00000000000000000000000000001101
	IADDR_SLOT12=32'b00000000000000000000000000001110
	IADDR_SLOT13=32'b00000000000000000000000000001111
	IADDR_SLOT14=32'b00000000000000000000000000010000
	IADDR_SLOT15=32'b00000000000000000000000000010001
	SL0=16'b0000000000000001
	SL1=16'b0000000000000000
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b0000000000000000
	SC=16'b0000000000000000
	SC_qual=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it.
@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work.

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
	DEVICE_090=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z2

@W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work.

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work.

@N:CG364 : Adaptive_FIR_FABOSC_0_OSC.v(5) | Synthesizing module Adaptive_FIR_FABOSC_0_OSC in library work.

@N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work.

@N:CG364 : Adaptive_FIR.v(9) | Synthesizing module Adaptive_FIR in library work.

@W:CG775 : COREFFT_TOP.v(28) | Found Component Adaptive_FIR_top_COREFFT_0_COREFFT in library COREFFT_LIB
@N:CG364 : COREFFT_TOP.v(28) | Synthesizing module Adaptive_FIR_top_COREFFT_0_COREFFT in library COREFFT_LIB.

	FPGA_FAMILY=32'b00000000000000000000000000010011
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	CFG_ARCH=32'b00000000000000000000000000000001
	DATA_BITS=32'b00000000000000000000000000010010
	TWID_BITS=32'b00000000000000000000000000010010
	FFT_SIZE=32'b00000000000000000000000100000000
	SCALE_ON=32'b00000000000000000000000000000001
	SCALE_SCH=32'b00000000000000000000000011111111
	ORDER=32'b00000000000000000000000000000000
	INVERSE=32'b00000000000000000000000000000000
	SCALE=32'b00000000000000000000000000000000
	POINTS=32'b00000000000000000000000100000000
	WIDTH=32'b00000000000000000000000000010000
	MEMBUF=32'b00000000000000000000000000000001
	SCALE_EXP_ON=32'b00000000000000000000000000000000
	NO_RAM=32'b00000000000000000000000000000000
	LOG2PTS=32'b00000000000000000000000000001000
	LOGLOG2PTS=32'b00000000000000000000000000000011
	FLOGLOG2PTS=32'b00000000000000000000000000000100
	STREAM_DATAO_BITS=32'b00000000000000000000000000010010
	IN_BITS=32'b00000000000000000000000000010000
	OUTP_BITS=32'b00000000000000000000000000010000
   Generated name = Adaptive_FIR_top_COREFFT_0_COREFFT_Z3

@N:CG364 : kit.v(445) | Synthesizing module fft_inpl_slowClock in library COREFFT_LIB.

@N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.

	DELAY=32'b00000000000000000000000000000010
   Generated name = fft_inpl_kitDelay_bit_reg_2s

@W:CG133 : kit.v(194) | Object delayLine_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(194) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(29) | Synthesizing module fft_inpl_kitEdge in library COREFFT_LIB.

	FRONT_EDGE=32'b00000000000000000000000000000000
   Generated name = fft_inpl_kitEdge_0s

@N:CG364 : kit.v(126) | Synthesizing module fft_inpl_counter_w in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000001010
	TC=32'b00000000000000000000000010001001
   Generated name = fft_inpl_counter_w_10_137s

@N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000000101
	TC=32'b00000000000000000000000000000111
   Generated name = fft_inpl_counter_5_7

@N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.

	DELAY=32'b00000000000000000000000000000011
   Generated name = fft_inpl_kitDelay_bit_reg_3s

@W:CG133 : kit.v(194) | Object delayLine_3_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(194) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : fftSm.v(361) | Synthesizing module fft_inpl_rdFFTtimer in library COREFFT_LIB.

	HALFPTS=32'b00000000000000000000000010000000
	LOGPTS=32'b00000000000000000000000000001000
	LOGLOGPTS=32'b00000000000000000000000000000011
	RW_DLY=32'b00000000000000000000000000001010
	MEMBUF=32'b00000000000000000000000000000001
   Generated name = fft_inpl_rdFFTtimer_128s_8_3_10s_1s

@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000001010
	DELAY=32'b00000000000000000000000000000010
   Generated name = fft_inpl_kitDelay_reg_10_2s

@W:CG133 : kit.v(235) | Object delayLine_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000000101
	DELAY=32'b00000000000000000000000000000010
   Generated name = fft_inpl_kitDelay_reg_5_2s

@W:CG133 : kit.v(235) | Object delayLine_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.

	DELAY=32'b00000000000000000000000000000001
   Generated name = fft_inpl_kitDelay_bit_reg_1s

@W:CG133 : kit.v(194) | Object delayLine_1_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(194) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(99) | Synthesizing module fft_inpl_kitCountS in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000000111
	DCVALUE=32'b00000000000000000000000001111111
	BUILD_DC=32'b00000000000000000000000000000000
   Generated name = fft_inpl_kitCountS_7_127s_0s

@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000000111
	DELAY=32'b00000000000000000000000000000010
   Generated name = fft_inpl_kitDelay_reg_7_2s

@W:CG133 : kit.v(235) | Object delayLine_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000000001
	DELAY=32'b00000000000000000000000000001010
   Generated name = fft_inpl_kitDelay_reg_1s_10s

@W:CG133 : kit.v(235) | Object delayLine_10_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000001000
	TC=32'b00000000000000000000000011111111
   Generated name = fft_inpl_counter_8_255s

@N:CG364 : fftSm.v(481) | Synthesizing module fft_inpl_inBuf_ldA in library COREFFT_LIB.

	PTS=32'b00000000000000000000000100000000
	LOGPTS=32'b00000000000000000000000000001000
   Generated name = fft_inpl_inBuf_ldA_256s_8

@W:CG360 : fftSm.v(502) | Removing wire load_over, as there is no assignment to it.
@N:CG364 : fftSm.v(623) | Synthesizing module fft_inpl_inBuf_fftA_pipe in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	LOGLOGPTS=32'b00000000000000000000000000000011
   Generated name = fft_inpl_inBuf_fftA_pipe_8_3

@W:CL265 : fftSm.v(675) | Removing unused bit 6 of mask1_r[6:0]. Either assign all bits or reduce the width of the signal.
@N:CG364 : fftSm.v(695) | Synthesizing module fft_inpl_twid_rA in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	LOGLOGPTS=32'b00000000000000000000000000000011
   Generated name = fft_inpl_twid_rA_8_3

@N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.

	DELAY=32'b00000000000000000000000000000100
   Generated name = fft_inpl_kitDelay_bit_reg_4s

@W:CG133 : kit.v(194) | Object delayLine_4_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(194) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(405) | Synthesizing module fft_inpl_kitSync_ngrst in library COREFFT_LIB.

	PULSE_WIDTH=32'b00000000000000000000000000000001
   Generated name = fft_inpl_kitSync_ngrst_1s

@W:CG133 : kit.v(412) | Object tick2 is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : kit.v(161) | Synthesizing module fft_inpl_bcounter in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000000111
   Generated name = fft_inpl_bcounter_7

@N:CG364 : fftSm.v(739) | Synthesizing module fft_inpl_twid_wA_gen in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	LOGLOGPTS=32'b00000000000000000000000000000011
   Generated name = fft_inpl_twid_wA_gen_8_3

@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000000011
	DELAY=32'b00000000000000000000000000000010
   Generated name = fft_inpl_kitDelay_reg_3_2s

@W:CG133 : kit.v(235) | Object delayLine_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : fftSm.v(532) | Synthesizing module fft_inpl_outBufA in library COREFFT_LIB.

	PTS=32'b00000000000000000000000100000000
	LOGPTS=32'b00000000000000000000000000001000
	MEMBUF=32'b00000000000000000000000000000001
   Generated name = fft_inpl_outBufA_256s_8_1s

@N:CG364 : fftSm.v(29) | Synthesizing module fft_inpl_sm_top in library COREFFT_LIB.

	PTS=32'b00000000000000000000000100000000
	HALFPTS=32'b00000000000000000000000010000000
	LOGPTS=32'b00000000000000000000000000001000
	LOGLOGPTS=32'b00000000000000000000000000000011
	RW_DLY=32'b00000000000000000000000000001010
	MEMBUF=32'b00000000000000000000000000000001
   Generated name = fft_inpl_sm_top_256s_128s_8_3_10s_1s

@W:CL168 : fftSm.v(234) | Removing instance wStage_dly_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : fftSm.v(118) | Removing instance edge_detect_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : fftDp.v(249) | Synthesizing module Adaptive_FIR_top_COREFFT_0_inPlace in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	DWIDTH=32'b00000000000000000000000000100000
	MEMBUF=32'b00000000000000000000000000000001
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
   Generated name = Adaptive_FIR_top_COREFFT_0_inPlace_8_32s_1s_0s_19s

@N:CG364 : fftDp.v(163) | Synthesizing module Adaptive_FIR_top_COREFFT_0_inBuffer in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	DWIDTH=32'b00000000000000000000000000100000
	MEMBUF=32'b00000000000000000000000000000001
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
   Generated name = Adaptive_FIR_top_COREFFT_0_inBuffer_8_32s_1s_0s_19s

@N:CG364 : fftDp.v(36) | Synthesizing module Adaptive_FIR_top_COREFFT_0_wrapRam in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	DWIDTH=32'b00000000000000000000000000100000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	RAM_DEPTH=32'b00000000000000000000000010000000
	SMARTGEN=32'b00000000000000000000000000000001
   Generated name = Adaptive_FIR_top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s

@N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work.

@N:CG364 : Adaptive_FIR_top_COREFFT_0_ram_smGen.v(5) | Synthesizing module Adaptive_FIR_top_COREFFT_0_ram_smGen in library COREFFT_LIB.

@W:CG133 : fftDp.v(267) | Object wA_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : fftDp.v(268) | Object wA_load_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : fftDp.v(270) | Object wEn_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : fftDp.v(270) | Object wEn_odd_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : fftDp.v(270) | Object wEn_even_r is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : kit.v(460) | Synthesizing module fft_inpl_switch in library COREFFT_LIB.

	DWIDTH=32'b00000000000000000000000000100000
   Generated name = fft_inpl_switch_32s

@N:CG364 : kit.v(326) | Synthesizing module fft_inpl_kitRndUp in library COREFFT_LIB.

	WIDTH_OUT=32'b00000000000000000000000000010000
	RND_MODE=32'b00000000000000000000000000000001
   Generated name = fft_inpl_kitRndUp_16s_1s

@N:CG364 : cmplx.v(442) | Synthesizing module fft_inpl_cmplx_rnd in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000010000
	NOPIPE=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	RND=32'b00000000000000000000000000000001
	P_WIDTH=32'b00000000000000000000000000101100
   Generated name = fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s

@N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt in library COREFFT_LIB.

	INWIDTH=32'b00000000000000000000000000010000
	OUTWIDTH=32'b00000000000000000000000000010010
	UNSIGNED=32'b00000000000000000000000000000000
   Generated name = fft_inpl_signExt_16s_18s_0s

@N:CG364 : mac_lib.v(36) | Synthesizing module fft_inpl_mac18x18mx in library COREFFT_LIB.

	WIDTH_A=32'b00000000000000000000000000010000
	WIDTH_B=32'b00000000000000000000000000010000
	BYPASS_REG_A=32'b00000000000000000000000000000000
	BYPASS_REG_B=32'b00000000000000000000000000000000
	BYPASS_REG_P=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	BY_REGA=2'b00
	BY_REGB=2'b00
	BY_REGP=2'b00
	P_WIDTH=32'b00000000000000000000000000101100
   Generated name = fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s

@N:CG364 : smartfusion2.v(567) | Synthesizing module MACC in library work.

@W:CG360 : mac_lib.v(69) | Removing wire sel_cdin, as there is no assignment to it.
@N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt in library COREFFT_LIB.

	INWIDTH=32'b00000000000000000000000000101100
	OUTWIDTH=32'b00000000000000000000000000100001
	UNSIGNED=32'b00000000000000000000000000000000
   Generated name = fft_inpl_signExt_44s_33s_0s

@N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000010000
	MINUS=32'b00000000000000000000000000000001
	NOPIPE=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	P_WIDTH=32'b00000000000000000000000000101100
	SUB=1'b1
	DBG=32'b00000000000000000000000000000000
   Generated name = fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s

@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000010000
	DELAY=32'b00000000000000000000000000000001
   Generated name = fft_inpl_kitDelay_reg_16s_1s

@W:CG133 : kit.v(235) | Object delayLine_1_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000010000
	MINUS=32'b00000000000000000000000000000000
	NOPIPE=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	P_WIDTH=32'b00000000000000000000000000101100
	SUB=1'b0
	DBG=32'b00000000000000000000000000000000
   Generated name = fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s

@N:CG364 : cmplx.v(414) | Synthesizing module fft_inpl_cmplx_18 in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000010000
	NOPIPE=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	P_WIDTH=32'b00000000000000000000000000101100
   Generated name = fft_inpl_cmplx_18_16s_0s_19s_44s

@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000010000
	DELAY=32'b00000000000000000000000000000100
   Generated name = fft_inpl_kitDelay_reg_16s_4s

@W:CG133 : kit.v(235) | Object delayLine_4_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.

	BITWIDTH=32'b00000000000000000000000000000010
	DELAY=32'b00000000000000000000000000000101
   Generated name = fft_inpl_kitDelay_reg_2s_5s

@W:CG133 : kit.v(235) | Object delayLine_5_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(235) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(499) | Synthesizing module fft_inpl_bfly2 in library COREFFT_LIB.

	WIDTH=32'b00000000000000000000000000010000
	TWIDTH=32'b00000000000000000000000000010000
	DWIDTH=32'b00000000000000000000000000100000
	TDWIDTH=32'b00000000000000000000000000100000
	MPIPE=32'b00000000000000000000000000000011
	FPGA_FAMILY=32'b00000000000000000000000000010011
   Generated name = fft_inpl_bfly2_16s_16s_32s_32s_3s_19s

@N:CG364 : twiddle32.v(27) | Synthesizing module Adaptive_FIR_top_COREFFT_0_twiddle in library COREFFT_LIB.

	TDWIDTH=32'b00000000000000000000000000100000
	LOGPTS=32'b00000000000000000000000000001000
   Generated name = Adaptive_FIR_top_COREFFT_0_twiddle_32s_8

@N:CG364 : fftDp.v(369) | Synthesizing module Adaptive_FIR_top_COREFFT_0_twidLUT in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	TDWIDTH=32'b00000000000000000000000000100000
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
   Generated name = Adaptive_FIR_top_COREFFT_0_twidLUT_8_32s_0s_19s

@N:CG364 : kit.v(570) | Synthesizing module fft_inpl_autoScale in library COREFFT_LIB.

	SCALE_MODE=32'b00000000000000000000000000000000
	SCALE_EXP_ON=32'b00000000000000000000000000000000
	LOGLOGPTS=32'b00000000000000000000000000000100
	MEMBUF=32'b00000000000000000000000000000001
   Generated name = fft_inpl_autoScale_0s_0s_4_1s

@W:CG133 : kit.v(590) | Object scale_exp_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : kit.v(590) | Object scale_exp_count is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : COREFFT.v(28) | Synthesizing module Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC in library COREFFT_LIB.

	INVERSE=32'b00000000000000000000000000000000
	SCALE=32'b00000000000000000000000000000000
	POINTS=32'b00000000000000000000000100000000
	WIDTH=32'b00000000000000000000000000010000
	MEMBUF=32'b00000000000000000000000000000001
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	SCALE_EXP_ON=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	LOGPTS=32'b00000000000000000000000000001000
	LOGLOGPTS=32'b00000000000000000000000000000011
	FLOGLOGPTS=32'b00000000000000000000000000000100
	DWIDTH=32'b00000000000000000000000000100000
	TWIDTH=32'b00000000000000000000000000010000
	TDWIDTH=32'b00000000000000000000000000100000
	HALFPTS=32'b00000000000000000000000010000000
	MPIPE=32'b00000000000000000000000000000011
	RW_DLY=32'b00000000000000000000000000001010
   Generated name = Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC_Z4

@N:CG364 : fftDp.v(329) | Synthesizing module Adaptive_FIR_top_COREFFT_0_outBuff in library COREFFT_LIB.

	LOGPTS=32'b00000000000000000000000000001000
	DWIDTH=32'b00000000000000000000000000100000
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
   Generated name = Adaptive_FIR_top_COREFFT_0_outBuff_8_32s_0s_19s

@W:CG360 : COREFFT.v(86) | Removing wire outPQ, as there is no assignment to it.
@W:CG360 : COREFFT.v(87) | Removing wire ctrl_outp, as there is no assignment to it.
@N:CG364 : DATAHANDLE_FSM.v(22) | Synthesizing module DATAHANDLE_FSM in library work.

@W:CG296 : DATAHANDLE_FSM.v(99) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W:CG290 : DATAHANDLE_FSM.v(109) | Referenced variable FFT_RE_RD is not in sensitivity list.
@W:CG290 : DATAHANDLE_FSM.v(101) | Referenced variable FIR_ENABLE is not in sensitivity list.
@W:CG290 : DATAHANDLE_FSM.v(104) | Referenced variable FIR_DATA_OUT is not in sensitivity list.
@W:CG290 : DATAHANDLE_FSM.v(114) | Referenced variable FFT_IM_DATA is not in sensitivity list.
@W:CL169 : DATAHANDLE_FSM.v(118) | Pruning unused register COEF_WR_EN. Make sure that there are no unused intermediate registers.
@W:CL118 : DATAHANDLE_FSM.v(101) | Latch generated from always block for signal PRDATA[15:0]; possible missing assignment in an if or case statement.
@W:CL118 : DATAHANDLE_FSM.v(101) | Latch generated from always block for signal FIR_RADDR[9:0]; possible missing assignment in an if or case statement.
@W:CL118 : DATAHANDLE_FSM.v(101) | Latch generated from always block for signal FFT_RE_RADDR[9:0]; possible missing assignment in an if or case statement.
@W:CL118 : DATAHANDLE_FSM.v(101) | Latch generated from always block for signal FFT_IM_RADDR[9:0]; possible missing assignment in an if or case statement.
@W:CL190 : DATAHANDLE_FSM.v(118) | Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : DATAHANDLE_FSM.v(118) | Pruning unused register PREADY. Make sure that there are no unused intermediate registers.
@N:CG364 : FILTERCONTROL_FSM.v(22) | Synthesizing module FILTERCONTROL_FSM in library work.

@W:CG775 : COREFIR.v(28) | Found Component LMS_FIR_TOP_COREFIR_0_COREFIR in library COREFIR_LIB
@N:CG364 : COREFIR.v(28) | Synthesizing module LMS_FIR_TOP_COREFIR_0_COREFIR in library COREFIR_LIB.

	CFG_ARCH=32'b00000000000000000000000000000001
	COEF_SYMM=32'b00000000000000000000000000000000
	COEF_UNSIGN=32'b00000000000000000000000000000000
	DATA_UNSIGN=32'b00000000000000000000000000000000
	SYSTOLIC=32'b00000000000000000000000000000000
	INP_REG=32'b00000000000000000000000000000000
	TAPS=32'b00000000000000000000000000001000
	COEF_TYPE=32'b00000000000000000000000000000001
	COEF_SETS=32'b00000000000000000000000000000001
	COEF_WIDTH=32'b00000000000000000000000000010000
	DATA_WIDTH=32'b00000000000000000000000000010000
	COEF_RAM=32'b00000000000000000000000000000000
	DATA_RAM=32'b00000000000000000000000000000000
	SAMPLEID=32'b00000000000000000000000000000000
	ID_WIDTH=32'b00000000000000000000000000001100
	SAMPLE_RATE=32'b00000000000011110100001001000000
	L=32'b00000000000000000000000000000010
	M=32'b00000000000000000000000000000010
	CLOCK_RATE=32'b00000000100110001001011010000000
	FPGA_FAMILY=32'b00000000000000000000000000010011
	DIE_SIZE=32'b00000000000000000000000000001010
	URAM_MAXDEPTH=32'b00000000000000000000000000000000
	PERFORMANCE=32'b00000000000000000000000000000000
	RADIX=32'b00000000000000000000000000001010
	FPGA_FAMILYI=32'b00000000000000000000000000010011
	clk_sample_rate=32'b00000000000000000000000000001010
	FLOOR_PHY=32'b00000000000000000000000000000000
	PHY_TAPS_FOLD=32'b00000000000000000000000000000001
	PHY_TAPS_INTP=32'b00000000000000000000000000000100
   Generated name = LMS_FIR_TOP_COREFIR_0_COREFIR_Z5

@N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB.

	BITWIDTH=32'b00000000000000000000000000010000
	DELAY=32'b00000000000000000000000000000000
   Generated name = enum_kitDelay_reg_16s_0s

@W:CG133 : kit.v(81) | Object delayLine_0_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(81) | Some of the address location in the memory "delayLine" are not assigned.
@W:CG133 : kit.v(82) | Object i is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB.

	BITWIDTH=32'b00000000000000000000000000000100
	DELAY=32'b00000000000000000000000000000000
   Generated name = enum_kitDelay_reg_4s_0s

@W:CG133 : kit.v(81) | Object delayLine_0_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(81) | Some of the address location in the memory "delayLine" are not assigned.
@W:CG133 : kit.v(82) | Object i is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB.

	DELAY=32'b00000000000000000000000000000000
   Generated name = enum_kitDelay_bit_reg_0s

@W:CG133 : kit.v(46) | Object delayLine_0_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(46) | Some of the address location in the memory "delayLine" are not assigned.
@W:CG133 : kit.v(47) | Object i is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB.

	DELAY=32'b00000000000000000000000000000100
   Generated name = enum_kitDelay_bit_reg_4s

@W:CG133 : kit.v(46) | Object delayLine_4_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(46) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(185) | Synthesizing module enum_kitSync_ngrst in library COREFIR_LIB.

	PULSE_WIDTH=32'b00000000000000000000000000000001
   Generated name = enum_kitSync_ngrst_1s

@W:CG133 : kit.v(192) | Object tick2 is declared but not assigned. Either assign a value or remove the declaration.
@N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB.

	DELAY=32'b00000000000000000000000000000010
   Generated name = enum_kitDelay_bit_reg_2s

@W:CG133 : kit.v(46) | Object delayLine_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(46) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB.

	DELAY=32'b00000000000000000000000000000111
   Generated name = enum_kitDelay_bit_reg_7

@W:CG133 : kit.v(46) | Object delayLine_7_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(46) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : coef_store.v(54) | Synthesizing module LMS_FIR_TOP_COREFIR_0_wide_coef in library COREFIR_LIB.

	TAPS=32'b00000000000000000000000000001000
	COEF_BITS=32'b00000000000000000000000000010000
	COEF_SETS=32'b00000000000000000000000000000001
	COEF_TYPE=32'b00000000000000000000000000000001
   Generated name = LMS_FIR_TOP_COREFIR_0_wide_coef_8s_16s_1s_1s

@N:CG364 : kit.v(142) | Synthesizing module enum_coef_sr in library COREFIR_LIB.

	TAPS=32'b00000000000000000000000000001000
	COEF_WIDTH=32'b00000000000000000000000000010000
   Generated name = enum_coef_sr_8s_16s

@N:CG364 : enum_fir.v(27) | Synthesizing module LMS_FIR_TOP_COREFIR_0_fir_enum_g4 in library COREFIR_LIB.

	TAPS=32'b00000000000000000000000000001000
	COEF_TYPE=32'b00000000000000000000000000000001
	COEF_SETS=32'b00000000000000000000000000000001
	COEF_SYMM=32'b00000000000000000000000000000000
	COEF_BITS=32'b00000000000000000000000000010000
	COEF_UNSIGN=32'b00000000000000000000000000000000
	DATA_BITS=32'b00000000000000000000000000010000
	DATA_UNSIGN=32'b00000000000000000000000000000000
	ACC_WIDTH=32'b00000000000000000000000000101100
	SYSTOLIC=32'b00000000000000000000000000000000
	VALID_O=32'b00000000000000000000000000000001
	COLUMN=32'b00000000000000000000000000001011
	XREG_COEF=32'b00000000000000000000000000000100
	PERFORMANCE=32'b00000000000000000000000000000000
	TAPS_PHY=32'b00000000000000000000000000001000
	ODD_SYMM=32'b00000000000000000000000000000000
	LATENCY1=32'b00000000000000000000000000000010
	SYST=32'b00000000000000000000000000000000
	XREGS=32'b00000000000000000000000000000000
	LATENC2=32'b00000000000000000000000000000111
	LATENC3=32'b00000000000000000000000000001010
	LATENCY=32'b00000000000000000000000000000111
	MAXDLY=32'b00000000000000000000000000001110
   Generated name = LMS_FIR_TOP_COREFIR_0_fir_enum_g4_Z6

@N:CG364 : kit.v(116) | Synthesizing module enum_signExt in library COREFIR_LIB.

	INWIDTH=32'b00000000000000000000000000010000
	OUTWIDTH=32'b00000000000000000000000000010010
	UNSIGNED=32'b00000000000000000000000000000000
   Generated name = enum_signExt_16s_18s_0s

@N:CG364 : mac.v(64) | Synthesizing module LMS_FIR_TOP_COREFIR_0_mac_enum_g4 in library COREFIR_LIB.

	ACC_WIDTH=32'b00000000000000000000000000101100
	CHAIN_BREAK=32'b00000000000000000000000000000000
	XREG_COEF=32'b00000000000000000000000000000100
	EXTEND=32'b00000000000000000000000000000000
	EXT_WIDTH=32'b00000000000000000000000000000001
   Generated name = LMS_FIR_TOP_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1

@N:CG364 : mac_lib.v(33) | Synthesizing module LMS_FIR_TOP_COREFIR_0_mac18x18_enum_g4 in library COREFIR_LIB.

@N:CG364 : mac.v(31) | Synthesizing module LMS_FIR_TOP_COREFIR_0_add2_g4 in library COREFIR_LIB.

@W:CG360 : mac.v(90) | Removing wire cdout_ext, as there is no assignment to it.
@W:CG360 : mac.v(90) | Removing wire cdin_ext, as there is no assignment to it.
@W:CG360 : mac.v(91) | Removing wire pre_pout, as there is no assignment to it.
@W:CG360 : mac.v(92) | Removing wire dumb, as there is no assignment to it.
@N:CG364 : mac.v(138) | Synthesizing module LMS_FIR_TOP_COREFIR_0_tap_enum_g4 in library COREFIR_LIB.

	COEF_SYMM=32'b00000000000000000000000000000000
	COEF_BITS=32'b00000000000000000000000000010000
	COEF_UNSIGN=32'b00000000000000000000000000000000
	DATA_BITS=32'b00000000000000000000000000010000
	DATA_UNSIGN=32'b00000000000000000000000000000000
	ACC_WIDTH=32'b00000000000000000000000000101100
	CHAIN_BREAK=32'b00000000000000000000000000000000
	XREG_COEF=32'b00000000000000000000000000000100
   Generated name = LMS_FIR_TOP_COREFIR_0_tap_enum_g4_0s_16s_0s_16s_0s_44_0s_4s

@W:CG360 : mac.v(167) | Removing wire data2add, as there is no assignment to it.
@W:CG360 : mac.v(167) | Removing wire symm_data2add, as there is no assignment to it.
@W:CG360 : mac.v(168) | Removing wire coef_val, as there is no assignment to it.
@W:CG360 : mac.v(169) | Removing wire data_tap_w, as there is no assignment to it.
@N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB.

	BITWIDTH=32'b00000000000000000000000000010000
	DELAY=32'b00000000000000000000000000000001
   Generated name = enum_kitDelay_reg_16s_1s

@W:CG133 : kit.v(81) | Object delayLine_1_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(81) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB.

	DELAY=32'b00000000000000000000000000000001
   Generated name = enum_kitDelay_bit_reg_1s

@W:CG133 : kit.v(46) | Object delayLine_1_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : kit.v(46) | Some of the address location in the memory "delayLine" are not assigned.
@N:CG364 : mac.v(241) | Synthesizing module LMS_FIR_TOP_COREFIR_0_odd_symmetry_tap_enum_g4 in library COREFIR_LIB.

	COEF_BITS=32'b00000000000000000000000000010000
	COEF_UNSIGN=32'b00000000000000000000000000000000
	DATA_BITS=32'b00000000000000000000000000010000
	DATA_UNSIGN=32'b00000000000000000000000000000000
	ACC_WIDTH=32'b00000000000000000000000000101100
	XREG_COEF=32'b00000000000000000000000000000100
   Generated name = LMS_FIR_TOP_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s

@W:CG360 : mac.v(266) | Removing wire coef_val, as there is no assignment to it.
@W:CG133 : enum_fir.v(83) | Object index is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_0_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_1_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_2_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_3_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_4_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_5_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_6_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_7_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_8_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_9_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_10_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_11_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_12_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(95) | Object syst_dly_line_13_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : enum_fir.v(95) | Some of the address location in the memory "syst_dly_line" are not assigned.
@W:CG133 : enum_fir.v(96) | Object short_dly_line_-1_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(96) | Object short_dly_line_0_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : enum_fir.v(96) | Some of the address location in the memory "short_dly_line" are not assigned.
@W:CG360 : enum_fir.v(98) | Removing wire turn_data, as there is no assignment to it.
@W:CG360 : enum_fir.v(102) | Removing wire cdsel_odd, as there is no assignment to it.
@W:CG133 : enum_fir.v(108) | Object filled is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(110) | Object add_valid_tick is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : enum_fir.v(110) | Object add_valid_tick2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CL168 : enum_fir.v(249) | Removing instance odd_tap.last_tap because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@N:CG364 : enum_COREFIR.v(47) | Synthesizing module LMS_FIR_TOP_COREFIR_0_COREENUMFIR_G4 in library COREFIR_LIB.

	TAPS=32'b00000000000000000000000000001000
	COEF_TYPE=32'b00000000000000000000000000000001
	COEF_SETS=32'b00000000000000000000000000000001
	COEF_SYMM=32'b00000000000000000000000000000000
	COEF_WIDTH=32'b00000000000000000000000000010000
	COEF_SIGN=32'b00000000000000000000000000000000
	DATA_WIDTH=32'b00000000000000000000000000010000
	DATA_SIGN=32'b00000000000000000000000000000000
	SYSTOLIC=32'b00000000000000000000000000000000
	VALID_O=32'b00000000000000000000000000000001
	INP_REG=32'b00000000000000000000000000000000
	CASCADE=32'b00000000000000000000000000001011
	PERFORMANCE=32'b00000000000000000000000000000000
	OUT_WIDTH=32'b00000000000000000000000000100011
	HW_WIDTH1=32'b00000000000000000000000000100011
	HW_WIDTH=32'b00000000000000000000000000100011
	ACC_WIDTH=32'b00000000000000000000000000101100
	XREG_COEF=32'b00000000000000000000000000000100
	WRAP_LAYERS=32'b00000000000000000000000000000000
   Generated name = LMS_FIR_TOP_COREFIR_0_COREENUMFIR_G4_Z7

@N:CG364 : LMS_ALGO.v(23) | Synthesizing module LMS_ALGO in library work.

@N:CG179 : LMS_ALGO.v(126) | Removing redundant assignment.
@W:CG133 : LMS_ALGO.v(62) | Object NEW_SAMPLE is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_8_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_9_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_10_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_11_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_12_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_13_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_14_ is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : LMS_ALGO.v(69) | Object input_reg_15_ is declared but not assigned. Either assign a value or remove the declaration.
@W: : LMS_ALGO.v(69) | Some of the address location in the memory "input_reg" are not assigned.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[0][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[0][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[1][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[1][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[2][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[2][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[3][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[3][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[4][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[4][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[5][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[5][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[6][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[6][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[7][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[7][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[15][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[15][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[14][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[14][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[13][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[13][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[12][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[12][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[11][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[11][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[10][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[10][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[9][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[9][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 31 to 29 of correction_factor[8][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : LMS_ALGO.v(152) | Pruning unused bits 12 to 0 of correction_factor[8][31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL113 : LMS_ALGO.v(196) | Feedback mux created for signal COEF_DONE. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_15_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_14_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_13_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_12_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_11_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_10_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_9_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(174) | Feedback mux created for signal filter_coefficient_temp_8_[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[15][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[14][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[13][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[12][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[11][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[10][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[9][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : LMS_ALGO.v(152) | Feedback mux created for signal correction_factor[8][28:13]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL250 : LMS_ALGO.v(196) | All reachable assignments to COEF_DONE assign 0, register removed by optimization
@N:CG364 : LMS_CONTROL_FSM.v(20) | Synthesizing module LMS_CONTROL_FSM in library work.

@N:CG364 : LMS_FIR_TOP.v(9) | Synthesizing module LMS_FIR_TOP in library work.

@N:CG364 : Adaptive_FIR_top_TPSRAM_0_TPSRAM.v(5) | Synthesizing module Adaptive_FIR_top_TPSRAM_0_TPSRAM in library work.

@N:CG364 : Adaptive_FIR_top_TPSRAM_1_TPSRAM.v(5) | Synthesizing module Adaptive_FIR_top_TPSRAM_1_TPSRAM in library work.

@N:CG364 : Adaptive_FIR_top_TPSRAM_2_TPSRAM.v(5) | Synthesizing module Adaptive_FIR_top_TPSRAM_2_TPSRAM in library work.

@N:CG364 : Adaptive_FIR_top_TPSRAM_3_TPSRAM.v(5) | Synthesizing module Adaptive_FIR_top_TPSRAM_3_TPSRAM in library work.

@N:CG364 : Adaptive_FIR_top.v(9) | Synthesizing module Adaptive_FIR_top in library work.

@N:CL201 : LMS_CONTROL_FSM.v(59) | Trying to extract state machine for register fsm.
Extracted state machine for register fsm
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N:CL159 : LMS_CONTROL_FSM.v(38) | Input COEF_DONE is unused.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_8_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_9_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_10_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_11_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_12_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_13_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_14_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@A:CL153 : LMS_ALGO.v(69) | *Unassigned bits of input_reg_15_[15:0] are referenced and tied to 0 -- simulation mismatch possible.
@N:CL159 : mac.v(158) | Input symm_datai is unused.
@N:CL159 : mac.v(42) | Input clkEn is unused.
@W:CL156 : enum_fir.v(98) | *Input turn_data[15:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@N:CL159 : coef_store.v(67) | Input set is unused.
@N:CL135 : kit.v(55) | Found sequential shift genblk1.delayLine with address depth of 7 words and data bit width of 1.
@N:CL135 : kit.v(55) | Found sequential shift genblk1.delayLine with address depth of 4 words and data bit width of 1.
@N:CL159 : kit.v(42) | Input nGrst is unused.
@N:CL159 : kit.v(42) | Input rst is unused.
@N:CL159 : kit.v(42) | Input clk is unused.
@N:CL159 : kit.v(42) | Input clkEn is unused.
@N:CL159 : kit.v(77) | Input nGrst is unused.
@N:CL159 : kit.v(77) | Input rst is unused.
@N:CL159 : kit.v(77) | Input clk is unused.
@N:CL159 : kit.v(77) | Input clkEn is unused.
@N:CL159 : kit.v(77) | Input nGrst is unused.
@N:CL159 : kit.v(77) | Input rst is unused.
@N:CL159 : kit.v(77) | Input clk is unused.
@N:CL159 : kit.v(77) | Input clkEn is unused.
@W:CL157 : COREFIR.v(96) | *Output DATAO has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : COREFIR.v(90) | Input COEF_REF is unused.
@N:CL159 : COREFIR.v(92) | Input SAMPLE_ID is unused.
@N:CL159 : COREFIR.v(93) | Input RCLK is unused.
@N:CL201 : FILTERCONTROL_FSM.v(58) | Trying to extract state machine for register fsm.
Extracted state machine for register fsm
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : DATAHANDLE_FSM.v(118) | Trying to extract state machine for register fsm.
Extracted state machine for register fsm
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL246 : DATAHANDLE_FSM.v(55) | Input port bits 15 to 12 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : DATAHANDLE_FSM.v(55) | Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : DATAHANDLE_FSM.v(54) | Input PENABLE is unused.
@N:CL159 : DATAHANDLE_FSM.v(53) | Input FILTER_COMPLETE is unused.
@A:CL153 : kit.v(590) | *Unassigned bits of scale_exp_r[3:0] are referenced and tied to 0 -- simulation mismatch possible.
@N:CL159 : kit.v(584) | Input fftRd_done_tick is unused.
@W:CL260 : kit.v(560) | Pruning register bit 16 of outQ[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL246 : kit.v(369) | Input port bits 42 to 32 of inp[43:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : fftDp.v(258) | Input load is unused.
@N:CL159 : fftSm.v(549) | Input rTimerTC_tick is unused.
@N:CL159 : fftSm.v(493) | Input clkEn is unused.
@W:CL157 : COREFFT_TOP.v(86) | *Output RFS has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : COREFFT_TOP.v(86) | *Output OVFLOW_FLAG has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : COREFFT_TOP.v(85) | Input CLKEN is unused.
@N:CL159 : COREFFT_TOP.v(85) | Input RST is unused.
@N:CL159 : COREFFT_TOP.v(85) | Input START is unused.
@N:CL159 : COREFFT_TOP.v(85) | Input INVERSE_STRM is unused.
@N:CL159 : COREFFT_TOP.v(85) | Input REFRESH is unused.
@W:CL157 : Adaptive_FIR_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : Adaptive_FIR_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : Adaptive_FIR_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W:CL157 : Adaptive_FIR_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@N:CL159 : Adaptive_FIR_FABOSC_0_OSC.v(14) | Input XTL is unused.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state.
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state.
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state.
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state.
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state.
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused.
@N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused.
@N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused.
@N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused.
@N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused.
@N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused.
@N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused.
@N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused.
@N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused.
@N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused.
@N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused.
@N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused.
@N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused.
@N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused.
@N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused.
@N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused.
@N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused.
@N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused.
@N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused.
@N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused.
@N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused.
@N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused.
@N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused.
@N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused.
@N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused.
@N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused.
@N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused.
@N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused.
@N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused.
@N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused.
@N:CL159 : coreapb3.v(72) | Input IADDR is unused.
@N:CL159 : coreapb3.v(73) | Input PRESETN is unused.
@N:CL159 : coreapb3.v(74) | Input PCLK is unused.
@N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused.
@N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused.
@N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused.
@N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused.
@N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused.
@N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused.
@N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused.
@N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused.
@N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused.
@N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused.
@N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused.
@N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused.
@N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused.
@N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused.
@N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused.
@N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused.
@N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused.
@N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused.
@N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused.
@N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused.
@N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused.
@N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused.
@N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused.
@N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused.
@N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused.
@N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused.
@N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused.
@N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused.
@N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused.
@N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused.
@N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused.
@N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused.
@N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused.
@N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused.
@N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused.
@N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused.
@N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused.
@N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused.
@N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused.
@N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused.
@N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused.
@N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused.
@N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused.
@N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused.
@N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Sep 11 19:35:46 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Sep 11 19:35:46 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Sep 11 19:35:46 2017

###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 82MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Sep 11 19:35:47 2017

###########################################################]
Pre-mapping Report

# Mon Sep 11 19:35:48 2017

Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\designer\Adaptive_FIR_top\synthesis.fdc
Linked File: Adaptive_FIR_top_scck.rpt
Printing clock  summary report in "D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\synthesis\Adaptive_FIR_top_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 123MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 123MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 123MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 123MB)

@W:BN132 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : fftsm.v(675) | Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : corefft_top.v(86) | Tristate driver OVFLOW_FLAG (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) on net OVFLOW_FLAG (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) has its enable tied to GND.
@N:MO111 : corefft_top.v(86) | Tristate driver RFS (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) on net RFS (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_1 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_1 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_2 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_2 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_3 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_3 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_4 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_4 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@W:MO129 : coreresetp.v(676) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(769) | Sequential instance Adaptive_FIR_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(676) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(769) | Sequential instance Adaptive_FIR_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(676) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(695) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(714) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(733) | Sequential instance Adaptive_FIR_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W:MO129 : coreresetp.v(1388) | Sequential instance Adaptive_FIR_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@N:BN115 : enum_corefir.v(108) | Removing instance wrap_coef_sel (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREENUMFIR_G4_Z7(verilog)) of type view:COREFIR_LIB.enum_kitDelay_reg_4s_0s(verilog) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : fftsm.v(675) | Removing sequential instance swCross (in view: COREFFT_LIB.fft_inpl_inBuf_fftA_pipe_8_3_0(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N:BN362 : corefft.v(229) | Removing sequential instance buf_ready_r (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC_Z4(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N:BN362 : kit.v(218) | Removing sequential instance pulse (in view: COREFIR_LIB.enum_kitSync_ngrst_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N:BN362 : fftsm.v(265) | Removing sequential instance fftRd_done_tick (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N:BN362 : filtercontrol_fsm.v(58) | Removing sequential instance FILTER_COMPLETE (in view: work.FILTERCONTROL_FSM(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corefft.v(229) | Removing sequential instance datao_valid_r (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC_Z4(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N:BN362 : kit.v(200) | Removing sequential instance tick1 (in view: COREFIR_LIB.enum_kitSync_ngrst_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N:BN115 : enum_fir.v(297) | Removing instance fill_in_dly (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_fir_enum_g4_Z6(verilog)) of type view:COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog) because it does not drive other instances.
@N:BN115 : fftsm.v(582) | Removing instance bit_dly_1 (in view: COREFFT_LIB.fft_inpl_outBufA_256s_8_1s(verilog)) of type view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because it does not drive other instances.
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_6_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN115 : enum_fir.v(284) | Removing instance pipe_dly_0 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_fir_enum_g4_Z6(verilog)) of type view:COREFIR_LIB.enum_kitDelay_bit_reg_2s(verilog) because it does not drive other instances.
@N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine_2_ (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1\.delayLine_1_ (in view: COREFIR_LIB.enum_kitDelay_bit_reg_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_5_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine_1_ (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1\.delayLine_0_ (in view: COREFIR_LIB.enum_kitDelay_bit_reg_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN115 : enum_fir.v(280) | Removing instance sync_ngrst_0 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_fir_enum_g4_Z6(verilog)) of type view:COREFIR_LIB.enum_kitSync_ngrst_1s(verilog) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_4_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN115 : kit.v(196) | Removing instance sync_ngrst_0 (in view: COREFIR_LIB.enum_kitSync_ngrst_1s(verilog)) of type view:COREFIR_LIB.enum_kitDelay_bit_reg_4s(verilog) because it does not drive other instances.
@N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine_0_ (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_3_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_4s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_3_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_2_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_4s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_1_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_4s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_2_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_0_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_4s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_1_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(55) | Removing sequential instance genblk1.delayLine_0_[0] (in view: COREFIR_LIB.enum_kitDelay_bit_reg_7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
syn_allowed_resources : blockrams=21,dsps=22  set on top level netlist Adaptive_FIR_top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 157MB peak: 158MB)



Clock Summary
*****************

Start                                               Requested     Requested     Clock                                                                Clock                   Clock
Clock                                               Frequency     Period        Type                                                                 Group                   Load 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Adaptive_FIR_0/CCC_0/GL0                            100.0 MHz     10.000        generated (from Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup        1998 
Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     50.0 MHz      20.000        declared                                                             default_clkgroup        15   
System                                              100.0 MHz     10.000        system                                                               system_clkgroup         46   
fft_inpl_slowClock|divider_inferred_clock[2]        100.0 MHz     10.000        inferred                                                             Inferred_clkgroup_0     17   
==================================================================================================================================================================================

@W:MT532 : datahandle_fsm.v(101) | Found signal identified as System clock which controls 46 sequential elements including DATAHANDLE_FSM_0.PRDATA[15:0].  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W:MT530 : kit.v(203) | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 17 sequential elements including COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine_3_. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\synthesis\Adaptive_FIR_top.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 154MB peak: 158MB)

Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : datahandle_fsm.v(118) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required.
Encoding state machine fsm[2:0] (in view: work.FILTERCONTROL_FSM(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine fsm[7:0] (in view: work.LMS_CONTROL_FSM(verilog))
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_1_[3] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_5_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_1_[4] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_5_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_0_[3] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_5_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_0_[4] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_5_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_1_[7] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_10_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_1_[8] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_10_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_1_[9] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_10_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_0_[7] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_10_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_0_[8] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_10_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance genblk1\.delayLine_0_[9] (in view: COREFFT_LIB.fft_inpl_kitDelay_reg_10_2s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@W:MF511 :  | Found issues with constraints. Please check constraint checker report "D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\synthesis\Adaptive_FIR_top_cck.rpt" . 

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 156MB peak: 158MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 158MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Sep 11 19:35:49 2017

###########################################################]
Map & Optimize Report

# Mon Sep 11 19:35:49 2017

Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)

@N:MO111 : adaptive_fir_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : adaptive_fir_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Adaptive_FIR_FABOSC_0_OSC(verilog)) has its enable tied to GND.
@N:MO111 : corefft_top.v(86) | Tristate driver OVFLOW_FLAG (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) on net OVFLOW_FLAG (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) has its enable tied to GND.
@N:MO111 : corefft_top.v(86) | Tristate driver RFS (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) on net RFS (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_Z3(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_1 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_1 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_2 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_2 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_3 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_3 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@N:MO111 : corefir.v(96) | Tristate driver DATAO_4 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) on net DATAO_4 (in view: COREFIR_LIB.LMS_FIR_TOP_COREFIR_0_COREFIR_Z5(verilog)) has its enable tied to GND.
@W:BN132 : coreresetp.v(963) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(946) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(946) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(929) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(884) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(912) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(898) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(912) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(898) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : coreresetp.v(884) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance Adaptive_FIR_0.CORERESETP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 150MB)

Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@N:MO231 : kit.v(111) | Found counter in view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) instance wTimer_0.Q[6:0] 
@N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_1_[3] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_1_[4] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_1_[7] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_1_[8] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_1_[9] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_0_[3] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_0_[4] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_0_[7] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_0_[8] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_0_[9] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:MO231 : kit.v(139) | Found counter in view:COREFFT_LIB.fft_inpl_counter_w_10_137s(verilog) instance Q[9:0] 
@N:MO231 : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_5_7(verilog) instance Q[4:0] 
@N:MO231 : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_8_255s(verilog) instance Q[7:0] 
@N:MO231 : kit.v(168) | Found counter in view:COREFFT_LIB.fft_inpl_twid_wA_gen_8_3(verilog) instance slowTimer.Q[6:0] 
Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : datahandle_fsm.v(118) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM(verilog)); safe FSM implementation is not required.
Encoding state machine fsm[2:0] (in view: work.FILTERCONTROL_FSM(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MO231 : filtercontrol_fsm.v(58) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance FIR_RADDR[9:0] 
@N:MO231 : filtercontrol_fsm.v(58) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance FFT_WADDR[9:0] 
@N:BN362 : lms_algo.v(133) | Removing sequential instance coef[4] (in view: work.LMS_ALGO(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine fsm[7:0] (in view: work.LMS_CONTROL_FSM(verilog))
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@N:MO231 : lms_control_fsm.v(59) | Found counter in view:work.LMS_CONTROL_FSM(verilog) instance COUNT[4:0] 

Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)

@N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[3] (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC_Z4(verilog)) because it does not drive other instances.
@N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[4] (in view: COREFFT_LIB.Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC_Z4(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.INIT_DONE_int (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[6] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 166MB peak: 167MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 173MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 165MB peak: 174MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 166MB peak: 174MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 167MB peak: 174MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 166MB peak: 174MB)

@N:MO106 : twiddle32.v(35) | Found ROM .delname. (in view: work.Adaptive_FIR_top(verilog)) with 128 words by 32 bits.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif2_core_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif1_core_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif0_core_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.ddr_settled_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(963) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif3_spll_lock_q2 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(929) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif3_core_clk_base (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif2_core_clk_base (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif1_core_clk_base (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif0_core_clk_base (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.ddr_settled_clk_base (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1613) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.ddr_settled (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1485) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif0_core (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1646) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.release_sdif3_core_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(870) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(870) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sdif0_areset_n_rcosc (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(856) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_areset_n_rcosc_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(856) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_areset_n_rcosc (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(755) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(755) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_areset_n_clk_base (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[5] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[4] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[3] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[2] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[1] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.
@N:BN362 : coreresetp.v(1089) | Removing sequential instance Adaptive_FIR_0.CORERESETP_0.sm0_state[0] (in view: work.Adaptive_FIR_top(verilog)) because it does not drive other instances.

Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 166MB peak: 174MB)


Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 221MB peak: 224MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		     0.34ns		2136 /      1894
   2		0h:00m:04s		     1.00ns		1953 /      1894
   3		0h:00m:04s		     1.00ns		1951 /      1894
@N:FP130 :  | Promoting Net Adaptive_FIR_0_MSS_READY on CLKINT  I_373  
@N:FP130 :  | Promoting Net COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider_i_0[2] on CLKINT  I_374  
Replicating Sequential Instance LMS_FIR_TOP_0.COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.add_valid_r, fanout 24 segments 24

Added 0 Buffers
Added 23 Cells via replication
	Added 23 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 224MB peak: 226MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:06s; Memory used current: 226MB peak: 226MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 2024 clock pin(s) of sequential element(s)
0 instances converted, 2024 sequential instances remain driven by gated/generated clocks

====================================================================================================== Gated/Generated Clocks =======================================================================================================
Clock Tree ID     Driving Element                                          Drive Element Type     Fanout     Sample Instance                                                  Explanation                                            
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        Adaptive_FIR_0.CCC_0.CCC_INST                            CCC                    1961       Adaptive_FIR_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base        No gated clock conversion method for cell cell:ACG4.SLE
ClockId0002        COREFFT_0.genblk1.DUT_INPLACE.slowClock_0.divider[2]     SLE                    17         COREFFT_0.genblk1.DUT_INPLACE.sm_0.twid_wA_0.preRstAfterInit     No gated clock conversion method for cell cell:ACG4.SLE
ClockId0003        DATAHANDLE_FSM_0.un1_FIR_ENABLE_2                        CFG2                   46         DATAHANDLE_FSM_0.PRDATA[10]                                      No gated clock conversion method for cell cell:ACG4.SLE
=====================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 187MB peak: 226MB)

Writing Analyst data base D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\synthesis\synwork\Adaptive_FIR_top_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 222MB peak: 226MB)

Writing EDIF Netlist and constraint files
@N:FX1056 :  | Writing EDF file: D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\synthesis\Adaptive_FIR_top.edn 
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
L-2016.09M-2

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 223MB peak: 227MB)


Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 221MB peak: 227MB)

@W:MT246 : adaptive_fir_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] with period 10.00ns. Please declare a user-defined clock on object "n:COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2]" 
@N:MT615 :  | Found clock Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns  
@N:MT615 :  | Found clock Adaptive_FIR_0/CCC_0/GL0 with period 10.00ns  


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Sep 11 19:35:57 2017
#


Top view:               Adaptive_FIR_top
Requested Frequency:    50.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\designer\Adaptive_FIR_top\synthesis.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: 1.486

                                                    Requested     Estimated     Requested     Estimated               Clock                                                                Clock              
Starting Clock                                      Frequency     Frequency     Period        Period        Slack     Type                                                                 Group              
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Adaptive_FIR_0/CCC_0/GL0                            100.0 MHz     117.5 MHz     10.000        8.514         1.486     generated (from Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT)     default_clkgroup   
Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT     50.0 MHz      NA            20.000        NA            NA        declared                                                             default_clkgroup   
fft_inpl_slowClock|divider_inferred_clock[2]        100.0 MHz     155.7 MHz     10.000        6.421         3.579     inferred                                                             Inferred_clkgroup_0
System                                              100.0 MHz     462.1 MHz     10.000        2.164         7.836     system                                                               system_clkgroup    
==============================================================================================================================================================================================================
@N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack 





Clock Relationships
*******************

Clocks                                                                                      |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                      Ending                                        |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                        Adaptive_FIR_0/CCC_0/GL0                      |  10.000      7.836  |  No paths    -      |  No paths    -      |  No paths    -    
Adaptive_FIR_0/CCC_0/GL0                      System                                        |  10.000      4.924  |  No paths    -      |  No paths    -      |  No paths    -    
Adaptive_FIR_0/CCC_0/GL0                      Adaptive_FIR_0/CCC_0/GL0                      |  10.000      1.486  |  No paths    -      |  No paths    -      |  No paths    -    
fft_inpl_slowClock|divider_inferred_clock[2]  Adaptive_FIR_0/CCC_0/GL0                      |  No paths    -      |  No paths    -      |  No paths    -      |  Diff grp    -    
fft_inpl_slowClock|divider_inferred_clock[2]  fft_inpl_slowClock|divider_inferred_clock[2]  |  No paths    -      |  10.000      3.579  |  No paths    -      |  No paths    -    
==================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Adaptive_FIR_0/CCC_0/GL0
====================================



Starting Points with Worst Slack
********************************

                                             Starting                                                          Arrival          
Instance                                     Reference                    Type     Pin     Net                 Time        Slack
                                             Clock                                                                              
--------------------------------------------------------------------------------------------------------------------------------
LMS_FIR_TOP_0.LMS_ALGO_0.mul_index[2]        Adaptive_FIR_0/CCC_0/GL0     SLE      Q       mul_index[2]        0.094       1.486
LMS_FIR_TOP_0.LMS_ALGO_0.mul_index[1]        Adaptive_FIR_0/CCC_0/GL0     SLE      Q       mul_index[1]        0.076       1.559
LMS_FIR_TOP_0.LMS_ALGO_0.mul_index[0]        Adaptive_FIR_0/CCC_0/GL0     SLE      Q       mul_index[0]        0.094       1.599
LMS_FIR_TOP_0.LMS_ALGO_0.add_index[2]        Adaptive_FIR_0/CCC_0/GL0     SLE      Q       add_index[2]        0.094       2.646
LMS_FIR_TOP_0.LMS_ALGO_0.input_reg_5_[5]     Adaptive_FIR_0/CCC_0/GL0     SLE      Q       input_reg_5_[5]     0.076       2.732
LMS_FIR_TOP_0.LMS_ALGO_0.input_reg_5_[1]     Adaptive_FIR_0/CCC_0/GL0     SLE      Q       input_reg_5_[1]     0.076       2.771
LMS_FIR_TOP_0.LMS_ALGO_0.input_reg_5_[2]     Adaptive_FIR_0/CCC_0/GL0     SLE      Q       input_reg_5_[2]     0.076       2.771
LMS_FIR_TOP_0.LMS_ALGO_0.input_reg_5_[3]     Adaptive_FIR_0/CCC_0/GL0     SLE      Q       input_reg_5_[3]     0.076       2.771
LMS_FIR_TOP_0.LMS_ALGO_0.input_reg_5_[4]     Adaptive_FIR_0/CCC_0/GL0     SLE      Q       input_reg_5_[4]     0.076       2.771
LMS_FIR_TOP_0.LMS_ALGO_0.input_reg_5_[6]     Adaptive_FIR_0/CCC_0/GL0     SLE      Q       input_reg_5_[6]     0.076       2.771
================================================================================================================================


Ending Points with Worst Slack
******************************

                                                        Starting                                                                        Required          
Instance                                                Reference                    Type     Pin     Net                               Time         Slack
                                                        Clock                                                                                             
----------------------------------------------------------------------------------------------------------------------------------------------------------
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][13]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[13]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][14]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[14]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][15]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[15]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][16]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[16]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][17]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[17]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][18]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[18]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][19]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[19]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][20]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[20]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][21]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[21]     9.778        1.486
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][22]     Adaptive_FIR_0/CCC_0/GL0     SLE      D       correction_factor\[15\]_2[22]     9.778        1.486
==========================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.222
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.778

    - Propagation time:                      8.292
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.486

    Number of logic level(s):                6
    Starting point:                          LMS_FIR_TOP_0.LMS_ALGO_0.mul_index[2] / Q
    Ending point:                            LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][28] / D
    The start point is clocked by            Adaptive_FIR_0/CCC_0/GL0 [rising] on pin CLK
    The end   point is clocked by            Adaptive_FIR_0/CCC_0/GL0 [rising] on pin CLK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                                     Type     Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
LMS_FIR_TOP_0.LMS_ALGO_0.mul_index[2]                                    SLE      Q         Out     0.094     0.094       -         
mul_index[2]                                                             Net      -         -       0.931     -           9         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_0_a4_2[15]        CFG2     B         In      -         1.026       -         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_0_a4_2[15]        CFG2     Y         Out     0.143     1.169       -         
N_252                                                                    Net      -         -       0.893     -           28        
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_a2_0[5]           CFG3     B         In      -         2.062       -         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_a2_0[5]           CFG3     Y         Out     0.143     2.205       -         
N_132                                                                    Net      -         -       0.483     -           1         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_1[5]              CFG4     C         In      -         2.688       -         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_1[5]              CFG4     Y         Out     0.182     2.870       -         
un13_correction_factor_0_iv_i_1[5]                                       Net      -         -       0.483     -           1         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_5[5]              CFG4     C         In      -         3.353       -         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_5[5]              CFG4     Y         Out     0.182     3.535       -         
un13_correction_factor_0_iv_i_5[5]                                       Net      -         -       0.483     -           1         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_5_RNILJPF1[5]     CFG4     B         In      -         4.019       -         
LMS_FIR_TOP_0.LMS_ALGO_0.un13_correction_factor_0_iv_i_5_RNILJPF1[5]     CFG4     Y         Out     0.129     4.148       -         
N_29_i                                                                   Net      -         -       0.971     -           1         
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[15\]_2_mulonly_0[28:0]       MACC     B[5]      In      -         5.119       -         
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[15\]_2_mulonly_0[28:0]       MACC     P[28]     Out     2.181     7.300       -         
correction_factor\[15\]_2[28]                                            Net      -         -       0.992     -           16        
LMS_FIR_TOP_0.LMS_ALGO_0.correction_factor\[0\][28]                      SLE      D         In      -         8.292       -         
====================================================================================================================================
Total path delay (propagation time + setup) of 8.514 is 3.276(38.5%) logic and 5.238(61.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: fft_inpl_slowClock|divider_inferred_clock[2]
====================================



Starting Points with Worst Slack
********************************

                                                                                                 Starting                                                                           Arrival          
Instance                                                                                         Reference                                        Type     Pin     Net              Time        Slack
                                                                                                 Clock                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[1]     0.094       3.579
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[0]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[0]     0.094       3.627
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[2]     0.094       3.631
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[3]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[3]     0.094       4.346
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[4]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[4]     0.094       4.566
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[5]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[5]     0.094       5.332
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[6]                                     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wA_w[6]     0.094       6.808
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.pulse                                  fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       pulse_rst        0.094       7.196
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.twid_wEn                                           fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       twid_wEn_w       0.094       8.363
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine_3_     fft_inpl_slowClock|divider_inferred_clock[2]     SLE      Q       synced_ngrst     0.076       8.811
=====================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                         Starting                                                                                      Required          
Instance                                                                                                                 Reference                                        Type        Pin           Net                Time         Slack
                                                                                                                         Clock                                                                                                           
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[12]     twidData_w[11]     9.708        3.579
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[2]      twidData_w[2]      9.708        3.601
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[5]      twidData_w[5]      9.708        3.782
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[7]      twidData_w[7]      9.708        3.786
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[11]     twidData_w[10]     9.708        3.871
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[6]      twidData_w[6]      9.708        4.013
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[1]      N_63_i             9.708        4.050
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[0]      N_35_i             9.708        4.087
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[10]     twidData_w[9]      9.708        4.098
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     fft_inpl_slowClock|divider_inferred_clock[2]     RAM1K18     B_DIN[4]      twidData_w[4]      9.708        4.138
=========================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.292
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.708

    - Propagation time:                      6.128
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 3.579

    Number of logic level(s):                6
    Starting point:                          COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1] / Q
    Ending point:                            COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0 / B_DIN[12]
    The start point is clocked by            fft_inpl_slowClock|divider_inferred_clock[2] [falling] on pin CLK
    The end   point is clocked by            fft_inpl_slowClock|divider_inferred_clock[2] [falling] on pin B_CLK

Instance / Net                                                                                                                       Pin           Pin               Arrival     No. of    
Name                                                                                                                     Type        Name          Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1]                                                             SLE         Q             Out     0.094     0.094       -         
twid_wA_w[1]                                                                                                             Net         -             -       1.232     -           97        
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m6_i                                                                      CFG2        B             In      -         1.326       -         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m6_i                                                                      CFG2        Y             Out     0.143     1.469       -         
N_7_i                                                                                                                    Net         -             -       0.590     -           3         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m259_2                                                                    CFG4        B             In      -         2.059       -         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m259_2                                                                    CFG4        Y             Out     0.143     2.201       -         
m259_2                                                                                                                   Net         -             -       0.483     -           1         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m259_4_1_0_0_wmux                                                         ARI1        D             In      -         2.685       -         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m259_4_1_0_0_wmux                                                         ARI1        Y             Out     0.284     2.969       -         
m259_4_1_0_0_y0                                                                                                          Net         -             -       0.324     -           1         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m259_4_1_0_wmux_0                                                         ARI1        A             In      -         3.292       -         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m259_4_1_0_wmux_0                                                         ARI1        Y             Out     0.087     3.380       -         
m259_4_1_0_wmux_0_Y                                                                                                      Net         -             -       0.971     -           1         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m260                                                                      CFG3        A             In      -         4.351       -         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m260                                                                      CFG3        Y             Out     0.076     4.427       -         
m260                                                                                                                     Net         -             -       0.548     -           2         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m268                                                                      CFG3        C             In      -         4.975       -         
COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m268                                                                      CFG3        Y             Out     0.182     5.157       -         
twidData_w[11]                                                                                                           Net         -             -       0.971     -           1         
COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0     RAM1K18     B_DIN[12]     In      -         6.128       -         
===========================================================================================================================================================================================
Total path delay (propagation time + setup) of 6.421 is 1.301(20.3%) logic and 5.119(79.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                Starting                                                                  Arrival          
Instance                        Reference     Type     Pin     Net                                        Time        Slack
                                Clock                                                                                      
---------------------------------------------------------------------------------------------------------------------------
DATAHANDLE_FSM_0.PRDATA[3]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[3]      0.094       7.836
DATAHANDLE_FSM_0.PRDATA[4]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[4]      0.094       7.892
DATAHANDLE_FSM_0.PRDATA[9]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[9]      0.094       7.947
DATAHANDLE_FSM_0.PRDATA[0]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[0]      0.094       7.970
DATAHANDLE_FSM_0.PRDATA[13]     System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[13]     0.094       7.993
DATAHANDLE_FSM_0.PRDATA[11]     System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[11]     0.094       8.003
DATAHANDLE_FSM_0.PRDATA[6]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[6]      0.094       8.004
DATAHANDLE_FSM_0.PRDATA[8]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[8]      0.094       8.021
DATAHANDLE_FSM_0.PRDATA[5]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[5]      0.094       8.025
DATAHANDLE_FSM_0.PRDATA[1]      System        SLE      Q       Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[1]      0.094       8.037
===========================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                                                   Required          
Instance                                             Reference     Type        Pin                 Net                                          Time         Slack
                                                     Clock                                                                                                        
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[3]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[3]      9.553        7.836
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[4]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[4]      9.609        7.892
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[9]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[9]      9.664        7.947
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[0]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[0]      9.687        7.970
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[13]     Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[13]     9.710        7.993
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[11]     Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[11]     9.720        8.003
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[6]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[6]      9.721        8.004
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[8]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[8]      9.738        8.021
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[5]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[5]      9.742        8.025
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST     System        MSS_010     F_HM0_RDATA[1]      Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[1]      9.754        8.037
==================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.447
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.553

    - Propagation time:                      1.717
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 7.836

    Number of logic level(s):                1
    Starting point:                          DATAHANDLE_FSM_0.PRDATA[3] / Q
    Ending point:                            Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            System [rising] on pin CLK
    The end   point is clocked by            Adaptive_FIR_0/CCC_0/GL0 [rising] on pin CLK_BASE

Instance / Net                                                         Pin                Pin               Arrival     No. of    
Name                                                       Type        Name               Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
DATAHANDLE_FSM_0.PRDATA[3]                                 SLE         Q                  Out     0.094     0.094       -         
Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[3]                      Net         -                  -       0.509     -           1         
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST_RNO_2     CFG2        B                  In      -         0.603       -         
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST_RNO_2     CFG2        Y                  Out     0.143     0.746       -         
Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_m[3]                    Net         -                  -       0.971     -           1         
Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST           MSS_010     F_HM0_RDATA[3]     In      -         1.717       -         
==================================================================================================================================
Total path delay (propagation time + setup) of 2.164 is 0.684(31.6%) logic and 1.480(68.4%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
@W:MT447 : synthesis.fdc(9) | Timing constraint (through [get_pins { Adaptive_FIR_0.Adaptive_FIR_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(10) | Timing constraint (through [get_nets { Adaptive_FIR_0.CORERESETP_0.ddr_settled Adaptive_FIR_0.CORERESETP_0.count_ddr_enable Adaptive_FIR_0.CORERESETP_0.release_sdif*_core Adaptive_FIR_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(11) | Timing constraint (from [get_cells { Adaptive_FIR_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Adaptive_FIR_0.CORERESETP_0.sm0_areset_n_rcosc Adaptive_FIR_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(12) | Timing constraint (from [get_cells { Adaptive_FIR_0.CORERESETP_0.MSS_HPMS_READY_int Adaptive_FIR_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Adaptive_FIR_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_nets { Adaptive_FIR_0.CORERESETP_0.CONFIG1_DONE Adaptive_FIR_0.CORERESETP_0.CONFIG2_DONE Adaptive_FIR_0.CORERESETP_0.SDIF*_PERST_N Adaptive_FIR_0.CORERESETP_0.SDIF*_PSEL Adaptive_FIR_0.CORERESETP_0.SDIF*_PWRITE Adaptive_FIR_0.CORERESETP_0.SDIF*_PRDATA[*] Adaptive_FIR_0.CORERESETP_0.SOFT_EXT_RESET_OUT Adaptive_FIR_0.CORERESETP_0.SOFT_RESET_F2M Adaptive_FIR_0.CORERESETP_0.SOFT_M3_RESET Adaptive_FIR_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET Adaptive_FIR_0.CORERESETP_0.SOFT_FDDR_CORE_RESET Adaptive_FIR_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET Adaptive_FIR_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET Adaptive_FIR_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET Adaptive_FIR_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W:MT447 : synthesis.fdc(14) | Timing constraint (through [get_pins { Adaptive_FIR_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 

Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 222MB peak: 227MB)


Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 222MB peak: 227MB)

---------------------------------------
Resource Usage Report for Adaptive_FIR_top 

Mapping to part: m2s010tfbga484-1
Cell usage:
CCC             1 use
CLKINT          3 uses
MSS_010         1 use
RCOSC_25_50MHZ  1 use
SYSRESET        1 use
CFG1           7 uses
CFG2           257 uses
CFG3           690 uses
CFG4           637 uses

Carry cells:
ARI1            212 uses - used for arithmetic functions
ARI1            166 uses - used for Wide-Mux implementation
Total ARI1      378 uses


Sequential Cells: 
SLE            1963 uses

DSP Blocks:   13 of 22 (59%)
 MACC:        13 Mults

I/O ports: 3
I/O primitives: 2
INBUF          1 use
TRIBUFF        1 use


Global Clock Buffers: 3 of 8 (37%)


RAM/ROM usage summary
Total Block RAMs (RAM1K18) : 11 of 21 (52%)

Total LUTs:    1969

Extra resources required for RAM and MACC interface logic during P&R:

RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
RAM1K18  Interface Logic : SLEs = 396; LUTs = 396;
MACC     Interface Logic : SLEs = 468; LUTs = 468;

Total number of SLEs after P&R:  1963 + 0 + 396 + 468 = 2827;
Total number of LUTs after P&R:  1969 + 0 + 396 + 468 = 2833;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 41MB peak: 227MB)

Process took 0h:00m:09s realtime, 0h:00m:09s cputime
# Mon Sep 11 19:35:58 2017

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