DESIGN:Adaptive_FIR_top_COREFFT_0_ram_smGen
FAM:SmartFusion2
OUTFORMAT:Verilog
LPMTYPE:LPM_RAM
DEVICE:15000
CLKS:2
RESET_POLARITY:2
PTYPE:1
MGNTIMER:F
MGNCMPL:F
GEN_BEHV_MODULE:F
WWIDTH:32
RWIDTH:32
WDEPTH:128
RDEPTH:128
WE_POLARITY:1
RE_POLARITY:1
RCLK_EDGE:RISE
WCLK_EDGE:RISE
PMODE2:1
DATA_IN_PN:DI
DATA_OUT_PN:DO
WADDRESS_PN:WADDR
RADDRESS_PN:RADDR
WE_PN:WRB
RE_PN:RDB
WCLOCK_PN:WCLOCK
RCLOCK_PN:RCLOCK
CLOCK_PN:clk
RESET_PN:ARST
CASCADE:0
A_DOUT_EN_POLARITY:2
B_DOUT_EN_POLARITY:2
A_DOUT_EN_PN:XYZ
B_DOUT_EN_PN:DOUT_EN
