<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.8.1.12</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)</text>
<text>Date: Mon Sep 11 19:38:35 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>5.290</cell>
 <cell>189.036</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>9.883</cell>
 <cell>7.036</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>4.428</cell>
 <cell>225.836</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/CCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_4_[13]:D</cell>
 <cell>5.094</cell>
 <cell>4.710</cell>
 <cell>7.968</cell>
 <cell>12.678</cell>
 <cell>0.201</cell>
 <cell>5.290</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_5_[13]:D</cell>
 <cell>5.094</cell>
 <cell>4.710</cell>
 <cell>7.968</cell>
 <cell>12.678</cell>
 <cell>0.201</cell>
 <cell>5.290</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[10][17]:D</cell>
 <cell>5.066</cell>
 <cell>4.711</cell>
 <cell>7.958</cell>
 <cell>12.669</cell>
 <cell>0.201</cell>
 <cell>5.289</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][17]:D</cell>
 <cell>5.066</cell>
 <cell>4.711</cell>
 <cell>7.958</cell>
 <cell>12.669</cell>
 <cell>0.201</cell>
 <cell>5.289</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[6][17]:D</cell>
 <cell>5.066</cell>
 <cell>4.718</cell>
 <cell>7.958</cell>
 <cell>12.676</cell>
 <cell>0.201</cell>
 <cell>5.282</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_4_[13]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.678</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.968</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.710</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>2.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.113</cell>
 <cell>2.173</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB11:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.364</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB11:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>2.537</cell>
 <cell>69</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB11_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.337</cell>
 <cell>2.874</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.060</cell>
 <cell>2.934</cell>
 <cell>43</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_a4_7[2]:A</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.739</cell>
 <cell>3.673</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_a4_7[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>3.783</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_2[9]:D</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_2135</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.711</cell>
 <cell>4.494</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_2[9]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.110</cell>
 <cell>4.604</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_12[9]:B</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_2[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.810</cell>
 <cell>5.414</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_12[9]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.051</cell>
 <cell>5.465</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_0_cy_363:C</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un10_filter_coefficient_temp_i_i_12[9]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.303</cell>
 <cell>5.768</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_0_cy_363:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.050</cell>
 <cell>5.818</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_9:B</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_298_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.520</cell>
 <cell>6.338</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_9:UB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.190</cell>
 <cell>6.528</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_0_cy_CC_1:UB[1]</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG203</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.528</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_0_cy_CC_1:CC[5]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CC_CONFIG</cell>
 <cell>+</cell>
 <cell>0.511</cell>
 <cell>7.039</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_13:CC</cell>
 <cell>net</cell>
 <cell>NET_CC_CONFIG216</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.039</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_13:S</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:ARI1_CC</cell>
 <cell>+</cell>
 <cell>0.046</cell>
 <cell>7.085</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_4_[13]:D</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un8_filter_coefficient_temp_cry_13_S</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.883</cell>
 <cell>7.968</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.968</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>11.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>12.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>12.174</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB13:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.192</cell>
 <cell>12.366</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB13:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>12.539</cell>
 <cell>61</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_4_[13]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB13_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.340</cell>
 <cell>12.879</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_4_[13]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.201</cell>
 <cell>12.678</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.678</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD</cell>
 <cell>3.933</cell>
 <cell></cell>
 <cell>7.036</cell>
 <cell></cell>
 <cell>7.036</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>7.036</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>2.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.113</cell>
 <cell>2.173</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>2.370</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>2.543</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.266</cell>
 <cell>2.809</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.144</cell>
 <cell>2.953</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.150</cell>
 <cell>3.103</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>1.313</cell>
 <cell>4.416</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.906</cell>
 <cell>5.322</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.714</cell>
 <cell>7.036</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>7.036</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.036</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>2.769</cell>
 <cell>7.287</cell>
 <cell>5.634</cell>
 <cell>12.921</cell>
 <cell>0.045</cell>
 <cell>2.713</cell>
 <cell>-0.101</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[3].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>2.220</cell>
 <cell>7.842</cell>
 <cell>5.085</cell>
 <cell>12.927</cell>
 <cell>0.045</cell>
 <cell>2.158</cell>
 <cell>-0.107</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[2].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>2.185</cell>
 <cell>7.879</cell>
 <cell>5.050</cell>
 <cell>12.929</cell>
 <cell>0.045</cell>
 <cell>2.121</cell>
 <cell>-0.109</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine_1_:ALn</cell>
 <cell>1.711</cell>
 <cell>7.990</cell>
 <cell>4.576</cell>
 <cell>12.566</cell>
 <cell>0.280</cell>
 <cell>2.010</cell>
 <cell>0.019</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine_0_:ALn</cell>
 <cell>1.711</cell>
 <cell>7.990</cell>
 <cell>4.576</cell>
 <cell>12.566</cell>
 <cell>0.280</cell>
 <cell>2.010</cell>
 <cell>0.019</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.921</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.634</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>7.287</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>1.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>2.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>2.174</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.193</cell>
 <cell>2.367</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>2.540</cell>
 <cell>72</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.325</cell>
 <cell>2.865</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.060</cell>
 <cell>2.925</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:EN</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.643</cell>
 <cell>5.568</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:IPENn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLKEN</cell>
 <cell>+</cell>
 <cell>0.038</cell>
 <cell>5.606</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4_enum_fir_g4/fir_enum_g4_0/taps_tap[7]_a_tap/mac_enum_0/adder2_adder2_0/mac_0/mac_0/U0/CDSEL_AL_N_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.028</cell>
 <cell>5.634</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.634</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.923</cell>
 <cell>11.923</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.137</cell>
 <cell>12.060</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.114</cell>
 <cell>12.174</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.200</cell>
 <cell>12.374</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>12.547</cell>
 <cell>27</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>12.895</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLKEN</cell>
 <cell>+</cell>
 <cell>0.041</cell>
 <cell>12.936</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_CLK</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4_enum_fir_g4/fir_enum_g4_0/taps_tap[7]_a_tap/mac_enum_0/adder2_adder2_0/mac_0/mac_0/U0/CDSEL_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.030</cell>
 <cell>12.966</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:MACC_IP</cell>
 <cell>-</cell>
 <cell>0.045</cell>
 <cell>12.921</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.921</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to Adaptive_FIR_0/CCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>4.284</cell>
 <cell></cell>
 <cell>6.407</cell>
 <cell></cell>
 <cell>0.220</cell>
 <cell>4.428</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[5]</cell>
 <cell>4.274</cell>
 <cell></cell>
 <cell>6.397</cell>
 <cell></cell>
 <cell>0.213</cell>
 <cell>4.411</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>4.229</cell>
 <cell></cell>
 <cell>6.343</cell>
 <cell></cell>
 <cell>0.220</cell>
 <cell>4.364</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[5]</cell>
 <cell>4.219</cell>
 <cell></cell>
 <cell>6.333</cell>
 <cell></cell>
 <cell>0.213</cell>
 <cell>4.347</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[0]</cell>
 <cell>3.898</cell>
 <cell></cell>
 <cell>6.021</cell>
 <cell></cell>
 <cell>0.255</cell>
 <cell>4.077</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>6.407</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>0.224</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>0.326</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.937</cell>
 <cell>1.263</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.151</cell>
 <cell>1.414</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.200</cell>
 <cell>1.614</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>1.787</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.336</cell>
 <cell>2.123</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.074</cell>
 <cell>2.197</cell>
 <cell>99</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m12:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0_genblk1_DUT_INPLACE_twid_wA_w[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.592</cell>
 <cell>2.789</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m12:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>2.891</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.N_140_i:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m12</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.645</cell>
 <cell>3.536</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.N_140_i:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>3.675</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_0:C</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/N_140_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.609</cell>
 <cell>4.284</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.195</cell>
 <cell>4.479</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_1:B</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m145_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.415</cell>
 <cell>4.894</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.139</cell>
 <cell>5.033</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m150:C</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m145_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>5.194</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m150:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.155</cell>
 <cell>5.349</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m151:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m150</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.295</cell>
 <cell>5.644</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m151:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.143</cell>
 <cell>5.787</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/CFG_21:B</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidData_w[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.436</cell>
 <cell>6.223</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/CFG_21:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2_IP_BC</cell>
 <cell>+</cell>
 <cell>0.138</cell>
 <cell>6.361</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/B_DIN_net[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.046</cell>
 <cell>6.407</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.407</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.224</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.102</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.937</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.151</cell>
 <cell>N/C</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.199</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/FF_24:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.314</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/FF_24:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.041</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/B_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>-</cell>
 <cell>0.220</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET Adaptive_FIR_0/CCC_0/GL0 to COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
