<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.8.1.12</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)</text>
<text>Date: Mon Sep 11 19:38:36 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>5.290</cell>
 <cell>189.036</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>9.883</cell>
 <cell>7.036</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>4.428</cell>
 <cell>225.836</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/CCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_0_[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_1_[1]:D</cell>
 <cell>0.445</cell>
 <cell>0.421</cell>
 <cell>4.482</cell>
 <cell>4.061</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine_2_[5]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine_3_[5]:D</cell>
 <cell>0.450</cell>
 <cell>0.423</cell>
 <cell>4.515</cell>
 <cell>4.092</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine_2_[9]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine_3_[9]:D</cell>
 <cell>0.438</cell>
 <cell>0.423</cell>
 <cell>4.515</cell>
 <cell>4.092</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine_2_[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine_3_[2]:D</cell>
 <cell>0.440</cell>
 <cell>0.424</cell>
 <cell>4.524</cell>
 <cell>4.100</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/rAmsb_r1:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/rAmsb_r2:D</cell>
 <cell>0.445</cell>
 <cell>0.424</cell>
 <cell>4.466</cell>
 <cell>4.042</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_0_[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_1_[1]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.061</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.421</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.700</cell>
 <cell>2.700</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.891</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>3.051</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>3.323</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>3.566</cell>
 <cell>67</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_0_[1]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.471</cell>
 <cell>4.037</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_0_[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.089</cell>
 <cell>4.126</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_1_[1]:D</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/bfly_0/ctrl_dly_0/delayLine_0_[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>4.482</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.482</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.700</cell>
 <cell>2.700</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.891</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>3.051</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB9:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>3.323</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB9:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>3.566</cell>
 <cell>67</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_1_[1]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB9_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.495</cell>
 <cell>4.061</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_1_[1]:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.061</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.061</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD</cell>
 <cell>5.524</cell>
 <cell></cell>
 <cell>9.883</cell>
 <cell></cell>
 <cell>9.883</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.883</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.700</cell>
 <cell>2.700</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.891</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.160</cell>
 <cell>3.051</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.279</cell>
 <cell>3.330</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>3.573</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>3.946</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.203</cell>
 <cell>4.149</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.210</cell>
 <cell>4.359</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>1.787</cell>
 <cell>6.146</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.274</cell>
 <cell>7.420</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.463</cell>
 <cell>9.883</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>9.883</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.883</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.700</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>1.228</cell>
 <cell>1.210</cell>
 <cell>5.249</cell>
 <cell>4.039</cell>
 <cell>0.000</cell>
 <cell>-0.018</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>1.228</cell>
 <cell>1.210</cell>
 <cell>5.249</cell>
 <cell>4.039</cell>
 <cell>0.000</cell>
 <cell>-0.018</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>1.228</cell>
 <cell>1.220</cell>
 <cell>5.249</cell>
 <cell>4.029</cell>
 <cell>0.000</cell>
 <cell>-0.008</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[6].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>1.332</cell>
 <cell>1.239</cell>
 <cell>5.357</cell>
 <cell>4.118</cell>
 <cell>-0.048</cell>
 <cell>-0.141</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[5].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>1.568</cell>
 <cell>1.479</cell>
 <cell>5.593</cell>
 <cell>4.114</cell>
 <cell>-0.048</cell>
 <cell>-0.137</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.249</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>4.039</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.210</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.700</cell>
 <cell>2.700</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.891</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>3.052</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB16:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.278</cell>
 <cell>3.330</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB16:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>3.573</cell>
 <cell>25</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB16_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.448</cell>
 <cell>4.021</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>4.105</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.144</cell>
 <cell>5.249</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.249</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.700</cell>
 <cell>2.700</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.191</cell>
 <cell>2.891</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.161</cell>
 <cell>3.052</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.273</cell>
 <cell>3.325</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>3.568</cell>
 <cell>72</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.471</cell>
 <cell>4.039</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>4.039</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.039</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to Adaptive_FIR_0/CCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</cell>
 <cell>0.460</cell>
 <cell></cell>
 <cell>3.426</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</cell>
 <cell>0.453</cell>
 <cell></cell>
 <cell>3.419</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:D</cell>
 <cell>0.470</cell>
 <cell></cell>
 <cell>3.427</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/tick1:D</cell>
 <cell>0.512</cell>
 <cell></cell>
 <cell>3.469</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/pulse:D</cell>
 <cell>0.584</cell>
 <cell></cell>
 <cell>3.541</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.426</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>0.316</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.143</cell>
 <cell>0.459</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.315</cell>
 <cell>1.774</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>1.987</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>2.259</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>2.502</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.464</cell>
 <cell>2.966</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>3.050</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/delayLine_0_</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.376</cell>
 <cell>3.426</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.426</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.143</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.315</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.213</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.272</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.243</cell>
 <cell>N/C</cell>
 <cell>6</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.478</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET Adaptive_FIR_0/CCC_0/GL0 to COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
