<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.8.1.12</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)</text>
<text>Date: Mon Sep 11 19:38:32 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>7.625</cell>
 <cell>131.148</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>6.724</cell>
 <cell>10.392</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>6.382</cell>
 <cell>156.691</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/CCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[10][17]:D</cell>
 <cell>7.339</cell>
 <cell>2.375</cell>
 <cell>11.528</cell>
 <cell>13.903</cell>
 <cell>0.254</cell>
 <cell>7.625</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][17]:D</cell>
 <cell>7.339</cell>
 <cell>2.375</cell>
 <cell>11.528</cell>
 <cell>13.903</cell>
 <cell>0.254</cell>
 <cell>7.625</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_4_[13]:D</cell>
 <cell>7.370</cell>
 <cell>2.383</cell>
 <cell>11.533</cell>
 <cell>13.916</cell>
 <cell>0.254</cell>
 <cell>7.617</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/add_index[1]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/filter_coefficient_temp_5_[13]:D</cell>
 <cell>7.370</cell>
 <cell>2.383</cell>
 <cell>11.533</cell>
 <cell>13.916</cell>
 <cell>0.254</cell>
 <cell>7.617</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[6][17]:D</cell>
 <cell>7.339</cell>
 <cell>2.387</cell>
 <cell>11.528</cell>
 <cell>13.915</cell>
 <cell>0.254</cell>
 <cell>7.613</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[10][17]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.903</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>11.528</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.375</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.784</cell>
 <cell>2.784</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>2.981</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>3.146</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB11:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.278</cell>
 <cell>3.424</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB11:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>3.675</cell>
 <cell>69</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB11_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.514</cell>
 <cell>4.189</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>4.276</cell>
 <cell>56</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[3]_0_sqmuxa_0_a2_0_a4:C</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[0]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.702</cell>
 <cell>4.978</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[3]_0_sqmuxa_0_a2_0_a4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.202</cell>
 <cell>5.180</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_5[5]:A</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_259</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.999</cell>
 <cell>6.179</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_5[5]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.158</cell>
 <cell>6.337</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_5_RNILJPF1[5]:B</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_5[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.429</cell>
 <cell>6.766</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_5_RNILJPF1[5]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.100</cell>
 <cell>6.866</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/CFG_11:C</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_29_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.977</cell>
 <cell>7.843</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/CFG_11:IPC</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3_IP_BCD</cell>
 <cell>+</cell>
 <cell>0.208</cell>
 <cell>8.051</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/INST_MACC_IP:B[5]</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28_0]/U0/B_net[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.060</cell>
 <cell>8.111</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/INST_MACC_IP:P[17]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MACC_IP</cell>
 <cell>+</cell>
 <cell>2.288</cell>
 <cell>10.399</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[10][17]:D</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2[17]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.129</cell>
 <cell>11.528</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.528</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.784</cell>
 <cell>12.784</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>12.981</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>13.146</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB8:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.283</cell>
 <cell>13.429</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB8:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>13.680</cell>
 <cell>26</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[10][17]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB8_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.477</cell>
 <cell>14.157</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[10][17]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>13.903</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.903</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD</cell>
 <cell>5.898</cell>
 <cell></cell>
 <cell>10.392</cell>
 <cell></cell>
 <cell>10.392</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.392</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.784</cell>
 <cell>2.784</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>2.981</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YNn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.165</cell>
 <cell>3.146</cell>
 <cell>14</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.288</cell>
 <cell>3.434</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>3.684</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.385</cell>
 <cell>4.069</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>4.278</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>4.494</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_010_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_010_IP</cell>
 <cell>+</cell>
 <cell>1.913</cell>
 <cell>6.407</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.319</cell>
 <cell>7.726</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.666</cell>
 <cell>10.392</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.392</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.392</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.784</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>4.009</cell>
 <cell>6.080</cell>
 <cell>8.159</cell>
 <cell>14.239</cell>
 <cell>0.056</cell>
 <cell>3.920</cell>
 <cell>-0.145</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[3].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>3.215</cell>
 <cell>6.884</cell>
 <cell>7.365</cell>
 <cell>14.249</cell>
 <cell>0.056</cell>
 <cell>3.116</cell>
 <cell>-0.155</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[2].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>3.165</cell>
 <cell>6.935</cell>
 <cell>7.315</cell>
 <cell>14.250</cell>
 <cell>0.056</cell>
 <cell>3.065</cell>
 <cell>-0.156</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine_1_:ALn</cell>
 <cell>2.479</cell>
 <cell>7.141</cell>
 <cell>6.629</cell>
 <cell>13.770</cell>
 <cell>0.353</cell>
 <cell>2.859</cell>
 <cell>0.027</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine_0_:ALn</cell>
 <cell>2.479</cell>
 <cell>7.141</cell>
 <cell>6.629</cell>
 <cell>13.770</cell>
 <cell>0.353</cell>
 <cell>2.859</cell>
 <cell>0.027</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.239</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>8.159</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.080</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.784</cell>
 <cell>2.784</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>2.981</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>3.147</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.281</cell>
 <cell>3.428</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.251</cell>
 <cell>3.679</cell>
 <cell>72</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB14_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.471</cell>
 <cell>4.150</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>4.237</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:EN</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.825</cell>
 <cell>8.062</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:IPENn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLKEN</cell>
 <cell>+</cell>
 <cell>0.056</cell>
 <cell>8.118</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4_enum_fir_g4/fir_enum_g4_0/taps_tap[7]_a_tap/mac_enum_0/adder2_adder2_0/mac_0/mac_0/U0/CDSEL_AL_N_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.041</cell>
 <cell>8.159</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.159</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.784</cell>
 <cell>12.784</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.197</cell>
 <cell>12.981</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.166</cell>
 <cell>13.147</cell>
 <cell>10</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.291</cell>
 <cell>13.438</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>13.688</cell>
 <cell>27</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.504</cell>
 <cell>14.192</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/FF_5:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLKEN</cell>
 <cell>+</cell>
 <cell>0.059</cell>
 <cell>14.251</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_CLK</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4_enum_fir_g4/fir_enum_g4_0/taps_tap[7]_a_tap/mac_enum_0/adder2_adder2_0/mac_0/mac_0/U0/CDSEL_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.044</cell>
 <cell>14.295</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:MACC_IP</cell>
 <cell>-</cell>
 <cell>0.056</cell>
 <cell>14.239</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>14.239</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to Adaptive_FIR_0/CCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>6.217</cell>
 <cell></cell>
 <cell>9.294</cell>
 <cell></cell>
 <cell>0.277</cell>
 <cell>6.382</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[5]</cell>
 <cell>6.204</cell>
 <cell></cell>
 <cell>9.281</cell>
 <cell></cell>
 <cell>0.268</cell>
 <cell>6.360</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>6.139</cell>
 <cell></cell>
 <cell>9.205</cell>
 <cell></cell>
 <cell>0.277</cell>
 <cell>6.293</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[5]</cell>
 <cell>6.126</cell>
 <cell></cell>
 <cell>9.192</cell>
 <cell></cell>
 <cell>0.268</cell>
 <cell>6.271</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[0]</cell>
 <cell>5.661</cell>
 <cell></cell>
 <cell>8.738</cell>
 <cell></cell>
 <cell>0.321</cell>
 <cell>5.870</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>9.294</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.326</cell>
 <cell>0.326</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.147</cell>
 <cell>0.473</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.356</cell>
 <cell>1.829</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>2.050</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.292</cell>
 <cell>2.342</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>2.592</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.485</cell>
 <cell>3.077</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.108</cell>
 <cell>3.185</cell>
 <cell>99</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m12:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0_genblk1_DUT_INPLACE_twid_wA_w[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.863</cell>
 <cell>4.048</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m12:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.147</cell>
 <cell>4.195</cell>
 <cell>10</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.N_140_i:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m12</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.933</cell>
 <cell>5.128</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.N_140_i:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.202</cell>
 <cell>5.330</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_0:C</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/N_140_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.881</cell>
 <cell>6.211</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.282</cell>
 <cell>6.493</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_1:B</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m145_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.600</cell>
 <cell>7.093</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m145_1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.202</cell>
 <cell>7.295</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m150:C</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m145_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.232</cell>
 <cell>7.527</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m150:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.225</cell>
 <cell>7.752</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m151:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m150</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.430</cell>
 <cell>8.182</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m151:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>8.391</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/CFG_21:B</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidData_w[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.635</cell>
 <cell>9.026</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/CFG_21:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2_IP_BC</cell>
 <cell>+</cell>
 <cell>0.201</cell>
 <cell>9.227</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/B_DIN_net[5]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>9.294</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>9.294</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.326</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.147</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.356</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YSn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GB</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>N/C</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YNn_GSouth</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.290</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.250</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/FF_24:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.455</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/FF_24:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.059</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/B_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.085</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>-</cell>
 <cell>0.277</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET Adaptive_FIR_0/CCC_0/GL0 to COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
