BATCH:T
MGNCMPL:F
MGNTIMER:F
GEN_BEHV_MODULE:F
DESDIR:D:\test\m2s_dg0441_starter_liberov11p8_sp1_df\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\component\work\Adaptive_FIR_top\TPSRAM_1\
DESIGN:Adaptive_FIR_top_TPSRAM_1_TPSRAM
OUTFORMAT:Verilog
RESET_POLARITY:2
A_DOUT_EN_PN:RD_EN
A_DOUT_EN_POLARITY:2
A_DOUT_SRST_PN:RD_SRST_N
A_DOUT_SRST_POLARITY:2
CASCADE:0
CLKS:2
CLK_EDGE:RISE
CLOCK_PN:CLK
DATA_IN_PN:WD
DATA_OUT_PN:RD
FAM:SmartFusion2
INIT_RAM:F
LPMTYPE:LPM_RAM
PTYPE:1
RADDRESS_PN:RADDR
RCLK_EDGE:RISE
RCLOCK_PN:RCLK
RDEPTH:1024
RESET_PN:ARST_N
RE_PN:REN
RE_POLARITY:1
PMODE2:0
RWIDTH:16
SD_EXPORT_HIDDEN_PORTS:false
WADDRESS_PN:WADDR
WCLK_EDGE:RISE
WCLOCK_PN:WCLK
WDEPTH:1024
WE_PN:WEN
WE_POLARITY:1
WWIDTH:16
DEVICE:1000
