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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Tue Mar 01 12:17:18 2016
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S010T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
<row>
 <cell>Restrict SPI Pins</cell>
 <cell>No</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>E:\Release\SF2_Starter_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo\synthesis\Adaptive_FIR_top.edn</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Enable Single Event Transient mitigation</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Enable Design Separation Methodology</cell>
 <cell>false</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>2829</cell>
 <cell>12084</cell>
 <cell>23.41</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>2827</cell>
 <cell>12084</cell>
 <cell>23.39</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>693</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>2</cell>
 <cell>231</cell>
 <cell>0.87</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>2</cell>
 <cell>231</cell>
 <cell>0.87</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>0</cell>
 <cell>115</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>22</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>11</cell>
 <cell>21</cell>
 <cell>52.38</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>13</cell>
 <cell>22</cell>
 <cell>59.09</cell>
</row>
<row>
 <cell>Chip Globals</cell>
 <cell>3</cell>
 <cell>8</cell>
 <cell>37.50</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>1</cell>
 <cell>2</cell>
 <cell>50.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>0</cell>
 <cell>4</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>1965</cell>
 <cell>1963</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>396</cell>
 <cell>396</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>468</cell>
 <cell>468</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>2829</cell>
 <cell>2827</cell>
</row>
</table>
<section><name>MSS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Cortex-M3*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eNVM (256KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>TIMER*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>CAN</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>I2C</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>UART</cell>
 <cell>1</cell>
 <cell>2</cell>
</row>
<row>
 <cell>USB</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MAC</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the MSS</text>
<text></text>
<section><name>Detailed Carry Chains Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>7</cell>
 <cell>2</cell>
</row>
<row>
 <cell>8</cell>
 <cell>2</cell>
</row>
<row>
 <cell>9</cell>
 <cell>2</cell>
</row>
<row>
 <cell>11</cell>
 <cell>3</cell>
</row>
<row>
 <cell>16</cell>
 <cell>5</cell>
</row>
<row>
 <cell>17</cell>
 <cell>3</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>17</cell>
</row>
</table>
<section><name>Detailed MACC Resource Usage</name></section>
<table>
<header>
</header>
<row>
 <cell>Length</cell>
 <cell>Used</cell>
</row>
<row>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>8</cell>
 <cell>1</cell>
</row>
<row>
 <cell>Total</cell>
 <cell>4</cell>
</row>
</table>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 1</cell>
 <cell> 1</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 2</cell>
 <cell>100.00%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>2041</cell>
 <cell>INT_NET</cell>
 <cell>Net   : DATAHANDLE_FSM_0_WCLK</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>839</cell>
 <cell>INT_NET</cell>
 <cell>Net   : Adaptive_FIR_0_MSS_READY</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
<row>
 <cell>17</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/divider_i_1[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Source: NETLIST</cell>
</row>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>195</cell>
 <cell>INT_NET</cell>
 <cell>Net   : CFG0_GND_INST_NET</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: CFG0_GND_INST</cell>
</row>
<row>
 <cell>144</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_CONTROL_FSM_0_ENABLE</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_CONTROL_FSM_0/ENABLE</cell>
</row>
<row>
 <cell>128</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0_SEND_ENABLE</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/SEND_ENABLE</cell>
</row>
<row>
 <cell>125</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0/add_index[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[3]</cell>
</row>
<row>
 <cell>125</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0/add_index[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[0]</cell>
</row>
<row>
 <cell>110</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]</cell>
</row>
<row>
 <cell>109</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0/add_index[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[2]</cell>
</row>
<row>
 <cell>101</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]</cell>
</row>
<row>
 <cell>95</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]</cell>
</row>
<row>
 <cell>90</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>195</cell>
 <cell>INT_NET</cell>
 <cell>Net   : CFG0_GND_INST_NET</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: CFG0_GND_INST</cell>
</row>
<row>
 <cell>144</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_CONTROL_FSM_0_ENABLE</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_CONTROL_FSM_0/ENABLE</cell>
</row>
<row>
 <cell>128</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0_SEND_ENABLE</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/SEND_ENABLE</cell>
</row>
<row>
 <cell>125</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0/add_index[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[3]</cell>
</row>
<row>
 <cell>125</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0/add_index[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[0]</cell>
</row>
<row>
 <cell>110</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]</cell>
</row>
<row>
 <cell>109</cell>
 <cell>INT_NET</cell>
 <cell>Net   : LMS_FIR_TOP_0/LMS_ALGO_0/add_index[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: LMS_FIR_TOP_0/LMS_ALGO_0/add_index[2]</cell>
</row>
<row>
 <cell>101</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]</cell>
</row>
<row>
 <cell>95</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]</cell>
</row>
<row>
 <cell>90</cell>
 <cell>INT_NET</cell>
 <cell>Net   : COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]</cell>
</row>
</table>
</doc>
