# Microsemi Physical design constraints file

# Version: v11.8 SP1 11.8.1.12

# Design Name:  

# Input Netlist Format: EDIF 

# Family: SmartFusion2 , Die: M2S010T , Package: 484 FBGA , Speed grade: -1 

# Date generated: Mon Sep 11 19:36:06 2017 


#
# IO banks setting
#

set_iobank Bank1 -vcci 2.50 -fixed no

#
# Local clock constraints
#


#
# Region constraints
#


#
# I/O constraints
#

set_io DEVRST_N -DIRECTION INPUT -pinname R15
set_io MMUART_0_RXD -DIRECTION INPUT -pinname C22 -fixed yes
set_io MMUART_0_TXD -DIRECTION OUTPUT -pinname D21 -fixed yes

#
# Core cell constraints
#

