| Project Settings |
|---|
| Project Name | Adaptive_FIR_top_syn | Implementation Name | synthesis |
| Top Module | Adaptive_FIR_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
223 |
200 |
0 |
- |
00m:02s |
- |
11-Sep-17
4:30:01 PM |
| (premap) | Complete |
77 |
20 |
0 |
0m:00s |
0m:00s |
158MB |
11-Sep-17
4:30:03 PM |
| (fpga_mapper) | Complete |
73 |
18 |
0 |
0m:09s |
0m:09s |
227MB |
11-Sep-17
4:30:12 PM |
| Multi-srs Generator |
Complete | | | | | | | 11-Sep-17
4:30:02 PM |
| Area Summary |
|---|
| |
| Carry Cells | 378 |
Sequential Cells | 1963 |
| DSP Blocks (MACC)
(dsp_used) | 13 |
I/O Cells | 2 |
| Global Clock Buffers | 3 |
RAM1K18
(v_ram) | 11 |
| LUTs
(total_luts) | 1968 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| Adaptive_FIR_0/CCC_0/GL0 | 100.0 MHz | 117.5 MHz | 1.486 |
| Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | NA | NA |
| fft_inpl_slowClock|divider_inferred_clock[2] | 100.0 MHz | 155.7 MHz | 3.579 |
| System | 100.0 MHz | 343.0 MHz | 7.085 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 3 |
| |
|