///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: Microsemi
//
// File: FILTERCONTROL_FSM.v
// File history:
//       1.0 : Date:03/05/2013 :Initial Release
//       2.0  : Date: 29/07/2013 :11.1 SP1 Update 
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description:This FSM Controls the Filter operations and FFT operations and also controls the
// read and write operations of corresponding buffers like reading Input buffer for filter 
//operation and writing the  filterd data to Output Buffer etc.
// 
//
// Targeted device: <Family::SmartFusion2> <Die::M2S050T> <Package::896 FBGA>
// Author: Applications Engineering
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 

`timescale 1 ns/100 ps
module FILTERCONTROL_FSM(
  PCLK,
  PRESETN,
  FILTER_COMPLETE, 
  FFT_START,
  FIR_RD_ENABLE,
  WCLK,
  RCLK,
  FIR_RADDR,
  FFT_WADDR,
  SEL,
  NEW_SAMP_EN 
  );

input PCLK, PRESETN;
input FFT_START;
input SEL;
input NEW_SAMP_EN;

output FILTER_COMPLETE; 
output FIR_RD_ENABLE;
output WCLK, RCLK;
output [9:0]   FFT_WADDR;
output [9:0]   FIR_RADDR;

reg  FILTER_COMPLETE;
reg  FIR_RD_ENABLE;
reg [9:0]   FFT_WADDR;
reg [9:0]   FIR_RADDR;
reg  [1:0] fsm;             //state machine register

wire WCLK, RCLK;

assign WCLK = PCLK;
assign RCLK = PCLK;

always@(posedge PCLK or negedge PRESETN)
  if(~PRESETN)
    begin
      fsm <= 2'b00;
      FIR_RD_ENABLE <= 1'b0;
      FIR_RADDR <= 10'b0000000000;
      FFT_WADDR <= 10'b0000000000;
      FILTER_COMPLETE <=1'b0;
    end
  else
    begin
      case (fsm)
        2'b00 :  begin
                   if (SEL)
                     begin 
                       FIR_RD_ENABLE <= 1'b1;
                       FIR_RADDR <= 10'b0000000000;
                       FFT_WADDR <= 10'b0000000000;
                       fsm <= 2'b01;
                     end
                   else        
                     begin
                       fsm <= 2'b00;
                       FIR_RD_ENABLE <= 1'b0;
                     end
                   end

        2'b01 : begin   
                  if(NEW_SAMP_EN)
                    begin   
                      FIR_RADDR <= FIR_RADDR+1;    
                      FIR_RD_ENABLE <= 1'b1;
                      if(FIR_RADDR == 10'b1111111110)
                        fsm <= 2'b10;
                      else
                        fsm <= 2'b01;
                    end
                  else 
                    begin  
                      fsm <= 2'b01;  
                      FIR_RD_ENABLE <= 1'b0;
                    end  
                end


        2'b10 :  begin            
                   FIR_RD_ENABLE <= 1'b0; 
                   if (FFT_START)
                     begin 
                      FFT_WADDR <= FFT_WADDR+1; 
                      if(FFT_WADDR == 10'b1111111111)
                        begin
                          FILTER_COMPLETE <=1'b1;
                          fsm <= 2'b00;
                        end
                      else 
                        fsm <= 2'b10;                              
                      end
                  end

        default : fsm <= 2'b00;
      endcase
    end
   
endmodule