Detailed Resource Usage
Module Name,Fabric 4LUT,Fabric DFF,Interface 4LUT,Interface DFF,Single-Ended I/O,LSRAM 18K,Math (18x18),PLLs and CCCs,Chip Globals,MSS,RCOSC_50MHZ
Adaptive_FIR_0/Adaptive_FIR_MSS_0/Primitives,16,0,0,0,2,0,0,0,0,1,0
Adaptive_FIR_0/CCC_0/Primitives,0,0,0,0,0,0,0,1,1,0,0
Adaptive_FIR_0/CORERESETP_0/Primitives,2,9,0,0,0,0,0,0,1,0,0
Adaptive_FIR_0/CoreAPB3_0/Primitives,2,0,0,0,0,0,0,0,0,0,0
Adaptive_FIR_0/FABOSC_0/Primitives,0,0,0,0,0,0,0,0,0,0,1
COREFFT_0/genblk1.DUT_INPLACE/Primitives,0,50,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/Primitives,7,3,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/edge_detect_0/Primitives,0,1,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/Primitives,127,63,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/Primitives,0,16,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/Primitives,0,16,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/Primitives,0,16,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/Primitives,17,16,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/Primitives,17,16,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/Primitives,0,10,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/Primitives,0,64,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/Primitives,0,64,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/Primitives,32,106,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/Primitives,64,0,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/Primitives,73,10,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/Primitives,73,10,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/lut_0/Primitives,273,0,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/Primitives,64,128,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/Primitives,64,130,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/Primitives,4,3,0,0,0,0,0,0,1,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/Primitives,32,15,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/Primitives,4,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Primitives,15,9,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/Primitives,32,49,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/Primitives,32,48,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/init_rear_0/Primitives,1,1,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/Primitives,3,9,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/Primitives,3,3,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_2/Primitives,1,1,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Primitives,14,9,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/pre2_sync_rw_0/Primitives,0,1,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/Primitives,0,6,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/Primitives,0,14,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/Primitives,12,6,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_0/Primitives,0,3,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_2/Primitives,2,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_3/Primitives,2,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_4/Primitives,2,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/Primitives,2,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Primitives,18,12,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Primitives,10,6,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/startFFT_dly_0/Primitives,1,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/Primitives,9,10,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/startFFT_g4_dly_0/Primitives,0,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/sync_rw_1/Primitives,0,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/Primitives,20,20,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/Primitives,5,3,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/Primitives,1,2,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/Primitives,0,4,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Primitives,8,7,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Primitives,8,7,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/Primitives,0,14,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/Primitives,0,7,0,0,0,0,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/bfly_0/cmplx_0/genblk1_cmplx18_0/half_0/mx_0/g4_macc_macc_0/Primitives,0,0,72,72,0,0,2,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/bfly_0/cmplx_0/genblk1_cmplx18_0/half_1/mx_0/g4_macc_macc_0/Primitives,0,0,72,72,0,0,2,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/genblk1_outBuff_0/outBuf_0/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/genblk1_outBuff_0/outBuf_1/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/inBuf_0/genblk1_piBuf/genblk1_memP/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/inBuf_0/genblk1_piBuf/genblk1_memQ/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/inBuf_0/genblk1_poBuf/genblk1_memP/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/inBuf_0/genblk1_poBuf/genblk1_memQ/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
DATAHANDLE_FSM_0/Primitives,49,52,0,0,0,0,0,0,0,0,0
FILTERCONTROL_FSM_0/Primitives,33,23,0,0,0,0,0,0,0,0,0
LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/Primitives,0,24,0,0,0,0,0,0,0,0,0
LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/wide_coef_0/genblk1.coef_sr_0/Primitives,0,128,0,0,0,0,0,0,0,0,0
LMS_FIR_TOP_0/COREFIR_0/enum_g4_enum_fir_g4/fir_enum_g4_0/taps_tap[0]_a_tap/mac_enum_0/adder2_adder2_0/mac_0/mac_0/Primitives,0,0,288,288,0,0,8,0,0,0,0
LMS_FIR_TOP_0/LMS_ALGO_0/Primitives,783,703,0,0,0,0,0,0,0,0,0
LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28_0]/Primitives,0,0,36,36,0,0,1,0,0,0,0
LMS_FIR_TOP_0/LMS_CONTROL_FSM_0/Primitives,22,20,0,0,0,0,0,0,0,0,0
Primitives/Primitives,10,0,0,0,0,0,0,0,0,0,0
TPSRAM_0/Primitives,0,0,36,36,0,1,0,0,0,0,0
TPSRAM_1/Primitives,0,0,36,36,0,1,0,0,0,0,0
TPSRAM_2/Primitives,0,0,36,36,0,1,0,0,0,0,0
TPSRAM_3/Primitives,0,0,36,36,0,1,0,0,0,0,0
