<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFFT</name><vendor>Actel</vendor><library>DirectCore</library><version>6.4.6</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\in_place\vlog\test\user\bhvKit.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="1"><name>coreparameters.v</name><logicalName>COREFFT_LIB</logicalName><userFileType>Verilog</userFileType><vendorExtensions><isIncludeFile/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="2"><name>rtl\in_place\vlog\core\mac_lib.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\in_place\vlog\core\cmplx.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\in_place\vlog\core\kit.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="5"><name>rtl\in_place\vlog\core\fftSm.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="6"><name>rtl\streaming\vlog\core\cmplx_fft_strm.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="7"><name>rtl\streaming\vlog\core\kit_fft_strm.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="8"><name>rtl\streaming\vlog\core\mac_lib_fft_strm.v</name><logicalName>COREFFT_LIB</logicalName><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>