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<doc>
<text>SmartTime Version 11.8.1.12</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)
Date: Mon Sep 11 16:32:28 2017 </text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
</table>
<text></text>
<text></text>
<section>
<name>Coverage Summary</name>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>         4095</cell>
 <cell>          139</cell>
 <cell>         4234</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>          840</cell>
 <cell>           16</cell>
 <cell>          856</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>         4935</cell>
 <cell>          156</cell>
 <cell>         5091</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>         4095</cell>
 <cell>          139</cell>
 <cell>         4234</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>          840</cell>
 <cell>           16</cell>
 <cell>          856</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>         4935</cell>
 <cell>          156</cell>
 <cell>         5091</cell>
</row>
</table>
<section>
<name>Clock domain: </name>
<text>Adaptive_FIR_0/CCC_0/GL0</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>         4095</cell>
 <cell>           31</cell>
 <cell>         4126</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>          840</cell>
 <cell>            2</cell>
 <cell>          842</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>         4935</cell>
 <cell>           34</cell>
 <cell>         4969</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>         4095</cell>
 <cell>           31</cell>
 <cell>         4126</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>          840</cell>
 <cell>            2</cell>
 <cell>          842</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            1</cell>
 <cell>            1</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>         4935</cell>
 <cell>           34</cell>
 <cell>         4969</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text></text>
<text> - Max output delay constraint missing on port:</text>
<text>   </text>
<list>
 <item>MMUART_1_TXD</item>
</list>
<text></text>
<text> - Min output delay constraint missing on port:</text>
<text>   </text>
<list>
 <item>MMUART_1_TXD</item>
</list>
<text></text>
<text></text>
<text> - Setup uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/init_rear_0/inp_tick:D</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[10]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[11]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[12]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[13]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[4]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[5]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[6]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[7]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[8]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[9]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[10]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[11]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[12]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[13]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[4]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[5]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[6]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[7]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[8]</item>
</list>
<text></text>
<text> - Recovery uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>Adaptive_FIR_0/CORERESETP_0/RESET_N_M2F_clk_base:ALn</item>
 <item>Adaptive_FIR_0/CORERESETP_0/RESET_N_M2F_q1:ALn</item>
</list>
<text></text>
<text> - Hold uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/init_rear_0/inp_tick:D</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[10]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[11]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[12]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[13]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[4]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[5]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[6]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[7]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[8]</item>
 <item>TPSRAM_1/Adaptive_FIR_top_TPSRAM_1_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[9]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[10]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[11]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[12]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[13]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[4]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[5]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[6]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[7]</item>
 <item>TPSRAM_2/Adaptive_FIR_top_TPSRAM_2_TPSRAM_R0C0/INST_RAM1K18_IP:A_ADDR[8]</item>
</list>
<text></text>
<text> - Removal uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>Adaptive_FIR_0/CORERESETP_0/RESET_N_M2F_clk_base:ALn</item>
 <item>Adaptive_FIR_0/CORERESETP_0/RESET_N_M2F_q1:ALn</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Clock domain: </name>
<text>Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
</table>
</section>
<section>
<name>Clock domain: </name>
<text>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>            0</cell>
 <cell>           62</cell>
 <cell>           62</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>            0</cell>
 <cell>           14</cell>
 <cell>           14</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>            0</cell>
 <cell>           76</cell>
 <cell>           76</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>            0</cell>
 <cell>           62</cell>
 <cell>           62</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>            0</cell>
 <cell>           14</cell>
 <cell>           14</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>            0</cell>
 <cell>           76</cell>
 <cell>           76</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text> - Clock constraint is missing </text>
<text></text>
<text></text>
<text> - Setup uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/pulse:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/tick1:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/preRstAfterInit:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/rstAfterInit:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[6]:D</item>
</list>
<text></text>
<text> - Recovery uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/preRstAfterInit:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/rstAfterInit:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[6]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/twid_wEn:ALn</item>
</list>
<text></text>
<text> - Hold uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/pulse:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/tick1:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/preRstAfterInit:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/rstAfterInit:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5]:D</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5]:EN</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[6]:D</item>
</list>
<text></text>
<text> - Removal uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/preRstAfterInit:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/rstAfterInit:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[6]:ALn</item>
 <item>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/twid_wEn:ALn</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Clock domain: </name>
<text>gated-clocks</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>            0</cell>
 <cell>           46</cell>
 <cell>           46</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>            0</cell>
 <cell>           46</cell>
 <cell>           46</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>            0</cell>
 <cell>           46</cell>
 <cell>           46</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>            0</cell>
 <cell>           46</cell>
 <cell>           46</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text> - Clock constraint is missing </text>
<text></text>
<text></text>
<text> - Setup uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[0]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[1]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[2]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[3]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[4]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[5]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[6]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[7]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[8]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[9]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[0]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[1]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[2]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[3]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[4]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[5]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[6]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[7]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[8]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[9]:D</item>
</list>
<text></text>
<text> - Hold uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[0]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[1]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[2]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[3]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[4]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[5]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[6]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[7]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[8]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_IM_RADDR[9]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[0]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[1]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[2]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[3]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[4]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[5]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[6]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[7]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[8]:D</item>
 <item>DATAHANDLE_FSM_0/FFT_RE_RADDR[9]:D</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Input to Output</name>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<separator/>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
</table>
</section>
</section>
</doc>
