<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Max Delay Analysis
</title>
<text>SmartTime Version 11.8.1.12</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)</text>
<text>Date: Mon Sep 11 18:58:40 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>8.314</cell>
 <cell>120.279</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>8.025</cell>
 <cell>12.275</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>5.930</cell>
 <cell>168.634</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/CCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[4][23]:D</cell>
 <cell>8.034</cell>
 <cell>1.686</cell>
 <cell>13.984</cell>
 <cell>15.670</cell>
 <cell>0.254</cell>
 <cell>8.314</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[1][23]:D</cell>
 <cell>8.034</cell>
 <cell>1.686</cell>
 <cell>13.984</cell>
 <cell>15.670</cell>
 <cell>0.254</cell>
 <cell>8.314</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[0][23]:D</cell>
 <cell>8.034</cell>
 <cell>1.686</cell>
 <cell>13.984</cell>
 <cell>15.670</cell>
 <cell>0.254</cell>
 <cell>8.314</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[5][23]:D</cell>
 <cell>8.034</cell>
 <cell>1.698</cell>
 <cell>13.984</cell>
 <cell>15.682</cell>
 <cell>0.254</cell>
 <cell>8.302</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[3][23]:D</cell>
 <cell>7.998</cell>
 <cell>1.725</cell>
 <cell>13.948</cell>
 <cell>15.673</cell>
 <cell>0.254</cell>
 <cell>8.275</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[4][23]:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>15.670</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>13.984</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.686</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.858</cell>
 <cell>3.858</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.456</cell>
 <cell>4.314</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>4.492</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB21:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.602</cell>
 <cell>5.094</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB21:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>5.410</cell>
 <cell>33</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB21_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.540</cell>
 <cell>5.950</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>6.037</cell>
 <cell>9</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_0_sqmuxa_0_a2_0_a4:B</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/mul_index[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.425</cell>
 <cell>6.462</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_0_sqmuxa_0_a2_0_a4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.202</cell>
 <cell>6.664</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/input_reg_7__RNIVJH11[10]:D</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_255</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.909</cell>
 <cell>8.573</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/input_reg_7__RNIVJH11[10]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.158</cell>
 <cell>8.731</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_3_RNI98PJ1[10]:A</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_3676_i_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.229</cell>
 <cell>8.960</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/un13_correction_factor_0_iv_i_3_RNI98PJ1[10]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.225</cell>
 <cell>9.185</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/CFG_21:C</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/N_3676_i</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.940</cell>
 <cell>10.125</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/CFG_21:IPC</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3_IP_BCD</cell>
 <cell>+</cell>
 <cell>0.208</cell>
 <cell>10.333</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/INST_MACC_IP:B[10]</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28_0]/U0/B_net[10]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.058</cell>
 <cell>10.391</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2_mulonly_0[28:0]/U0/INST_MACC_IP:P[23]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MACC_IP</cell>
 <cell>+</cell>
 <cell>2.421</cell>
 <cell>12.812</cell>
 <cell>16</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[4][23]:D</cell>
 <cell>net</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[15]_2[23]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.172</cell>
 <cell>13.984</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>13.984</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.858</cell>
 <cell>13.858</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.456</cell>
 <cell>14.314</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>14.492</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB26:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.602</cell>
 <cell>15.094</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB26:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>15.410</cell>
 <cell>83</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[4][23]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB26_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.514</cell>
 <cell>15.924</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[4][23]:D</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.254</cell>
 <cell>15.670</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>15.670</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>MMUART_1_TXD</cell>
 <cell>6.004</cell>
 <cell></cell>
 <cell>12.275</cell>
 <cell></cell>
 <cell>12.275</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>12.275</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.858</cell>
 <cell>3.858</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.456</cell>
 <cell>4.314</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>4.492</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.631</cell>
 <cell>5.123</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>5.439</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.407</cell>
 <cell>5.846</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>6.055</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>6.271</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>2.019</cell>
 <cell>8.290</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.319</cell>
 <cell>9.609</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.666</cell>
 <cell>12.275</cell>
 <cell>0</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>12.275</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.275</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.858</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Recovery (ns)</cell>
 <cell>Minimum Period (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][21]:ALn</cell>
 <cell>4.424</cell>
 <cell>5.238</cell>
 <cell>10.337</cell>
 <cell>15.575</cell>
 <cell>0.353</cell>
 <cell>4.762</cell>
 <cell>-0.015</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine_6_:ALn</cell>
 <cell>4.444</cell>
 <cell>5.238</cell>
 <cell>10.357</cell>
 <cell>15.595</cell>
 <cell>0.353</cell>
 <cell>4.762</cell>
 <cell>-0.035</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q[2]:ALn</cell>
 <cell>4.446</cell>
 <cell>5.238</cell>
 <cell>10.359</cell>
 <cell>15.597</cell>
 <cell>0.353</cell>
 <cell>4.762</cell>
 <cell>-0.037</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine_1_[0]:ALn</cell>
 <cell>4.444</cell>
 <cell>5.238</cell>
 <cell>10.357</cell>
 <cell>15.595</cell>
 <cell>0.353</cell>
 <cell>4.762</cell>
 <cell>-0.035</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/tc:ALn</cell>
 <cell>4.446</cell>
 <cell>5.238</cell>
 <cell>10.359</cell>
 <cell>15.597</cell>
 <cell>0.353</cell>
 <cell>4.762</cell>
 <cell>-0.037</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][21]:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>15.575</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.337</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.238</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.858</cell>
 <cell>3.858</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.456</cell>
 <cell>4.314</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>4.492</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.600</cell>
 <cell>5.092</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>5.408</cell>
 <cell>55</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.505</cell>
 <cell>5.913</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>6.000</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.476</cell>
 <cell>8.476</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>8.850</cell>
 <cell>27</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.602</cell>
 <cell>9.452</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>9.768</cell>
 <cell>30</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][21]:ALn</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int_RNIC4GE/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.569</cell>
 <cell>10.337</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.337</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>10.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.858</cell>
 <cell>13.858</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.456</cell>
 <cell>14.314</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>14.492</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB30:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.606</cell>
 <cell>15.098</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB30:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.316</cell>
 <cell>15.414</cell>
 <cell>79</cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][21]:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB30_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.514</cell>
 <cell>15.928</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>LMS_FIR_TOP_0/LMS_ALGO_0/correction_factor[2][21]:ALn</cell>
 <cell>Library recovery time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>-</cell>
 <cell>0.353</cell>
 <cell>15.575</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>15.575</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to Adaptive_FIR_0/CCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Setup (ns)</cell>
 <cell>Minimum Period (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[2]</cell>
 <cell>5.766</cell>
 <cell></cell>
 <cell>10.394</cell>
 <cell></cell>
 <cell>0.298</cell>
 <cell>5.930</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[2]</cell>
 <cell>5.767</cell>
 <cell></cell>
 <cell>10.395</cell>
 <cell></cell>
 <cell>0.284</cell>
 <cell>5.917</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[2]</cell>
 <cell>5.645</cell>
 <cell></cell>
 <cell>10.273</cell>
 <cell></cell>
 <cell>0.298</cell>
 <cell>5.809</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[2]</cell>
 <cell>5.646</cell>
 <cell></cell>
 <cell>10.274</cell>
 <cell></cell>
 <cell>0.284</cell>
 <cell>5.796</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[11]</cell>
 <cell>5.574</cell>
 <cell></cell>
 <cell>10.202</cell>
 <cell></cell>
 <cell>0.229</cell>
 <cell>5.669</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[2]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>10.394</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.322</cell>
 <cell>0.322</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>0.543</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.290</cell>
 <cell>2.833</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>3.207</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.595</cell>
 <cell>3.802</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB0:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.317</cell>
 <cell>4.119</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB0_rgbl_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.509</cell>
 <cell>4.628</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>4.715</cell>
 <cell>97</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m3:C</cell>
 <cell>net</cell>
 <cell>COREFFT_0_genblk1_DUT_INPLACE_twid_wA_w[1]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.289</cell>
 <cell>6.004</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m3:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.202</cell>
 <cell>6.206</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m79_4_1_0:D</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m3</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.730</cell>
 <cell>6.936</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m79_4_1_0:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.332</cell>
 <cell>7.268</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m79_4_1_1:D</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m79_4_1_0</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.234</cell>
 <cell>7.502</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m79_4_1_1:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.209</cell>
 <cell>7.711</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m79_4:B</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m79_4_1_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.303</cell>
 <cell>8.014</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m79_4:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG4</cell>
 <cell>+</cell>
 <cell>0.319</cell>
 <cell>8.333</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m84:C</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m79_4</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.669</cell>
 <cell>9.002</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m84:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.143</cell>
 <cell>9.145</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m85:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/lut_0/m84</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.099</cell>
 <cell>9.244</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m85:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG3</cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>9.331</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/CFG_9:B</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidData_w[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.796</cell>
 <cell>10.127</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/CFG_9:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2_IP_BC</cell>
 <cell>+</cell>
 <cell>0.201</cell>
 <cell>10.328</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[2]</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/B_DIN_net[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.066</cell>
 <cell>10.394</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>10.394</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.322</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.290</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.374</cell>
 <cell>N/C</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.603</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:YL</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.317</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/FF_24:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/divider_i_0[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.491</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/FF_24:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.059</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram_smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/B_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.085</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[2]</cell>
 <cell>Library setup time</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>-</cell>
 <cell>0.298</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Setup</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Recovery</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET Adaptive_FIR_0/CCC_0/GL0 to COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
