`timescale 1 ns/100 ps
// Version: v11.8 SP1 11.8.1.12


module Adaptive_FIR_top_COREFFT_0_ram_smGen(
       DI,
       DO,
       WADDR,
       RADDR,
       WRB,
       RDB,
       WCLOCK,
       RCLOCK
    );
input  [31:0] DI;
output [31:0] DO;
input  [6:0] WADDR;
input  [6:0] RADDR;
input  WRB;
input  RDB;
input  WCLOCK;
input  RCLOCK;

    wire VCC, GND, ADLIB_VCC;
    wire GND_power_net1;
    wire VCC_power_net1;
    assign GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign ADLIB_VCC = VCC_power_net1;
    
    RAM1K18 Adaptive_FIR_top_COREFFT_0_ram_smGen_R0C0 (.A_DOUT({nc0, 
        DO[31], DO[30], DO[29], DO[28], DO[27], DO[26], DO[25], DO[24], 
        nc1, DO[23], DO[22], DO[21], DO[20], DO[19], DO[18], DO[17], 
        DO[16]}), .B_DOUT({nc2, DO[15], DO[14], DO[13], DO[12], DO[11], 
        DO[10], DO[9], DO[8], nc3, DO[7], DO[6], DO[5], DO[4], DO[3], 
        DO[2], DO[1], DO[0]}), .BUSY(), .A_CLK(RCLOCK), .A_DOUT_CLK(
        RCLOCK), .A_ARST_N(VCC), .A_DOUT_EN(VCC), .A_BLK({RDB, VCC, 
        VCC}), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .A_DIN({GND, 
        DI[31], DI[30], DI[29], DI[28], DI[27], DI[26], DI[25], DI[24], 
        GND, DI[23], DI[22], DI[21], DI[20], DI[19], DI[18], DI[17], 
        DI[16]}), .A_ADDR({GND, GND, RADDR[6], RADDR[5], RADDR[4], 
        RADDR[3], RADDR[2], RADDR[1], RADDR[0], GND, GND, GND, GND, 
        GND}), .A_WEN({VCC, VCC}), .B_CLK(WCLOCK), .B_DOUT_CLK(RCLOCK), 
        .B_ARST_N(VCC), .B_DOUT_EN(VCC), .B_BLK({WRB, VCC, VCC}), 
        .B_DOUT_ARST_N(VCC), .B_DOUT_SRST_N(VCC), .B_DIN({GND, DI[15], 
        DI[14], DI[13], DI[12], DI[11], DI[10], DI[9], DI[8], GND, 
        DI[7], DI[6], DI[5], DI[4], DI[3], DI[2], DI[1], DI[0]}), 
        .B_ADDR({GND, GND, WADDR[6], WADDR[5], WADDR[4], WADDR[3], 
        WADDR[2], WADDR[1], WADDR[0], GND, GND, GND, GND, GND}), 
        .B_WEN({VCC, VCC}), .A_EN(VCC), .A_DOUT_LAT(GND), .A_WIDTH({
        VCC, GND, VCC}), .A_WMODE(GND), .B_EN(VCC), .B_DOUT_LAT(GND), 
        .B_WIDTH({VCC, GND, VCC}), .B_WMODE(GND), .SII_LOCK(GND));
    GND GND_power_inst1 (.Y(GND_power_net1));
    VCC VCC_power_inst1 (.Y(VCC_power_net1));
    
endmodule
