//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sun Sep 10 21:57:43 2017
// Version: v11.8 SP1 11.8.1.12
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// LMS_FIR_TOP
module LMS_FIR_TOP(
    // Inputs
    ARST_N,
    CLK,
    INPUT_SIGNAL,
    START,
    // Outputs
    COEF_ON,
    ERROR,
    FIRO
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input          ARST_N;
input          CLK;
input  [15:0]  INPUT_SIGNAL;
input          START;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output         COEF_ON;
output [15:0]  ERROR;
output [25:10] FIRO;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire           ARST_N;
wire           CLK;
wire           COEF_ON_net_0;
wire   [15:0]  ERROR_net_0;
wire   [25:10] FIRO_net_0;
wire   [15:0]  INPUT_SIGNAL;
wire           LMS_ALGO_0_COEF_DONE;
wire   [15:0]  LMS_ALGO_0_DELAYED_SIGNAL;
wire   [15:0]  LMS_ALGO_0_FILTER_COEF_OUT;
wire           LMS_ALGO_0_SEND_ENABLE;
wire           LMS_CONTROL_FSM_0_ADD_ENABLE;
wire   [4:0]   LMS_CONTROL_FSM_0_COUNT;
wire           LMS_CONTROL_FSM_0_DATAI_VALID;
wire           LMS_CONTROL_FSM_0_ENABLE;
wire           LMS_CONTROL_FSM_0_MUL_ENABLE;
wire           LMS_CONTROL_FSM_0_OUTPUT_ENABLE;
wire           LMS_CONTROL_FSM_0_UPDATE_ENABLE;
wire           START;
wire           COEF_ON_net_1;
wire   [15:0]  ERROR_net_1;
wire   [25:10] FIRO_net_1;
wire   [34:26] FIRO_slice_0;
wire   [9:0]   FIRO_slice_1;
wire   [34:0]  FIRO_net_2;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire           VCC_net;
wire           GND_net;
wire   [3:0]   COEF_SEL_const_net_0;
wire   [11:0]  SAMPLE_ID_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net               = 1'b1;
assign GND_net               = 1'b0;
assign COEF_SEL_const_net_0  = 4'h0;
assign SAMPLE_ID_const_net_0 = 12'h000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign COEF_ON_net_1 = COEF_ON_net_0;
assign COEF_ON       = COEF_ON_net_1;
assign ERROR_net_1   = ERROR_net_0;
assign ERROR[15:0]   = ERROR_net_1;
assign FIRO_net_1    = FIRO_net_0;
assign FIRO[25:10]   = FIRO_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign FIRO_net_0   = FIRO_net_2[25:10];
assign FIRO_slice_0 = FIRO_net_2[34:26];
assign FIRO_slice_1 = FIRO_net_2[9:0];
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------LMS_FIR_TOP_COREFIR_0_COREFIR   -   Actel:DirectCore:COREFIR:8.6.101
LMS_FIR_TOP_COREFIR_0_COREFIR #( 
        .CFG_ARCH      ( 1 ),
        .CLOCK_RATE    ( 10000000 ),
        .COEF_RAM      ( 0 ),
        .COEF_SETS     ( 1 ),
        .COEF_SYMM     ( 0 ),
        .COEF_TYPE     ( 1 ),
        .COEF_UNSIGN   ( 0 ),
        .COEF_WIDTH    ( 16 ),
        .DATA_RAM      ( 0 ),
        .DATA_UNSIGN   ( 0 ),
        .DATA_WIDTH    ( 16 ),
        .DIE_SIZE      ( 25 ),
        .FPGA_FAMILY   ( 19 ),
        .ID_WIDTH      ( 12 ),
        .INP_REG       ( 0 ),
        .L             ( 2 ),
        .M             ( 2 ),
        .RADIX         ( 10 ),
        .SAMPLE_RATE   ( 1000000 ),
        .SAMPLEID      ( 0 ),
        .SYSTOLIC      ( 0 ),
        .TAPS          ( 8 ),
        .URAM_MAXDEPTH ( 0 ) )
COREFIR_0(
        // Inputs
        .NGRST         ( ARST_N ),
        .RSTN          ( VCC_net ),
        .CLK           ( CLK ),
        .DATAI_VALID   ( LMS_CONTROL_FSM_0_DATAI_VALID ),
        .COEFI_VALID   ( LMS_ALGO_0_SEND_ENABLE ),
        .COEF_ON       ( COEF_ON_net_0 ),
        .COEF_REF      ( GND_net ), // tied to 1'b0 from definition
        .RCLK          ( VCC_net ), // tied to 1'b1 from definition
        .DATAI         ( LMS_ALGO_0_DELAYED_SIGNAL ),
        .COEFI         ( LMS_ALGO_0_FILTER_COEF_OUT ),
        .COEF_SEL      ( COEF_SEL_const_net_0 ), // tied to 4'h0 from definition
        .SAMPLE_ID     ( SAMPLE_ID_const_net_0 ), // tied to 12'h000 from definition
        // Outputs
        .COEF_REF_DONE (  ),
        .READY         (  ),
        .DATAO_VALID   (  ),
        .COEF_ON_SLOT  (  ),
        .DATAO         (  ),
        .FIRO_ID       (  ),
        .FIRO          ( FIRO_net_2 ) 
        );

//--------LMS_ALGO
LMS_ALGO LMS_ALGO_0(
        // Inputs
        .CLK             ( CLK ),
        .ARST_N          ( ARST_N ),
        .ENABLE          ( LMS_CONTROL_FSM_0_ENABLE ),
        .OUTPUT_ENABLE   ( LMS_CONTROL_FSM_0_OUTPUT_ENABLE ),
        .MUL_ENABLE      ( LMS_CONTROL_FSM_0_MUL_ENABLE ),
        .ADD_ENABLE      ( LMS_CONTROL_FSM_0_ADD_ENABLE ),
        .UPDATE_ENABLE   ( LMS_CONTROL_FSM_0_UPDATE_ENABLE ),
        .INPUT_SIGNAL    ( INPUT_SIGNAL ),
        .FIR_OUT_SIGNAL  ( FIRO_net_0 ),
        .COUNT           ( LMS_CONTROL_FSM_0_COUNT ),
        // Outputs
        .SEND_ENABLE     ( LMS_ALGO_0_SEND_ENABLE ),
        .COEF_DONE       ( LMS_ALGO_0_COEF_DONE ),
        .DELAYED_SIGNAL  ( LMS_ALGO_0_DELAYED_SIGNAL ),
        .FILTER_COEF_OUT ( LMS_ALGO_0_FILTER_COEF_OUT ),
        .ERROR           ( ERROR_net_0 ) 
        );

//--------LMS_CONTROL_FSM
LMS_CONTROL_FSM LMS_CONTROL_FSM_0(
        // Inputs
        .CLK           ( CLK ),
        .ARST_N        ( ARST_N ),
        .START         ( START ),
        .COEF_DONE     ( LMS_ALGO_0_COEF_DONE ),
        // Outputs
        .ENABLE        ( LMS_CONTROL_FSM_0_ENABLE ),
        .OUTPUT_ENABLE ( LMS_CONTROL_FSM_0_OUTPUT_ENABLE ),
        .MUL_ENABLE    ( LMS_CONTROL_FSM_0_MUL_ENABLE ),
        .ADD_ENABLE    ( LMS_CONTROL_FSM_0_ADD_ENABLE ),
        .COEF_ON       ( COEF_ON_net_0 ),
        .UPDATE_ENABLE ( LMS_CONTROL_FSM_0_UPDATE_ENABLE ),
        .DATAI_VALID   ( LMS_CONTROL_FSM_0_DATAI_VALID ),
        .COUNT         ( LMS_CONTROL_FSM_0_COUNT ) 
        );


endmodule
