//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Sun Sep 10 22:00:13 2017
// Version: v11.8 SP1 11.8.1.12
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// Adaptive_FIR_top
module Adaptive_FIR_top(
    // Inputs
    DEVRST_N,
    MMUART_1_RXD,
    // Outputs
    MMUART_1_TXD
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  DEVRST_N;
input  MMUART_1_RXD;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output MMUART_1_TXD;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          Adaptive_FIR_0_AMBA_SLAVE_0_PENABLE;
wire          Adaptive_FIR_0_AMBA_SLAVE_0_PREADY;
wire          Adaptive_FIR_0_AMBA_SLAVE_0_PSELx;
wire          Adaptive_FIR_0_AMBA_SLAVE_0_PSLVERR;
wire          Adaptive_FIR_0_AMBA_SLAVE_0_PWRITE;
wire          Adaptive_FIR_0_FIC_0_CLK;
wire          Adaptive_FIR_0_GPIO_0_M2F;
wire          Adaptive_FIR_0_GPIO_1_M2F;
wire          Adaptive_FIR_0_MSS_READY;
wire   [15:0] COREFFT_0_DATAO_IM;
wire   [15:0] COREFFT_0_DATAO_RE;
wire          COREFFT_0_OUTP_READY;
wire   [9:0]  DATAHANDLE_FSM_0_FFT_IM_RADDR;
wire   [9:0]  DATAHANDLE_FSM_0_FFT_RE_RADDR;
wire          DATAHANDLE_FSM_0_FFT_VALID;
wire          DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE;
wire   [9:0]  DATAHANDLE_FSM_0_FIR_RADDR;
wire   [9:0]  DATAHANDLE_FSM_0_INPUT_WADDR;
wire          DATAHANDLE_FSM_0_INPUT_WR_ENABLE;
wire   [15:0] DATAHANDLE_FSM_0_MEM_DATA_IN;
wire          DATAHANDLE_FSM_0_RCLK;
wire          DATAHANDLE_FSM_0_SEL;
wire          DATAHANDLE_FSM_0_WCLK;
wire          DEVRST_N;
wire   [9:0]  FILTERCONTROL_FSM_0_FFT_WADDR;
wire          FILTERCONTROL_FSM_0_FILTER_COMPLETE;
wire   [9:0]  FILTERCONTROL_FSM_0_FIR_RADDR;
wire          FILTERCONTROL_FSM_0_FIR_RD_ENABLE;
wire          FILTERCONTROL_FSM_0_RCLK;
wire          FILTERCONTROL_FSM_0_WCLK;
wire          LMS_FIR_TOP_0_COEF_ON;
wire   [15:0] LMS_FIR_TOP_0_ERROR;
wire          MMUART_1_RXD;
wire          MMUART_1_TXD_0;
wire   [15:0] TPSRAM_0_RD;
wire   [15:0] TPSRAM_1_RD;
wire   [15:0] TPSRAM_2_RD;
wire   [15:0] TPSRAM_3_RD;
wire          MMUART_1_TXD_0_net_0;
wire   [1:0]  FIR_ENABLE_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
wire   [15:0] DATAI_IM_const_net_0;
wire          GND_net;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [31:0] Adaptive_FIR_0_AMBA_SLAVE_0_PADDR;
wire   [15:0] Adaptive_FIR_0_AMBA_SLAVE_0_PADDR_0_15to0;
wire   [15:0] Adaptive_FIR_0_AMBA_SLAVE_0_PADDR_0;
wire   [31:16]Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0_31to16;
wire   [15:0] Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0_15to0;
wire   [31:0] Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0;
wire   [15:0] Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA;
wire   [31:0] Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA;
wire   [15:0] Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA_0_15to0;
wire   [15:0] Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net              = 1'b1;
assign DATAI_IM_const_net_0 = 16'h0000;
assign GND_net              = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_1_TXD_0_net_0 = MMUART_1_TXD_0;
assign MMUART_1_TXD         = MMUART_1_TXD_0_net_0;
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign FIR_ENABLE_net_0 = { Adaptive_FIR_0_GPIO_1_M2F , Adaptive_FIR_0_GPIO_0_M2F };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign Adaptive_FIR_0_AMBA_SLAVE_0_PADDR_0_15to0 = Adaptive_FIR_0_AMBA_SLAVE_0_PADDR[15:0];
assign Adaptive_FIR_0_AMBA_SLAVE_0_PADDR_0 = { Adaptive_FIR_0_AMBA_SLAVE_0_PADDR_0_15to0 };

assign Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0_31to16 = 16'h0;
assign Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0_15to0 = Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA[15:0];
assign Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0 = { Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0_31to16, Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0_15to0 };

assign Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA_0_15to0 = Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA[15:0];
assign Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA_0 = { Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA_0_15to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------Adaptive_FIR
Adaptive_FIR Adaptive_FIR_0(
        // Inputs
        .MMUART_1_RXD           ( MMUART_1_RXD ),
        .FAB_RESET_N            ( VCC_net ),
        .AMBA_SLAVE_0_PREADYS0  ( Adaptive_FIR_0_AMBA_SLAVE_0_PREADY ),
        .AMBA_SLAVE_0_PSLVERRS0 ( Adaptive_FIR_0_AMBA_SLAVE_0_PSLVERR ),
        .DEVRST_N               ( DEVRST_N ),
        .AMBA_SLAVE_0_PRDATAS0  ( Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA_0 ),
        // Outputs
        .MMUART_1_TXD           ( MMUART_1_TXD_0 ),
        .POWER_ON_RESET_N       (  ),
        .INIT_DONE              (  ),
        .AMBA_SLAVE_0_PSELS0    ( Adaptive_FIR_0_AMBA_SLAVE_0_PSELx ),
        .AMBA_SLAVE_0_PENABLES  ( Adaptive_FIR_0_AMBA_SLAVE_0_PENABLE ),
        .AMBA_SLAVE_0_PWRITES   ( Adaptive_FIR_0_AMBA_SLAVE_0_PWRITE ),
        .FIC_0_CLK              ( Adaptive_FIR_0_FIC_0_CLK ),
        .FIC_0_LOCK             (  ),
        .MSS_READY              ( Adaptive_FIR_0_MSS_READY ),
        .GPIO_0_M2F             ( Adaptive_FIR_0_GPIO_0_M2F ),
        .GPIO_1_M2F             ( Adaptive_FIR_0_GPIO_1_M2F ),
        .AMBA_SLAVE_0_PADDRS    ( Adaptive_FIR_0_AMBA_SLAVE_0_PADDR ),
        .AMBA_SLAVE_0_PWDATAS   ( Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA ) 
        );

//--------Adaptive_FIR_top_COREFFT_0_COREFFT   -   Actel:DirectCore:COREFFT:7.0.104
Adaptive_FIR_top_COREFFT_0_COREFFT #( 
        .CFG_ARCH      ( 1 ),
        .DATA_BITS     ( 18 ),
        .FFT_SIZE      ( 256 ),
        .FPGA_FAMILY   ( 19 ),
        .INVERSE       ( 0 ),
        .MEMBUF        ( 1 ),
        .ORDER         ( 0 ),
        .POINTS        ( 256 ),
        .SCALE         ( 0 ),
        .SCALE_EXP_ON  ( 0 ),
        .SCALE_ON      ( 1 ),
        .SCALE_SCH     ( 255 ),
        .TWID_BITS     ( 18 ),
        .URAM_MAXDEPTH ( 0 ),
        .WIDTH         ( 16 ) )
COREFFT_0(
        // Inputs
        .CLK          ( FILTERCONTROL_FSM_0_RCLK ),
        .NGRST        ( Adaptive_FIR_0_MSS_READY ),
        .DATAI_VALID  ( DATAHANDLE_FSM_0_FFT_VALID ),
        .READ_OUTP    ( VCC_net ), // tied to 1'b1 from definition
        .START        ( VCC_net ), // tied to 1'b1 from definition
        .INVERSE_STRM ( GND_net ), // tied to 1'b0 from definition
        .REFRESH      ( GND_net ), // tied to 1'b0 from definition
        .CLKEN        ( VCC_net ), // tied to 1'b1 from definition
        .RST          ( GND_net ), // tied to 1'b0 from definition
        .DATAI_IM     ( DATAI_IM_const_net_0 ),
        .DATAI_RE     ( TPSRAM_1_RD ),
        // Outputs
        .DATAO_VALID  (  ),
        .BUF_READY    (  ),
        .OUTP_READY   ( COREFFT_0_OUTP_READY ),
        .PONG         (  ),
        .OVFLOW_FLAG  (  ),
        .RFS          (  ),
        .DATAO_IM     ( COREFFT_0_DATAO_IM ),
        .DATAO_RE     ( COREFFT_0_DATAO_RE ),
        .SCALE_EXP    (  ) 
        );

//--------DATAHANDLE_FSM
DATAHANDLE_FSM DATAHANDLE_FSM_0(
        // Inputs
        .PCLK              ( Adaptive_FIR_0_FIC_0_CLK ),
        .PENABLE           ( Adaptive_FIR_0_AMBA_SLAVE_0_PENABLE ),
        .PSEL              ( Adaptive_FIR_0_AMBA_SLAVE_0_PSELx ),
        .PRESETN           ( Adaptive_FIR_0_MSS_READY ),
        .PWRITE            ( Adaptive_FIR_0_AMBA_SLAVE_0_PWRITE ),
        .FILTER_COMPLETE   ( FILTERCONTROL_FSM_0_FILTER_COMPLETE ),
        .PADDR             ( Adaptive_FIR_0_AMBA_SLAVE_0_PADDR_0 ),
        .PWDATA            ( Adaptive_FIR_0_AMBA_SLAVE_0_PWDATA_0 ),
        .FIR_DATA_OUT      ( TPSRAM_1_RD ),
        .FIR_ENABLE        ( FIR_ENABLE_net_0 ),
        .FFT_IM_DATA       ( TPSRAM_2_RD ),
        .FFT_RE_RD         ( TPSRAM_3_RD ),
        // Outputs
        .PREADY            ( Adaptive_FIR_0_AMBA_SLAVE_0_PREADY ),
        .PSLVERR           ( Adaptive_FIR_0_AMBA_SLAVE_0_PSLVERR ),
        .FIR_FFT_RD_ENABLE ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE ),
        .INPUT_WR_ENABLE   ( DATAHANDLE_FSM_0_INPUT_WR_ENABLE ),
        .WCLK              ( DATAHANDLE_FSM_0_WCLK ),
        .RCLK              ( DATAHANDLE_FSM_0_RCLK ),
        .SEL               ( DATAHANDLE_FSM_0_SEL ),
        .FFT_VALID         ( DATAHANDLE_FSM_0_FFT_VALID ),
        .PRDATA            ( Adaptive_FIR_0_AMBA_SLAVE_0_PRDATA ),
        .FFT_RE_RADDR      ( DATAHANDLE_FSM_0_FFT_RE_RADDR ),
        .INPUT_WADDR       ( DATAHANDLE_FSM_0_INPUT_WADDR ),
        .FIR_RADDR         ( DATAHANDLE_FSM_0_FIR_RADDR ),
        .FFT_IM_RADDR      ( DATAHANDLE_FSM_0_FFT_IM_RADDR ),
        .MEM_DATA_IN       ( DATAHANDLE_FSM_0_MEM_DATA_IN ) 
        );

//--------FILTERCONTROL_FSM
FILTERCONTROL_FSM FILTERCONTROL_FSM_0(
        // Inputs
        .PCLK            ( Adaptive_FIR_0_FIC_0_CLK ),
        .PRESETN         ( Adaptive_FIR_0_MSS_READY ),
        .FFT_START       ( COREFFT_0_OUTP_READY ),
        .SEL             ( DATAHANDLE_FSM_0_SEL ),
        .NEW_SAMP_EN     ( LMS_FIR_TOP_0_COEF_ON ),
        // Outputs
        .FILTER_COMPLETE ( FILTERCONTROL_FSM_0_FILTER_COMPLETE ),
        .FIR_RD_ENABLE   ( FILTERCONTROL_FSM_0_FIR_RD_ENABLE ),
        .WCLK            ( FILTERCONTROL_FSM_0_WCLK ),
        .RCLK            ( FILTERCONTROL_FSM_0_RCLK ),
        .FIR_RADDR       ( FILTERCONTROL_FSM_0_FIR_RADDR ),
        .FFT_WADDR       ( FILTERCONTROL_FSM_0_FFT_WADDR ) 
        );

//--------LMS_FIR_TOP
LMS_FIR_TOP LMS_FIR_TOP_0(
        // Inputs
        .CLK          ( Adaptive_FIR_0_FIC_0_CLK ),
        .ARST_N       ( Adaptive_FIR_0_MSS_READY ),
        .START        ( FILTERCONTROL_FSM_0_FIR_RD_ENABLE ),
        .INPUT_SIGNAL ( TPSRAM_0_RD ),
        // Outputs
        .COEF_ON      ( LMS_FIR_TOP_0_COEF_ON ),
        .ERROR        ( LMS_FIR_TOP_0_ERROR ),
        .FIRO         (  ) 
        );

//--------Adaptive_FIR_top_TPSRAM_0_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
Adaptive_FIR_top_TPSRAM_0_TPSRAM TPSRAM_0(
        // Inputs
        .WEN   ( DATAHANDLE_FSM_0_INPUT_WR_ENABLE ),
        .REN   ( FILTERCONTROL_FSM_0_FIR_RD_ENABLE ),
        .WCLK  ( DATAHANDLE_FSM_0_WCLK ),
        .RCLK  ( FILTERCONTROL_FSM_0_RCLK ),
        .WD    ( DATAHANDLE_FSM_0_MEM_DATA_IN ),
        .WADDR ( DATAHANDLE_FSM_0_INPUT_WADDR ),
        .RADDR ( FILTERCONTROL_FSM_0_FIR_RADDR ),
        // Outputs
        .RD    ( TPSRAM_0_RD ) 
        );

//--------Adaptive_FIR_top_TPSRAM_1_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
Adaptive_FIR_top_TPSRAM_1_TPSRAM TPSRAM_1(
        // Inputs
        .WEN   ( FILTERCONTROL_FSM_0_FIR_RD_ENABLE ),
        .REN   ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE ),
        .WCLK  ( FILTERCONTROL_FSM_0_RCLK ),
        .RCLK  ( DATAHANDLE_FSM_0_RCLK ),
        .WD    ( LMS_FIR_TOP_0_ERROR ),
        .WADDR ( FILTERCONTROL_FSM_0_FIR_RADDR ),
        .RADDR ( DATAHANDLE_FSM_0_FIR_RADDR ),
        // Outputs
        .RD    ( TPSRAM_1_RD ) 
        );

//--------Adaptive_FIR_top_TPSRAM_2_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
Adaptive_FIR_top_TPSRAM_2_TPSRAM TPSRAM_2(
        // Inputs
        .WEN   ( COREFFT_0_OUTP_READY ),
        .REN   ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE ),
        .WCLK  ( FILTERCONTROL_FSM_0_WCLK ),
        .RCLK  ( DATAHANDLE_FSM_0_RCLK ),
        .WD    ( COREFFT_0_DATAO_IM ),
        .WADDR ( FILTERCONTROL_FSM_0_FFT_WADDR ),
        .RADDR ( DATAHANDLE_FSM_0_FFT_IM_RADDR ),
        // Outputs
        .RD    ( TPSRAM_2_RD ) 
        );

//--------Adaptive_FIR_top_TPSRAM_3_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
Adaptive_FIR_top_TPSRAM_3_TPSRAM TPSRAM_3(
        // Inputs
        .WEN   ( COREFFT_0_OUTP_READY ),
        .REN   ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE ),
        .WCLK  ( FILTERCONTROL_FSM_0_WCLK ),
        .RCLK  ( DATAHANDLE_FSM_0_RCLK ),
        .WD    ( COREFFT_0_DATAO_RE ),
        .WADDR ( FILTERCONTROL_FSM_0_FFT_WADDR ),
        .RADDR ( DATAHANDLE_FSM_0_FFT_RE_RADDR ),
        // Outputs
        .RD    ( TPSRAM_3_RD ) 
        );


endmodule
