// ***************************************************************************/
//Actel Corporation Proprietary and Confidential
//Copyright 2011 Actel Corporation. All rights reserved.
//
//ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
//IN ADVANCE IN WRITING.
//
//Description:  CoreFIR
//              Structural MAC wrapper for G4 enumerated filter
//
//Revision Information:
//Date         Description
//26Apr2011    Initial Release
//
//SVN Revision Information:
//SVN $Revision: 14801 $
//SVN $Data: $
//
//Resolved SARs
//SAR     Date    Who         Description
//
//Notes:
//

`timescale 1 ns/100 ps


// Either cdin or cin is used statically in the enum filter.  The combined
// cascade chain input is called cascade_in whether it comes from HW cascade or
// from P output via fabric.  Explicit control is provided by cdsel:
// 0: product+registered cin; 1: product+cdin
module LMS_FIR_TOP_COREFIR_0_mac18x18_enum_g4 (
  nGrst,
  rstn,
  clk,
  en_a,
  en_b,
  en_c,
  en_p,
  mcand_a, mcand_b,
  cascade_in,
  cdsel,
  cdout,
  pout,
  cout,
  s);

  parameter CHAIN_BREAK = 0;

  input nGrst, rstn, clk, en_a, en_b, en_c, en_p;
  input [17:0] mcand_a, mcand_b;
  input [43:0] cascade_in;
  input cdsel;
  output[43:0] cdout;
  output[43:0] pout;
  output cout, s;

  wire [1:0] rstn_c;
  wire[43:0] hw_cin, hw_cdin, cdout_w;

  assign s = pout[43] & cout;
  assign cdout = CHAIN_BREAK ? pout : cdout_w;

  // Hold C register in zero state if csel==0 to prevent adding cin
  assign rstn_c  = cdsel ? 2'b00 : {rstn, rstn};
  // Just in case ground unused cin input when not in use.
  assign hw_cin  = cdsel ? 44'b0 : cascade_in;
  assign hw_cdin = cdsel ? cascade_in : 44'b0;

  MACC mac_0 (
    .CLK  ({clk,clk}),

    .A        (mcand_a),
    .A_EN     ({en_a, en_a}),
    .A_ARST_N ({nGrst,nGrst}),
    .A_SRST_N ({rstn, rstn}),
    .A_BYPASS (2'b00),      // latch

    .B        (mcand_b),
    .B_EN     ({en_b, en_b}),
    .B_ARST_N ({nGrst,nGrst}),
    .B_SRST_N ({rstn, rstn}),
    .B_BYPASS (2'b00),      // latch

    .C        (hw_cin),
    .C_EN     ({en_c, en_c}),
    .C_ARST_N ({nGrst,nGrst}),
    .C_SRST_N (rstn_c),
    .C_BYPASS (2'b00),      // latch
    .CARRYIN  (1'b0),

    .P        (pout),
    .CDOUT    (cdout_w),
    .P_EN     ({en_p, en_p}),
    .P_ARST_N ({nGrst,nGrst}),
    .P_SRST_N ({rstn, rstn}),
    .P_BYPASS (2'b00),      //latch

    .OVFL_CARRYOUT  (cout),

    .CDIN (hw_cdin),

    .SUB        (1'b0),
    .SUB_EN     (1'b1),           // en
    .SUB_AD     (1'b0),           // async data bit
    .SUB_AL_N   (1'b0),           // async load the data bit
    .SUB_SD_N   (1'b1),           // sync data bit
    .SUB_SL_N   (1'b0),           // sync load the data bit
    .SUB_BYPASS (1'b1),           // latch

    .ARSHFT17         (1'b0),
    .ARSHFT17_EN      (1'b1),           // en
    .ARSHFT17_AD      (1'b0),           // async data bit
    .ARSHFT17_AL_N    (1'b0),           // async load the data bit
    .ARSHFT17_SD_N    (1'b1),           // sync data bit
    .ARSHFT17_SL_N    (1'b0),           // sync load the data bit
    .ARSHFT17_BYPASS  (1'b1),           // latch

    // Pass 0 so, that when cdsel==0 the adder 'd' input = 0
    .FDBKSEL        (1'b0),
    .FDBKSEL_EN     (1'b1),           // en
    .FDBKSEL_AD     (1'b0),           // async data bit
    .FDBKSEL_AL_N   (1'b0),           // async load the data bit
    .FDBKSEL_SD_N   (1'b1),           // sync data bit
    .FDBKSEL_SL_N   (1'b0),           // sync load the data bit
    .FDBKSEL_BYPASS (1'b1),           // latch

    .CDSEL        (cdsel),
    .CDSEL_EN     (1'b1),           // en
    .CDSEL_AD     (1'b0),           // async data bit
    .CDSEL_AL_N   (nGrst),          // async load the data bit
    .CDSEL_SD_N   (1'b1),           // sync data bit
    .CDSEL_SL_N   (rstn),           // sync load the data bit
    .CDSEL_BYPASS (1'b0),           // latch

    .OVFL_CARRYOUT_SEL  (1'b1),       // Select carryout 1 ???

    .SIMD(1'b0),
    .DOTP(1'b0)    );

endmodule


