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KEY CAPTURE "11.8.1.12"
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KEY ProjectID "0"
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KEY UseConstraintFlowTechnology "TRUE"
KEY VendorTechnology_Family "SmartFusion2"
KEY VendorTechnology_Die "PA4M7500_TS"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "-1"
KEY VendorTechnology_DieVoltage "1.2"
KEY VendorTechnology_PART_RANGE "COM"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
KEY VendorTechnology_IO_DEFT_STD "LVCMOS25"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_25"
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
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KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "D:\test\m2s_dg0441_eval_liberov11p8_sp1_df\SF2_Eval_Adaptive_FIR_filter_Demo_DF\DesignFiles\Adaptive_FIR_filter_Demo"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "Adaptive_FIR_top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
COREAPB3_LIB
COREFIR_LIB
COREFFT_LIB
ENDLIST
LIST LIBRARY_COREAPB3_LIB
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COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_COREFIR_LIB
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COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_COREFFT_LIB
ALIAS=COREFFT_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST FileManager
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ENDFILE
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SIZE="2138"
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LIBRARY="COREFIR_LIB"
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ENDFILE
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LIBRARY="COREFIR_LIB"
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TIME="1387071736"
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ENDFILE
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TIME="1489462219"
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ENDFILE
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SIZE="734"
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ENDFILE
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SIZE="555"
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ENDFILE
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SIZE="3014"
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STATE="utd"
TIME="1505137185"
SIZE="10068"
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ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "Adaptive_FIR::work"
FILE "<project>\component\work\Adaptive_FIR\Adaptive_FIR.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "Adaptive_FIR_MSS::work"
FILE "<project>\component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST "Adaptive_FIR_top::work"
FILE "<project>\component\work\Adaptive_FIR_top\Adaptive_FIR_top.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST SynthesisConstraints
VALUE "<project>\constraint\Adaptive_FIR_top_derived_constraints.sdc,sdc"
ENDLIST
LIST TimingConstraints
VALUE "<project>\constraint\Adaptive_FIR_top_derived_constraints.sdc,sdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\Adaptive_FIR_top.edn,syn_edn)=StateSuccess
ideSYNTHESIS(<project>\synthesis\Adaptive_FIR_top.vm,syn_vm)=StateFailure
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREFIR::COREFIR_LIB"
FILE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\top\COREFIR.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\coreparameters_tgi.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\coreparameters_tgi.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_COREFFT::COREFFT_LIB"
FILE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\fft_tb_inc32.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v,tb_hdl"
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\in_place_FFT_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\coreparameters.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\fft_tb_inc32.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v,tb_hdl"
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\in_place_FFT_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\coreparameters.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST Adaptive_FIR
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST LMS_FIR_TOP_COREFIR_0_COREFIR
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\coreparameters_tgi.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v,tb_hdl"
ENDLIST
LIST Adaptive_FIR_top_COREFFT_0_COREFFT
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\fft_tb_inc32.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v,tb_hdl"
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\in_place_FFT_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\coreparameters.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST Adaptive_FIR_top
VALUE "<project>\simulation\subsystem.bfm,sim"
ENDLIST
LIST Adaptive_FIR
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST Adaptive_FIR_MSS
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
LIST LMS_FIR_TOP_COREFIR_0_COREFIR
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\coreparameters_tgi.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v,tb_hdl"
VALUE "<project>\component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v,tb_hdl"
ENDLIST
LIST Adaptive_FIR_top_COREFFT_0_COREFFT
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\fft_tb_inc32.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v,tb_hdl"
VALUE "<project>\component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\in_place_FFT_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFFT\7.0.104\coreparameters.v,tb_hdl"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1fs
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
InstantiateInSmartDesign=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="11.8_issue_resolved"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="D:\cap\sympify_bug_fix\synplify_L201609M-2_W\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="D:\Microsemi\Libero_SoC_v11.8\Modelsim\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FPExpress"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="D:\Microsemi\Libero_SoC_v11.8\Designer\bin\FPExpress.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="D:\Microsemi\Libero_SoC_v11.8\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "Adaptive_FIR::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "Adaptive_FIR_top::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\Adaptive_FIR_top.edn,syn_edn)=StateSuccess
ideSYNTHESIS(<project>\synthesis\Adaptive_FIR_top.vm,syn_vm)=StateFailure
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREFIR::COREFIR_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_COREFFT::COREFFT_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Synthesize:Adaptive_FIR_top_compile_netlist_hier_resources.csv
SmartDesign;Adaptive_FIR_top;0
StartPage;StartPage;0
ACTIVEVIEW;Adaptive_FIR_top
ENDLIST
LIST ModuleSubBlockList
LIST "Adaptive_FIR::work","component\work\Adaptive_FIR\Adaptive_FIR.v","TRUE","FALSE"
SUBBLOCK "Adaptive_FIR_CCC_0_FCCC::work","component\work\Adaptive_FIR\CCC_0\Adaptive_FIR_CCC_0_FCCC.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_FABOSC_0_OSC::work","component\work\Adaptive_FIR\FABOSC_0\Adaptive_FIR_FABOSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_MSS::work","component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS.v","TRUE","FALSE"
SUBBLOCK "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v","FALSE","FALSE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_CCC_0_FCCC::work","component\work\Adaptive_FIR\CCC_0\Adaptive_FIR_CCC_0_FCCC.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_FABOSC_0_OSC::work","component\work\Adaptive_FIR\FABOSC_0\Adaptive_FIR_FABOSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_MSS::work","component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS.v","TRUE","FALSE"
SUBBLOCK "MSS_075::work","component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS_syn.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top::work","component\work\Adaptive_FIR_top\Adaptive_FIR_top.v","TRUE","FALSE"
SUBBLOCK "Adaptive_FIR::work","component\work\Adaptive_FIR\Adaptive_FIR.v","TRUE","FALSE"
SUBBLOCK "Adaptive_FIR_top_TPSRAM_0_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_0\Adaptive_FIR_top_TPSRAM_0_TPSRAM.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_TPSRAM_1_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_1\Adaptive_FIR_top_TPSRAM_1_TPSRAM.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_TPSRAM_2_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_2\Adaptive_FIR_top_TPSRAM_2_TPSRAM.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_TPSRAM_3_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_3\Adaptive_FIR_top_TPSRAM_3_TPSRAM.v","FALSE","FALSE"
SUBBLOCK "DATAHANDLE_FSM::work","hdl\DATAHANDLE_FSM.v","FALSE","FALSE"
SUBBLOCK "FILTERCONTROL_FSM::work","hdl\FILTERCONTROL_FSM.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP::work","component\work\LMS_FIR_TOP\LMS_FIR_TOP.v","TRUE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_COREFFT::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_TPSRAM_0_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_0\Adaptive_FIR_top_TPSRAM_0_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_TPSRAM_1_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_1\Adaptive_FIR_top_TPSRAM_1_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_TPSRAM_2_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_2\Adaptive_FIR_top_TPSRAM_2_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_TPSRAM_3_TPSRAM::work","component\work\Adaptive_FIR_top\TPSRAM_3\Adaptive_FIR_top_TPSRAM_3_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v","FALSE","FALSE"
SUBBLOCK "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v","FALSE","FALSE"
ENDLIST
LIST "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v","FALSE","FALSE"
ENDLIST
LIST "DATAHANDLE_FSM::work","hdl\DATAHANDLE_FSM.v","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "SmartFusion2_CMSIS::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_GPIO_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_MMUART_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "FILTERCONTROL_FSM::work","hdl\FILTERCONTROL_FSM.v","FALSE","FALSE"
ENDLIST
LIST "LMS_ALGO::work","hdl\LMS_ALGO.v","FALSE","FALSE"
ENDLIST
LIST "LMS_CONTROL_FSM::work","hdl\LMS_CONTROL_FSM.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP::work","component\work\LMS_FIR_TOP\LMS_FIR_TOP.v","TRUE","FALSE"
SUBBLOCK "LMS_ALGO::work","hdl\LMS_ALGO.v","FALSE","FALSE"
SUBBLOCK "LMS_CONTROL_FSM::work","hdl\LMS_CONTROL_FSM.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREFIR::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\top\COREFIR.v","FALSE","FALSE"
ENDLIST
LIST "MSS_075::work","component\work\Adaptive_FIR_MSS\Adaptive_FIR_MSS_syn.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_CMSIS::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_GPIO_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_MMUART_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
SUBBLOCK "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v","FALSE","FALSE"
SUBBLOCK "coreapb3_iaddr_reg::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v","FALSE","FALSE"
ENDLIST
LIST "coreapb3_iaddr_reg::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v","FALSE","FALSE"
ENDLIST
LIST "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v","FALSE","FALSE"
ENDLIST
LIST "BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
SUBBLOCK "BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
SUBBLOCK "BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
SUBBLOCK "BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
SUBBLOCK "BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
ENDLIST
LIST "accumulator_44bit::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_accumulator::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "accumulator_44bit::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_signExt::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "fabric_accumulator::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_accumulator_OLD::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "accumulator_44bit::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_kitCountS::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_kitEdge::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_kitSync_ngrst::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_RAM_fabric::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "decm_signExt::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "enum_coef_sr::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "enum_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "enum_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "enum_kitSync_ngrst::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "enum_signExt::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fabric_accumulator::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_kitCountC::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_kitCountS::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_kitEdge::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_kitSync_ngrst::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
SUBBLOCK "fold_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_RAM_fabric::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "fold_signExt::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\fold_kit.v","FALSE","FALSE"
ENDLIST
LIST "intrp_data_dly_section::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_add2_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_mac18x18_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac_lib.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_const_arr::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREDECMFIR::COREFIR_LIB","","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREENUMFIR::COREFIR_LIB","","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREENUMFIR_G4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_COREFIR.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_fir_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREFIR::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\top\COREFIR.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREDECMFIR::COREFIR_LIB","","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREENUMFIR::COREFIR_LIB","","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREENUMFIR_G4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_COREFIR.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREFOLDFIR::COREFIR_LIB","","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREINTRPFIR::COREFIR_LIB","","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREFOLDFIR::COREFIR_LIB","","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_COREINTRPFIR::COREFIR_LIB","","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_fir_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_odd_symmetry_tap_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_tap_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_wide_coef::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_kitSync_ngrst::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_mac18x18_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac_lib.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_mac_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_add2_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_odd_symmetry_tap_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_mac_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_signExt::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_tap_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_mac_enum_g4::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_bit_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_kitDelay_reg::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "enum_signExt::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "LMS_FIR_TOP_COREFIR_0_wide_coef::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v","FALSE","FALSE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_const_arr::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v","FALSE","FALSE"
SUBBLOCK "enum_coef_sr::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "write_reload_coef_decm::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitEdge::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitSync_ngrst::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "write_reload_coef_intrp::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitEdge::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
SUBBLOCK "decm_kitSync_ngrst::COREFIR_LIB","component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\decimation_kit.v","FALSE","FALSE"
ENDLIST
LIST "bhv_coef_gen::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_dirac::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_fEdge_ce::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_gen::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhvEdge::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_dirac::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_fEdge_ce::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_lfsr::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_step::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_lfsr::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_step::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhvClockGen::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhvDelay::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhvEdge::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "data_gen_bhv::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v","FALSE","TRUE"
ENDLIST
LIST "gen_data_valid_bhv::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v","FALSE","TRUE"
SUBBLOCK "LMS_FIR_TOP_COREFIR_0_COREFIR::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\core\top\COREFIR.v","FALSE","FALSE"
SUBBLOCK "bhvClockGen::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhvDelay::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhvEdge::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvKit.v","FALSE","TRUE"
SUBBLOCK "data_gen_bhv::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v","FALSE","TRUE"
SUBBLOCK "gen_data_valid_bhv::COREFIR_LIB","component\work\LMS_FIR_TOP\COREFIR_0\rtl\vlog\test\user\enum_SmFu4\bhvFir_tb.v","FALSE","TRUE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_COREFFT::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_COREFFT_STRM::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_COREFFT_INPLC::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_inPlace::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_outBuff::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_twidLUT::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_twiddle::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\twiddle32.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_autoScale::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_bfly2::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_bit_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_slowClock::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_sm_top::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_switch::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_COREFFT_STRM::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_inBuffer::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_wrapRam::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_inPlace::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_inBuffer::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_lsram_g5::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_outBuff::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_wrapRam::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_ram_smGen::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\Adaptive_FIR_top_COREFFT_0_ram_smGen.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_twiddle::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\twiddle32.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_twidLUT::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_wrapRam::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_uram_g5::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_uram_smGen::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "Adaptive_FIR_top_COREFFT_0_wrapRam::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_lsram_g5::COREFFT_LIB","","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_ram_smGen::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\Adaptive_FIR_top_COREFFT_0_ram_smGen.v","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_uram_g5::COREFFT_LIB","","FALSE","FALSE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_uram_smGen::COREFFT_LIB","","FALSE","FALSE"
SUBBLOCK "fft_inpl_RAM_two_port::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_autoScale::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitEdge::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_bcounter::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_bfly2::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_cmplx_rnd::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_cmplx_18::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_half_cmplx_18::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_cmplx_35::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_half_cmplx_35::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_cmplx_rnd::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_cmplx_18::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_cmplx_35::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitRndUp::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_counter::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_counter_w::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_half_cmplx_18::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_mac18x18mx::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\mac_lib.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_signExt::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_half_cmplx_35::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\cmplx.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_mac18x18mx::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\mac_lib.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_signExt::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_inBuf_fftA_pipe::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_inBuf_ldA::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_counter::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_kitCountS::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_kitDelay_bit_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_kitEdge::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_kitRndUp::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_kitSync_ngrst::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_bit_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_mac18x18mx::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\mac_lib.v","FALSE","FALSE"
SUBBLOCK "MACC_PA::COREFFT_LIB","","FALSE","FALSE"
SUBBLOCK "MATH18X18::COREFFT_LIB","","FALSE","FALSE"
SUBBLOCK "fft_inpl_signExt::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_outBufA::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_counter::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_bit_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_RAM_two_port::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_rdFFTtimer::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_counter::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_counter_w::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_bit_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_signExt::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_slowClock::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_sm_top::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_inBuf_fftA_pipe::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_inBuf_ldA::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitCountS::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_bit_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitDelay_reg::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitEdge::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_outBufA::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_rdFFTtimer::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_twid_rA::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_twid_wA_gen::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_switch::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_twid_rA::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
ENDLIST
LIST "fft_inpl_twid_wA_gen::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\fftSm.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_bcounter::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
SUBBLOCK "fft_inpl_kitSync_ngrst::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\core\kit.v","FALSE","FALSE"
ENDLIST
LIST "MACC_PA::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "MATH18X18::COREFFT_LIB","","FALSE","FALSE"
ENDLIST
LIST "bhv_dirac::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_fEdge_ce::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_gen::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhvEdge::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_dirac::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_fEdge_ce::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_lfsr::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhv_step::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_lfsr::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhv_step::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhvClockGen::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhvDelay::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "bhvEdge::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\test\user\in_place_FFT_tb.v","FALSE","TRUE"
SUBBLOCK "Adaptive_FIR_top_COREFFT_0_COREFFT::COREFFT_LIB","component\work\Adaptive_FIR_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v","FALSE","FALSE"
SUBBLOCK "bhvClockGen::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
SUBBLOCK "bhvEdge::COREFFT_LIB","component\Actel\DirectCore\COREFFT\7.0.104\rtl\in_place\vlog\test\user\bhvKit.v","FALSE","TRUE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST
LIST IOTabList
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
VALUE "constraint\Adaptive_FIR_top_derived_constraints.sdc"
ENDLIST
LIST FDCTabList
ENDLIST
