<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.8.1.12</text>
<text>Microsemi Corporation - Microsemi Libero Software Release Libero SoC v11.8 SP1 (Version 11.8.1.12)</text>
<text>Date: Mon Sep 11 18:58:44 2017
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>Adaptive_FIR_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>timing_analysis</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>5.762</cell>
 <cell>173.551</cell>
 <cell>10.000</cell>
 <cell>100.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>11.768</cell>
 <cell>8.336</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>4.117</cell>
 <cell>242.895</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/CCC_0/GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine_1_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/inBufValid_r:D</cell>
 <cell>0.437</cell>
 <cell>0.421</cell>
 <cell>6.232</cell>
 <cell>5.811</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_3_[1]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine_4_[1]:D</cell>
 <cell>0.450</cell>
 <cell>0.425</cell>
 <cell>6.236</cell>
 <cell>5.811</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine_1_[0]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[0]:D</cell>
 <cell>0.456</cell>
 <cell>0.427</cell>
 <cell>6.242</cell>
 <cell>5.815</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine_0_[0]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine_1_[0]:D</cell>
 <cell>0.456</cell>
 <cell>0.427</cell>
 <cell>6.238</cell>
 <cell>5.811</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[24]:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[24]:D</cell>
 <cell>0.456</cell>
 <cell>0.428</cell>
 <cell>6.242</cell>
 <cell>5.814</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine_1_:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/inBufValid_r:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.232</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.811</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.421</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.742</cell>
 <cell>3.742</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.442</cell>
 <cell>4.184</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>4.357</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.608</cell>
 <cell>4.965</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>5.272</cell>
 <cell>111</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine_1_:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.523</cell>
 <cell>5.795</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine_1_:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.089</cell>
 <cell>5.884</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/inBufValid_r:D</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/inBufValid_w</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>6.232</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.232</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.742</cell>
 <cell>3.742</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.442</cell>
 <cell>4.184</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>4.357</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.608</cell>
 <cell>4.965</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>5.272</cell>
 <cell>111</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/inBufValid_r:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.539</cell>
 <cell>5.811</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/inBufValid_r:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.811</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.811</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>MMUART_1_TXD</cell>
 <cell>5.684</cell>
 <cell></cell>
 <cell>11.768</cell>
 <cell></cell>
 <cell>11.768</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.768</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.742</cell>
 <cell>3.742</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.442</cell>
 <cell>4.184</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>4.357</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.612</cell>
 <cell>4.969</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>5.276</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.395</cell>
 <cell>5.671</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.203</cell>
 <cell>5.874</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.210</cell>
 <cell>6.084</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_075_IP</cell>
 <cell>+</cell>
 <cell>1.947</cell>
 <cell>8.031</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.274</cell>
 <cell>9.305</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/Adaptive_FIR_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>2.463</cell>
 <cell>11.768</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>11.768</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>11.768</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.742</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_1_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>0.598</cell>
 <cell>0.583</cell>
 <cell>6.334</cell>
 <cell>5.751</cell>
 <cell>0.000</cell>
 <cell>-0.015</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:ALn</cell>
 <cell>0.598</cell>
 <cell>0.583</cell>
 <cell>6.334</cell>
 <cell>5.751</cell>
 <cell>0.000</cell>
 <cell>-0.015</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_select:ALn</cell>
 <cell>0.598</cell>
 <cell>0.592</cell>
 <cell>6.334</cell>
 <cell>5.742</cell>
 <cell>0.000</cell>
 <cell>-0.006</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[7].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>1.100</cell>
 <cell>1.015</cell>
 <cell>6.836</cell>
 <cell>5.821</cell>
 <cell>-0.048</cell>
 <cell>-0.133</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</cell>
 <cell>LMS_FIR_TOP_0/COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[4].a_tap/mac_enum_0/adder2.adder2_0/mac_0/mac_0/U0/INST_MACC_IP:CDSEL_AL_N</cell>
 <cell>1.374</cell>
 <cell>1.288</cell>
 <cell>7.110</cell>
 <cell>5.822</cell>
 <cell>-0.048</cell>
 <cell>-0.134</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.334</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.751</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.583</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.742</cell>
 <cell>3.742</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.442</cell>
 <cell>4.184</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>4.357</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.582</cell>
 <cell>4.939</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>5.246</cell>
 <cell>55</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.490</cell>
 <cell>5.736</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>5.820</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CORERESETP_0/POWER_ON_RESET_N_clk_base</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.514</cell>
 <cell>6.334</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.334</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.742</cell>
 <cell>3.742</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.442</cell>
 <cell>4.184</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.173</cell>
 <cell>4.357</cell>
 <cell>35</cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.582</cell>
 <cell>4.939</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>5.246</cell>
 <cell>55</cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:CLK</cell>
 <cell>net</cell>
 <cell>Adaptive_FIR_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.505</cell>
 <cell>5.751</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>Adaptive_FIR_0/CORERESETP_0/mss_ready_state:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.751</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.751</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to Adaptive_FIR_0/CCC_0/GL0</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain Adaptive_FIR_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</cell>
 <cell>0.468</cell>
 <cell></cell>
 <cell>4.964</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/tick1:D</cell>
 <cell>0.511</cell>
 <cell></cell>
 <cell>4.996</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_0_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:D</cell>
 <cell>0.576</cell>
 <cell></cell>
 <cell>5.061</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:D</cell>
 <cell>0.583</cell>
 <cell></cell>
 <cell>5.068</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_3_:CLK</cell>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/pulse:D</cell>
 <cell>0.584</cell>
 <cell></cell>
 <cell>5.069</cell>
 <cell></cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.964</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.312</cell>
 <cell>0.312</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.214</cell>
 <cell>0.526</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.221</cell>
 <cell>2.747</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>3.110</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.576</cell>
 <cell>3.686</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>3.993</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.503</cell>
 <cell>4.496</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_1_:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.084</cell>
 <cell>4.580</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/delayLine_1_</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.384</cell>
 <cell>4.964</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.964</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.312</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG1</cell>
 <cell>+</cell>
 <cell>0.214</cell>
 <cell>N/C</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.221</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.363</cell>
 <cell>N/C</cell>
 <cell>4</cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.576</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.307</cell>
 <cell>N/C</cell>
 <cell>7</cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:CLK</cell>
 <cell>net</cell>
 <cell>COREFFT_0/genblk1_DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.507</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine_2_:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET Adaptive_FIR_0/CCC_0/GL0 to COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
