#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: W764-ONTEDDHUS1 # Tue Mar 14 12:30:28 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\FCCC_0\Modbus_TCP_top_FCCC_0_FCCC.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\FCCC_1\Modbus_TCP_top_FCCC_1_FCCC.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF_syn.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\CCC_0\Modbus_TCP_top_sb_CCC_0_FCCC.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb_MSS\Modbus_TCP_top_sb_MSS_syn.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb_MSS\Modbus_TCP_top_sb_MSS.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\Modbus_TCP_top_sb.v" (library work) @I::"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\Modbus_TCP_top.v" (library work) Verilog syntax check successful! File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\FCCC_0\Modbus_TCP_top_FCCC_0_FCCC.v changed - recompiling File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\FCCC_1\Modbus_TCP_top_FCCC_1_FCCC.v changed - recompiling File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF_syn.v changed - recompiling File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF.v changed - recompiling File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\Modbus_TCP_top.v changed - recompiling Selecting top level module Modbus_TCP_top @N:CG364 : smartfusion2.v(126) | Synthesizing module AND2 in library work. @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF in library work. @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work. @N:CG364 : Modbus_TCP_top_FCCC_0_FCCC.v(5) | Synthesizing module Modbus_TCP_top_FCCC_0_FCCC in library work. @N:CG364 : Modbus_TCP_top_FCCC_1_FCCC.v(5) | Synthesizing module Modbus_TCP_top_FCCC_1_FCCC in library work. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. @N:CG364 : Modbus_TCP_top_sb_CCC_0_FCCC.v(5) | Synthesizing module Modbus_TCP_top_sb_CCC_0_FCCC in library work. @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP in library work. FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000001 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z1 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000001 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000001 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z2 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset in library work. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(5) | Synthesizing module Modbus_TCP_top_sb_FABOSC_0_OSC in library work. @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF in library work. @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF in library work. @N:CG364 : smartfusion2.v(338) | Synthesizing module BIBUF_DIFF in library work. @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. @N:CG364 : Modbus_TCP_top_sb_MSS_syn.v(5) | Synthesizing module MSS_120 in library work. @N:CG364 : Modbus_TCP_top_sb_MSS.v(9) | Synthesizing module Modbus_TCP_top_sb_MSS in library work. @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : Modbus_TCP_top_sb.v(9) | Synthesizing module Modbus_TCP_top_sb in library work. @N:CG364 : smartfusion2.v(320) | Synthesizing module INBUF_DIFF in library work. @N:CG364 : Modbus_TCP_top_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_120_3 in library work. @N:CG364 : Modbus_TCP_top_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module Modbus_TCP_top_SERDES_IF_0_SERDES_IF in library work. @N:CG364 : Modbus_TCP_top.v(9) | Synthesizing module Modbus_TCP_top in library work. @W:CL156 : Modbus_TCP_top_SERDES_IF_0_SERDES_IF.v(198) | *Input un1_gnd_net[63:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL157 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : Modbus_TCP_top_sb_FABOSC_0_OSC.v(14) | Input XTL is unused. @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 12:30:29 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 12:30:29 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 12:30:29 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\synwork\Modbus_TCP_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Mar 14 12:30:30 2017 ###########################################################] Pre-mapping Report # Tue Mar 14 12:30:30 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\designer\Modbus_TCP_top\synthesis.fdc Linked File: Modbus_TCP_top_scck.rpt @W:MF499 : | Found issues with constraints. Please check report file D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\Modbus_TCP_top_scck.rpt. @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 112MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF1_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE (in view: work.CoreConfigP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. syn_allowed_resources : blockrams=236 set on top level netlist Modbus_TCP_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ CLK0_PAD 50.0 MHz 20.000 declared default_clkgroup 0 FCCC_0/GL0 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 FCCC_0/GL1 62.5 MHz 16.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup 1 FCCC_1/GL0 125.0 MHz 8.000 generated (from SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup 1 Modbus_TCP_top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 1 Modbus_TCP_top_sb_0/CCC_0/GL0 100.0 MHz 10.000 generated (from CLK0_PAD) default_clkgroup 53 Modbus_TCP_top_sb_0/CCC_0/GL3 125.0 MHz 8.000 generated (from CLK0_PAD) default_clkgroup 37 Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 46 Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB 20.0 MHz 50.000 declared default_clkgroup 113 SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz 8.000 declared default_clkgroup 0 ========================================================================================================================================================================================== @W:MT530 : modbus_tcp_top_serdes_if_0_serdes_if.v(103) | Found inferred clock Modbus_TCP_top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock which controls 1 sequential elements including SERDES_IF_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\Modbus_TCP_top.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1365) | There are no possible illegal states for state machine sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required. @W:MF511 : | Found issues with constraints. Please check constraint checker report "D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\Modbus_TCP_top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 54MB peak: 141MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Mar 14 12:30:31 2017 ###########################################################] Map & Optimize Report # Tue Mar 14 12:30:32 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) @W:BN309 : | One or more non-fatal issues found in constraints; Please run Constraint Check for analysis Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB) @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : modbus_tcp_top_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) on net RCOSC_25_50MHZ_CCC (in view: work.Modbus_TCP_top_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif2_spll_lock_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(963) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_spll_lock_q2 because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif2_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(755) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sm0_areset_n_q1 because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_areset_n_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(912) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif2_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(898) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif1_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(884) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif1_areset_n_rcosc because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(839) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_areset_n_clk_base because it is equivalent to instance Modbus_TCP_top_sb_0.CORERESETP_0.sm0_areset_n_clk_base. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 138MB) Encoding state machine state[2:0] (in view: work.CoreConfigP_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N:MO225 : coreresetp.v(1365) | There are no possible illegal states for state machine sdif3_state[3:0] (in view: work.CoreResetP_Z2(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z2(verilog) instance count_ddr[13:0] @N:MO231 : coreresetp.v(1581) | Found counter in view:work.CoreResetP_Z2(verilog) instance count_sdif3[12:0] Encoding state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreresetp_pcie_hotreset.v(179) | There are no possible illegal states for state machine state[3:0] (in view: work.coreresetp_pcie_hotreset(verilog)); safe FSM implementation is not required. @N:MO231 : coreresetp_pcie_hotreset.v(227) | Found counter in view:work.coreresetp_pcie_hotreset(verilog) instance count[6:0] Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) @N:BN362 : coreresetp.v(1089) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.DDR_READY_int (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.sdif_core_reset_n (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.sdif_core_reset_n_q1 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.hot_reset_n (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[6] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[5] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[4] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[3] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[2] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[1] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(227) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.count[0] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.SDIF3_CORE_RESET_N_0 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.psel_q2 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.reset_n_q1 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_HotReset_q (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_Disabled_q (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_DetectQuiet_q (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.pwrite_q1 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.psel_q1 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_HotReset (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_Disabled (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_DetectQuiet (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_HotReset_entry_p (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_Disabled_entry_p (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(134) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.LTSSM_DetectQuiet_entry_p (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(84) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.reset_n_clk_ltssm (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.pwrite_q2 (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.state[0] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[1] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[0] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.state[1] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[4] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[3] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[2] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[1] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q1[0] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[4] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[3] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp_pcie_hotreset.v(99) | Removing sequential instance Modbus_TCP_top_sb_0.CORERESETP_0.genblk5\.sdif3_phr.ltssm_q2[2] (in view: work.Modbus_TCP_top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:01s 6.08ns 193 / 189 @N:FP130 : | Promoting Net Modbus_TCP_top_sb_0_INIT_APB_S_PRESET_N on CLKINT I_117 @N:FP130 : | Promoting Net Modbus_TCP_top_sb_0_INIT_APB_S_PCLK on CLKINT I_118 @N:FP130 : | Promoting Net Modbus_TCP_top_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_119 @N:FP130 : | Promoting Net Modbus_TCP_top_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_120 @N:FP130 : | Promoting Net Modbus_TCP_top_sb_0.CORERESETP_0.sdif0_areset_n_rcosc on CLKINT I_121 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 142MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 151 clock pin(s) of sequential element(s) 4 gated/generated clock tree(s) driving 45 clock pin(s) of sequential element(s) 0 instances converted, 45 sequential instances remain driven by gated/generated clocks ============================================================================== Non-Gated/Non-Generated Clocks =============================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0005 SERDES_IF_0.refclk1_inbuf_diff INBUF_DIFF 1 SERDES_IF_0.SERDESIF_INST ClockId0006 Modbus_TCP_top_sb_0.Modbus_TCP_top_sb_MSS_0.MSS_ADLIB_INST clock definition on MSS_120 112 Modbus_TCP_top_sb_0.Modbus_TCP_top_sb_MSS_0.MSS_ADLIB_INST ClockId0007 Modbus_TCP_top_sb_0.FABOSC_0.I_RCOSC_25_50MHZ clock definition on RCOSC_25_50MHZ 38 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[12] ============================================================================================================================================================================================= ============================================================================================== Gated/Generated Clocks =============================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Modbus_TCP_top_sb_0.CCC_0.CCC_INST CCC 42 Modbus_TCP_top_sb_0.Modbus_TCP_top_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0002 FCCC_0.CCC_INST CCC 1 Modbus_TCP_top_sb_0.Modbus_TCP_top_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0003 FCCC_0.CCC_INST CCC 1 Modbus_TCP_top_sb_0.Modbus_TCP_top_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ClockId0004 FCCC_1.CCC_INST CCC 1 Modbus_TCP_top_sb_0.Modbus_TCP_top_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_120 ===================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 110MB peak: 142MB) Writing Analyst data base D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\synwork\Modbus_TCP_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 142MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\synthesis\Modbus_TCP_top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 142MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 142MB) @W:MT246 : modbus_tcp_top_sb_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock CLK0_PAD with period 20.00ns @W:MT420 : | Found inferred clock Modbus_TCP_top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_IF_0.REFCLK1_OUT" @N:MT615 : | Found clock SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] with period 8.00ns @N:MT615 : | Found clock SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] with period 8.00ns @N:MT615 : | Found clock Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB with period 50.00ns @N:MT615 : | Found clock Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock Modbus_TCP_top_sb_0/CCC_0/GL0 with period 10.00ns @N:MT615 : | Found clock Modbus_TCP_top_sb_0/CCC_0/GL3 with period 8.00ns @N:MT615 : | Found clock FCCC_1/GL0 with period 8.00ns @N:MT615 : | Found clock FCCC_0/GL0 with period 16.00ns @N:MT615 : | Found clock FCCC_0/GL1 with period 16.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Mar 14 12:30:34 2017 # Top view: Modbus_TCP_top Requested Frequency: 20.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\designer\Modbus_TCP_top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 7.334 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CLK0_PAD 50.0 MHz NA 20.000 NA NA declared default_clkgroup FCCC_0/GL0 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_0/GL1 62.5 MHz NA 16.000 NA NA generated (from SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1]) default_clkgroup FCCC_1/GL0 125.0 MHz NA 8.000 NA NA generated (from SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1]) default_clkgroup Modbus_TCP_top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 Modbus_TCP_top_sb_0/CCC_0/GL0 100.0 MHz 375.1 MHz 10.000 2.666 7.334 generated (from CLK0_PAD) default_clkgroup Modbus_TCP_top_sb_0/CCC_0/GL3 125.0 MHz NA 8.000 NA NA generated (from CLK0_PAD) default_clkgroup Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 428.6 MHz 20.000 2.333 17.667 declared default_clkgroup Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB 20.0 MHz 103.4 MHz 50.000 9.675 21.002 declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] 125.0 MHz NA 8.000 NA NA declared default_clkgroup System 100.0 MHz NA 10.000 NA NA system system_clkgroup ======================================================================================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 17.667 | No paths - | No paths - | No paths - Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Modbus_TCP_top_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB | 50.000 40.325 | No paths - | 25.000 22.713 | 25.000 21.002 Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB Modbus_TCP_top_sb_0/CCC_0/GL0 | 10.000 False | No paths - | No paths - | No paths - Modbus_TCP_top_sb_0/CCC_0/GL0 Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 10.000 False | No paths - | No paths - | No paths - Modbus_TCP_top_sb_0/CCC_0/GL0 Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB | 10.000 False | No paths - | No paths - | No paths - Modbus_TCP_top_sb_0/CCC_0/GL0 Modbus_TCP_top_sb_0/CCC_0/GL0 | 10.000 7.334 | No paths - | No paths - | No paths - ================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Modbus_TCP_top_sb_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORERESETP_0.ddr_settled_clk_base Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q ddr_settled_clk_base 0.076 7.334 Modbus_TCP_top_sb_0.CORERESETP_0.release_sdif3_core_clk_base Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q release_sdif3_core_clk_base 0.076 7.374 Modbus_TCP_top_sb_0.CORERESETP_0.release_sdif1_core_clk_base Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q release_sdif1_core_clk_base 0.076 7.906 Modbus_TCP_top_sb_0.CORERESETP_0.sdif2_spll_lock_q2 Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q next_sm0_state18 0.094 7.922 Modbus_TCP_top_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q CONFIG1_DONE_clk_base 0.094 7.964 Modbus_TCP_top_sb_0.CORERESETP_0.release_sdif2_core_clk_base Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q release_sdif2_core_clk_base 0.076 7.993 Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state[3] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q sm0_state[3] 0.094 8.079 Modbus_TCP_top_sb_0.CORERESETP_0.release_sdif0_core_clk_base Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q release_sdif0_core_clk_base 0.076 8.102 Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_state[0] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q sdif3_state[0] 0.094 8.482 Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_state[1] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE Q sdif3_state[1] 0.094 8.616 ===================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state[5] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE D sm0_state_ns[5] 9.778 7.334 Modbus_TCP_top_sb_0.CORERESETP_0.SDIF_RELEASED_int Modbus_TCP_top_sb_0/CCC_0/GL0 SLE EN next_sdif_released_0_sqmuxa 9.707 7.433 Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state[4] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE D sm0_state_ns[4] 9.778 7.449 Modbus_TCP_top_sb_0.CORERESETP_0.SDIF3_PHY_RESET_N_int Modbus_TCP_top_sb_0/CCC_0/GL0 SLE EN next_sdif3_phy_reset_n_0_sqmuxa 9.707 7.922 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3_enable Modbus_TCP_top_sb_0/CCC_0/GL0 SLE EN un1_next_sdif3_core_reset_n_0_sqmuxa_i_i 9.707 7.993 Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_state[0] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE D N_5_mux_i 9.778 8.018 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_enable Modbus_TCP_top_sb_0/CCC_0/GL0 SLE EN un1_next_ddr_ready_0_sqmuxa_0 9.707 8.079 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_enable Modbus_TCP_top_sb_0/CCC_0/GL0 SLE D next_count_ddr_enable_0_sqmuxa 9.778 8.382 Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state[3] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE D sm0_state_ns[3] 9.778 8.691 Modbus_TCP_top_sb_0.CORERESETP_0.sdif3_state[1] Modbus_TCP_top_sb_0/CCC_0/GL0 SLE D N_4_i 9.778 8.745 ============================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.444 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 7.334 Number of logic level(s): 3 Starting point: Modbus_TCP_top_sb_0.CORERESETP_0.ddr_settled_clk_base / Q Ending point: Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state[5] / D The start point is clocked by Modbus_TCP_top_sb_0/CCC_0/GL0 [rising] on pin CLK The end point is clocked by Modbus_TCP_top_sb_0/CCC_0/GL0 [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORERESETP_0.ddr_settled_clk_base SLE Q Out 0.076 0.076 - ddr_settled_clk_base Net - - 0.587 - 2 Modbus_TCP_top_sb_0.CORERESETP_0.next_sdif3_core_reset_n_0_sqmuxa_i_i_o3 CFG2 A In - 0.663 - Modbus_TCP_top_sb_0.CORERESETP_0.next_sdif3_core_reset_n_0_sqmuxa_i_i_o3 CFG2 Y Out 0.087 0.750 - N_23 Net - - 0.548 - 2 Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state_ns_0_o2[4] CFG4 B In - 1.298 - Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state_ns_0_o2[4] CFG4 Y Out 0.143 1.441 - N_25 Net - - 0.590 - 3 Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state_ns_0[5] CFG4 D In - 2.031 - Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state_ns_0[5] CFG4 Y Out 0.276 2.306 - sm0_state_ns[5] Net - - 0.138 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.sm0_state[5] SLE D In - 2.444 - ======================================================================================================================================= Total path delay (propagation time + setup) of 2.666 is 0.804(30.2%) logic and 1.862(69.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[0] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[0] 0.094 17.667 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[0] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[0] 0.094 17.681 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[1] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[1] 0.094 17.732 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[2] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[2] 0.094 17.746 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[1] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[1] 0.094 17.746 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[3] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[3] 0.094 17.760 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[2] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[2] 0.094 17.760 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[4] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[4] 0.094 17.774 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[3] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_sdif3[3] 0.094 17.774 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[5] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE Q count_ddr[5] 0.094 17.789 =================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[13] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[13] 19.778 17.667 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[12] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[12] 19.778 17.681 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[12] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[12] 19.778 17.681 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[11] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[11] 19.778 17.695 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[11] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[11] 19.778 17.695 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[10] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[10] 19.778 17.709 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[10] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[10] 19.778 17.709 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[9] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[9] 19.778 17.724 Modbus_TCP_top_sb_0.CORERESETP_0.count_sdif3[9] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_sdif3_s[9] 19.778 17.724 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[8] Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT SLE D count_ddr_s[8] 19.778 17.738 ======================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.778 - Propagation time: 2.111 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.667 Number of logic level(s): 14 Starting point: Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[0] / Q Ending point: Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[13] / D The start point is clocked by Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK The end point is clocked by Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.094 0.094 - count_ddr[0] Net - - 0.637 - 3 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_s_116 ARI1 B In - 0.732 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_s_116 ARI1 FCO Out 0.174 0.906 - count_ddr_s_116_FCO Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCI In - 0.906 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCO Out 0.014 0.920 - count_ddr_cry[1] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCI In - 0.920 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCO Out 0.014 0.935 - count_ddr_cry[2] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCI In - 0.935 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCO Out 0.014 0.949 - count_ddr_cry[3] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCI In - 0.949 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCO Out 0.014 0.963 - count_ddr_cry[4] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCI In - 0.963 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCO Out 0.014 0.977 - count_ddr_cry[5] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCI In - 0.977 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCO Out 0.014 0.991 - count_ddr_cry[6] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCI In - 0.991 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCO Out 0.014 1.006 - count_ddr_cry[7] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCI In - 1.006 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCO Out 0.014 1.020 - count_ddr_cry[8] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCI In - 1.020 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCO Out 0.014 1.034 - count_ddr_cry[9] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCI In - 1.034 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCO Out 0.014 1.048 - count_ddr_cry[10] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCI In - 1.048 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCO Out 0.014 1.062 - count_ddr_cry[11] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCI In - 1.062 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCO Out 0.014 1.077 - count_ddr_cry[12] Net - - 0.000 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_s[13] ARI1 FCI In - 1.077 - Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr_s[13] ARI1 S Out 0.063 1.140 - count_ddr_s[13] Net - - 0.971 - 1 Modbus_TCP_top_sb_0.CORERESETP_0.count_ddr[13] SLE D In - 2.111 - ================================================================================================================= Total path delay (propagation time + setup) of 2.333 is 0.725(31.1%) logic and 1.609(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORECONFIGP_0.psel Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q psel 0.094 21.002 Modbus_TCP_top_sb_0.CORECONFIGP_0.paddr[12] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PADDR[12] 0.094 22.713 Modbus_TCP_top_sb_0.CORECONFIGP_0.paddr[13] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PADDR[13] 0.094 22.750 Modbus_TCP_top_sb_0.CORECONFIGP_0.state[1] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q state[1] 0.076 22.897 Modbus_TCP_top_sb_0.CORECONFIGP_0.SDIF3_PENABLE Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PENABLE 0.094 23.455 Modbus_TCP_top_sb_0.CORECONFIGP_0.paddr[16] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q paddr[16] 0.076 23.628 Modbus_TCP_top_sb_0.CORECONFIGP_0.MDDR_PENABLE Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q CORECONFIGP_0_MDDR_APBmslave_PENABLE 0.094 23.651 Modbus_TCP_top_sb_0.CORECONFIGP_0.paddr[15] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PADDR[15] 0.094 23.658 Modbus_TCP_top_sb_0.CORECONFIGP_0.state[0] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q state[0] 0.076 23.784 Modbus_TCP_top_sb_0.CORECONFIGP_0.paddr[14] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE Q Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PADDR[14] 0.076 23.859 ======================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SERDESIF_120_3 APB_PSEL Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PSELx 23.020 21.002 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[3] 24.778 21.208 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[5] 24.778 21.208 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[0] 24.778 21.453 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[1] 24.778 21.453 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE EN un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0 24.706 21.672 Modbus_TCP_top_sb_0.CORECONFIGP_0.state[1] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D state_ns[1] 24.778 21.757 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[2] 24.778 21.818 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[4] 24.778 21.818 Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB SLE D prdata[6] 24.778 21.818 =========================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 25.000 - Setup time: 1.980 + Clock delay at ending point: 0.000 (ideal) = Required time: 23.020 - Propagation time: 2.018 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 21.002 Number of logic level(s): 1 Starting point: Modbus_TCP_top_sb_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB [falling] on pin CLK The end point is clocked by Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- Modbus_TCP_top_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.676 - 4 Modbus_TCP_top_sb_0.CORECONFIGP_0.R_SDIF3_PSEL_1_0_a2 CFG4 D In - 0.770 - Modbus_TCP_top_sb_0.CORECONFIGP_0.R_SDIF3_PSEL_1_0_a2 CFG4 Y Out 0.250 1.021 - Modbus_TCP_top_sb_0_SDIF3_INIT_APB_PSELx Net - - 0.998 - 35 SERDES_IF_0.SERDESIF_INST SERDESIF_120_3 APB_PSEL In - 2.018 - ================================================================================================================================== Total path delay (propagation time + setup) of 3.998 is 2.324(58.1%) logic and 1.674(41.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(20) | Timing constraint (from [get_cells { Modbus_TCP_top_sb_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { Modbus_TCP_top_sb_0.CORERESETP_0.sm0_areset_n_rcosc Modbus_TCP_top_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(21) | Timing constraint (from [get_cells { Modbus_TCP_top_sb_0.CORERESETP_0.MSS_HPMS_READY_int Modbus_TCP_top_sb_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { Modbus_TCP_top_sb_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(22) | Timing constraint (through [get_nets { Modbus_TCP_top_sb_0.CORERESETP_0.*sdif*_phr.hot_reset_n Modbus_TCP_top_sb_0.CORERESETP_0.*sdif*_phr.sdif_core_reset_n_0 }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(23) | Timing constraint (to [get_cells { Modbus_TCP_top_sb_0.CORERESETP_0.*sdif*_phr.ltssm_q1[*] Modbus_TCP_top_sb_0.CORERESETP_0.*sdif*_phr.psel_q1 Modbus_TCP_top_sb_0.CORERESETP_0.*sdif*_phr.pwrite_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT443 : synthesis.fdc(25) | Timing constraint (through [get_nets { Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PSEL Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { Modbus_TCP_top_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* Modbus_TCP_top_sb_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 142MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 139MB peak: 142MB) --------------------------------------- Resource Usage Report for Modbus_TCP_top Mapping to part: m2s150tfc1152-1 Cell usage: AND2 1 use CCC 3 uses CLKINT 10 uses MSS_120 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_120_3 1 use SYSRESET 1 use CFG1 6 uses CFG2 32 uses CFG3 16 uses CFG4 61 uses Carry cells: ARI1 27 uses - used for arithmetic functions Sequential Cells: SLE 189 uses DSP Blocks: 0 of 240 (0%) I/O ports: 122 I/O primitives: 98 BIBUF 42 uses BIBUF_DIFF 5 uses INBUF 13 uses INBUF_DIFF 1 use OUTBUF 35 uses OUTBUF_DIFF 1 use TRIBUFF 1 use Global Clock Buffers: 10 of 8 (125%) Total LUTs: 142 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 189 + 0 + 0 + 0 = 189; Total number of LUTs after P&R: 142 + 0 + 0 + 0 = 142; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 142MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Mar 14 12:30:34 2017 ###########################################################]