@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":126:7:126:10|Synthesizing module AND2 in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":727:7:727:9|Synthesizing module CCC in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\FCCC_0\Modbus_TCP_top_FCCC_0_FCCC.v":5:7:5:32|Synthesizing module Modbus_TCP_top_FCCC_0_FCCC in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\FCCC_1\Modbus_TCP_top_FCCC_1_FCCC.v":5:7:5:32|Synthesizing module Modbus_TCP_top_FCCC_1_FCCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\CCC_0\Modbus_TCP_top_sb_CCC_0_FCCC.v":5:7:5:34|Synthesizing module Modbus_TCP_top_sb_CCC_0_FCCC in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":31:7:31:30|Synthesizing module coreresetp_pcie_hotreset in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":5:7:5:36|Synthesizing module Modbus_TCP_top_sb_FABOSC_0_OSC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":274:7:274:12|Synthesizing module OUTBUF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":338:7:338:16|Synthesizing module BIBUF_DIFF in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb_MSS\Modbus_TCP_top_sb_MSS_syn.v":5:7:5:13|Synthesizing module MSS_120 in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb_MSS\Modbus_TCP_top_sb_MSS.v":9:7:9:27|Synthesizing module Modbus_TCP_top_sb_MSS in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":718:7:718:14|Synthesizing module SYSRESET in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\Modbus_TCP_top_sb.v":9:7:9:23|Synthesizing module Modbus_TCP_top_sb in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v":320:7:320:16|Synthesizing module INBUF_DIFF in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF_syn.v":5:7:5:20|Synthesizing module SERDESIF_120_3 in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF.v":5:7:5:42|Synthesizing module Modbus_TCP_top_SERDES_IF_0_SERDES_IF in library work.
@N: CG364 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\Modbus_TCP_top.v":9:7:9:20|Synthesizing module Modbus_TCP_top in library work.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":179:4:179:9|Trying to extract state machine for register state.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused.
@N: CL159 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused.
@N: CL201 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreConfigP\7.1.100\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state.
@N|Running in 64-bit mode

