Project Settings
Project Name | Modbus_TCP_top_syn | Implementation Name | synthesis
Top Module | Modbus_TCP_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 52 | 33 | 0 | - | 00m:01s | - | 14-03-2017 PM 12:30:29
(premap) | Complete | 30 | 20 | 0 | 0m:01s | 0m:01s | 141MB | 14-03-2017 PM 12:30:31
(fpga_mapper) | Complete | 72 | 18 | 0 | 0m:02s | 0m:02s | 142MB | 14-03-2017 PM 12:30:34
Multi-srs Generator | Complete |  |  |  |  |  |  | 14-03-2017 PM 12:30:30
Area Summary
Carry Cells | 27 | Sequential Cells | 189
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 98
Global Clock Buffers | 10 | LUTs (total_luts) | 142
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
CLK0_PAD | 50.0 MHz | NA | NA
FCCC_0/GL0 | 62.5 MHz | NA | NA
FCCC_0/GL1 | 62.5 MHz | NA | NA
FCCC_1/GL0 | 125.0 MHz | NA | NA
Modbus_TCP_top_SERDES_IF_0_SERDES_IF|REFCLK1_OUT_inferred_clock | 100.0 MHz | NA | NA
Modbus_TCP_top_sb_0/CCC_0/GL0 | 100.0 MHz | 375.1 MHz | 7.334
Modbus_TCP_top_sb_0/CCC_0/GL3 | 125.0 MHz | NA | NA
Modbus_TCP_top_sb_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | 428.6 MHz | 17.667
Modbus_TCP_top_sb_0/Modbus_TCP_top_sb_MSS_0/CLK_CONFIG_APB | 20.0 MHz | 103.4 MHz | 21.002
SERDES_IF_0/SERDESIF_INST/EPCS_RXCLK[1] | 125.0 MHz | NA | NA
SERDES_IF_0/SERDESIF_INST/EPCS_TXCLK[1] | 125.0 MHz | NA | NA
System | 100.0 MHz | NA | NA
Optimizations Summary
Combined Clock Conversion | 3 / 4 |  |