@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL156 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top\SERDES_IF_0\Modbus_TCP_top_SERDES_IF_0_SERDES_IF.v":198:35:206:69|*Input un1_gnd_net[63:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL157 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":15:7:15:24|*Output RCOSC_25_50MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\work\Modbus_TCP_top_sb\FABOSC_0\Modbus_TCP_top_sb_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL247 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bit 31 of prdata[31:0] is unused
@W: CL246 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v":36:24:36:29|Input port bits 25 to 0 of prdata[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\Libero11.8\m2s_dg0440_liberov11p7sp2_df\SF2_Modbus_TCP_Ref_Design_DF\Libero\SF2_MODBUS_TCP\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.

