#Build: Synplify Pro (R) R-2020.09M-SP1-1, Build 100R, Feb 17 2021 #install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I52881 # Sun May 30 18:57:24 2021 #Implementation: synthesis Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys HDL Compiler, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Verilog Compiler, Version comp202009synp2, Build 147R, Built Mar 17 2021 10:14:42, @ @N: : | Running in 64-bit mode @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\FILTER_CONTROL_FSM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\CCC_0\FIR_FILTER_CCC_0_FCCC.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\FABOSC_0\FIR_FILTER_FABOSC_0_OSC.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER_MSS\FIR_FILTER_MSS_syn.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER_MSS\FIR_FILTER_MSS.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\FIR_FILTER.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\Coef_Buffer\top_Coef_Buffer_TPSRAM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\FFT_IM_Buffer\top_FFT_IM_Buffer_TPSRAM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\FFT_RE_Buffer\top_FFT_RE_Buffer_TPSRAM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\FIR_IN_Buffer\top_FIR_IN_Buffer_TPSRAM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\FIR_OUT_Buffer\top_FIR_OUT_Buffer_TPSRAM.v" (library work) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\mac_lib.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\top_COREFFT_0_ram_smGen.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\twiddle32.v" (library COREFFT_LIB) @N:CG347 : twiddle32.v(35) | Read a parallel_case directive. @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v" (library COREFFT_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac_lib.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v" (library COREFIR_LIB) @I:"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v":"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\top_COREFIR_0_coef.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_COREFIR.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\top\COREFIR.v" (library COREFIR_LIB) @I::"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. Running optimization stage 1 on RAM1K18 ....... Finished optimization stage 1 on RAM1K18 (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N:CG364 : top_Coef_Buffer_TPSRAM.v(5) | Synthesizing module top_Coef_Buffer_TPSRAM in library work. Running optimization stage 1 on top_Coef_Buffer_TPSRAM ....... Finished optimization stage 1 on top_Coef_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 95MB) @N:CG775 : COREFFT_TOP.v(28) | Component top_COREFFT_0_COREFFT not found in library "work" or "__hyper__lib__", but found in library COREFFT_LIB @N:CG364 : COREFFT_TOP.v(28) | Synthesizing module top_COREFFT_0_COREFFT in library COREFFT_LIB. FPGA_FAMILY=32'b00000000000000000000000000010011 URAM_MAXDEPTH=32'b00000000000000000000000000000000 CFG_ARCH=32'b00000000000000000000000000000001 DATA_BITS=32'b00000000000000000000000000010010 TWID_BITS=32'b00000000000000000000000000010010 FFT_SIZE=32'b00000000000000000000000100000000 SCALE_ON=32'b00000000000000000000000000000001 SCALE_SCH=32'b00000000000000000000000011111111 ORDER=32'b00000000000000000000000000000000 INVERSE=32'b00000000000000000000000000000000 SCALE=32'b00000000000000000000000000000000 POINTS=32'b00000000000000000000000100000000 WIDTH=32'b00000000000000000000000000010000 MEMBUF=32'b00000000000000000000000000000001 SCALE_EXP_ON=32'b00000000000000000000000000000000 NO_RAM=32'b00000000000000000000000000000000 LOG2PTS=32'b00000000000000000000000000001000 LOGLOG2PTS=32'b00000000000000000000000000000011 FLOGLOG2PTS=32'b00000000000000000000000000000100 STREAM_DATAO_BITS=32'b00000000000000000000000000010010 IN_BITS=32'b00000000000000000000000000010000 OUTP_BITS=32'b00000000000000000000000000010000 Generated name = top_COREFFT_0_COREFFT_Z1 @N:CG364 : kit.v(445) | Synthesizing module fft_inpl_slowClock in library COREFFT_LIB. Running optimization stage 1 on fft_inpl_slowClock ....... Finished optimization stage 1 on fft_inpl_slowClock (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_bit_reg_2s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_2s ....... Finished optimization stage 1 on fft_inpl_kitDelay_bit_reg_2s (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : kit.v(29) | Synthesizing module fft_inpl_kitEdge in library COREFFT_LIB. FRONT_EDGE=32'b00000000000000000000000000000000 Generated name = fft_inpl_kitEdge_0s Running optimization stage 1 on fft_inpl_kitEdge_0s ....... Finished optimization stage 1 on fft_inpl_kitEdge_0s (CPU Time 0h:00m:00s, Memory Used current: 95MB peak: 96MB) @N:CG364 : kit.v(126) | Synthesizing module fft_inpl_counter_w in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000001010 TC=32'b00000000000000000000000010001001 Generated name = fft_inpl_counter_w_10_137s Running optimization stage 1 on fft_inpl_counter_w_10_137s ....... Finished optimization stage 1 on fft_inpl_counter_w_10_137s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000000101 TC=32'b00000000000000000000000000000111 Generated name = fft_inpl_counter_5_7 Running optimization stage 1 on fft_inpl_counter_5_7 ....... Finished optimization stage 1 on fft_inpl_counter_5_7 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000011 Generated name = fft_inpl_kitDelay_bit_reg_3s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_3s ....... Finished optimization stage 1 on fft_inpl_kitDelay_bit_reg_3s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : fftSm.v(361) | Synthesizing module fft_inpl_rdFFTtimer in library COREFFT_LIB. HALFPTS=32'b00000000000000000000000010000000 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_rdFFTtimer_128s_8_3_10s_1s Running optimization stage 1 on fft_inpl_rdFFTtimer_128s_8_3_10s_1s ....... Finished optimization stage 1 on fft_inpl_rdFFTtimer_128s_8_3_10s_1s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000001010 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_10_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_10_2s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_10_2s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000101 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_5_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_5_2s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_5_2s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitDelay_bit_reg_1s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_1s ....... Finished optimization stage 1 on fft_inpl_kitDelay_bit_reg_1s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(99) | Synthesizing module fft_inpl_kitCountS in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000000111 DCVALUE=32'b00000000000000000000000001111111 BUILD_DC=32'b00000000000000000000000000000000 Generated name = fft_inpl_kitCountS_7_127s_0s Running optimization stage 1 on fft_inpl_kitCountS_7_127s_0s ....... Finished optimization stage 1 on fft_inpl_kitCountS_7_127s_0s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000111 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_7_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_7_2s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_7_2s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000001 DELAY=32'b00000000000000000000000000001010 Generated name = fft_inpl_kitDelay_reg_1s_10s Running optimization stage 1 on fft_inpl_kitDelay_reg_1s_10s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_1s_10s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000001000 TC=32'b00000000000000000000000011111111 Generated name = fft_inpl_counter_8_255s Running optimization stage 1 on fft_inpl_counter_8_255s ....... Finished optimization stage 1 on fft_inpl_counter_8_255s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : fftSm.v(481) | Synthesizing module fft_inpl_inBuf_ldA in library COREFFT_LIB. PTS=32'b00000000000000000000000100000000 LOGPTS=32'b00000000000000000000000000001000 Generated name = fft_inpl_inBuf_ldA_256s_8 @W:CG360 : fftSm.v(502) | Removing wire load_over, as there is no assignment to it. Running optimization stage 1 on fft_inpl_inBuf_ldA_256s_8 ....... Finished optimization stage 1 on fft_inpl_inBuf_ldA_256s_8 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : fftSm.v(623) | Synthesizing module fft_inpl_inBuf_fftA_pipe in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_inBuf_fftA_pipe_8_3 Running optimization stage 1 on fft_inpl_inBuf_fftA_pipe_8_3 ....... @W:CL265 : fftSm.v(675) | Removing unused bit 6 of mask1_r[6:0]. Either assign all bits or reduce the width of the signal. Finished optimization stage 1 on fft_inpl_inBuf_fftA_pipe_8_3 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : fftSm.v(695) | Synthesizing module fft_inpl_twid_rA in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_twid_rA_8_3 Running optimization stage 1 on fft_inpl_twid_rA_8_3 ....... Finished optimization stage 1 on fft_inpl_twid_rA_8_3 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000100 Generated name = fft_inpl_kitDelay_bit_reg_4s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_4s ....... Finished optimization stage 1 on fft_inpl_kitDelay_bit_reg_4s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(405) | Synthesizing module fft_inpl_kitSync_ngrst in library COREFFT_LIB. PULSE_WIDTH=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitSync_ngrst_1s @W:CG133 : kit.v(412) | Object tick2 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on fft_inpl_kitSync_ngrst_1s ....... Finished optimization stage 1 on fft_inpl_kitSync_ngrst_1s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(161) | Synthesizing module fft_inpl_bcounter in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000000111 Generated name = fft_inpl_bcounter_7 Running optimization stage 1 on fft_inpl_bcounter_7 ....... Finished optimization stage 1 on fft_inpl_bcounter_7 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : fftSm.v(739) | Synthesizing module fft_inpl_twid_wA_gen in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_twid_wA_gen_8_3 Running optimization stage 1 on fft_inpl_twid_wA_gen_8_3 ....... Finished optimization stage 1 on fft_inpl_twid_wA_gen_8_3 (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000011 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_3_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_3_2s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_3_2s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 96MB) @N:CG364 : fftSm.v(532) | Synthesizing module fft_inpl_outBufA in library COREFFT_LIB. PTS=32'b00000000000000000000000100000000 LOGPTS=32'b00000000000000000000000000001000 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_outBufA_256s_8_1s Running optimization stage 1 on fft_inpl_outBufA_256s_8_1s ....... Finished optimization stage 1 on fft_inpl_outBufA_256s_8_1s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) @N:CG364 : fftSm.v(29) | Synthesizing module fft_inpl_sm_top in library COREFFT_LIB. PTS=32'b00000000000000000000000100000000 HALFPTS=32'b00000000000000000000000010000000 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_sm_top_256s_128s_8_3_10s_1s Running optimization stage 1 on fft_inpl_sm_top_256s_128s_8_3_10s_1s ....... @W:CL168 : fftSm.v(234) | Removing instance wStage_dly_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : fftSm.v(118) | Removing instance edge_detect_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Finished optimization stage 1 on fft_inpl_sm_top_256s_128s_8_3_10s_1s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) @N:CG364 : fftDp.v(249) | Synthesizing module top_COREFFT_0_inPlace in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = top_COREFFT_0_inPlace_8_32s_1s_0s_19s @N:CG364 : fftDp.v(163) | Synthesizing module top_COREFFT_0_inBuffer in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = top_COREFFT_0_inBuffer_8_32s_1s_0s_19s @N:CG364 : fftDp.v(36) | Synthesizing module top_COREFFT_0_wrapRam in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 FPGA_FAMILY=32'b00000000000000000000000000010011 URAM_MAXDEPTH=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000010000000 SMARTGEN=32'b00000000000000000000000000000001 Generated name = top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s @N:CG364 : top_COREFFT_0_ram_smGen.v(5) | Synthesizing module top_COREFFT_0_ram_smGen in library COREFFT_LIB. Running optimization stage 1 on top_COREFFT_0_ram_smGen ....... Finished optimization stage 1 on top_COREFFT_0_ram_smGen (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 1 on top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s ....... Finished optimization stage 1 on top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) Running optimization stage 1 on top_COREFFT_0_inBuffer_8_32s_1s_0s_19s ....... Finished optimization stage 1 on top_COREFFT_0_inBuffer_8_32s_1s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) @W:CG133 : fftDp.v(267) | Object wA_bfly_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(268) | Object wA_load_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(270) | Object wEn_bfly_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(270) | Object wEn_odd_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(270) | Object wEn_even_r is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on top_COREFFT_0_inPlace_8_32s_1s_0s_19s ....... Finished optimization stage 1 on top_COREFFT_0_inPlace_8_32s_1s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 96MB peak: 97MB) @N:CG364 : kit.v(460) | Synthesizing module fft_inpl_switch in library COREFFT_LIB. DWIDTH=32'b00000000000000000000000000100000 Generated name = fft_inpl_switch_32s Running optimization stage 1 on fft_inpl_switch_32s ....... Finished optimization stage 1 on fft_inpl_switch_32s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : kit.v(326) | Synthesizing module fft_inpl_kitRndUp in library COREFFT_LIB. WIDTH_OUT=32'b00000000000000000000000000010000 RND_MODE=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitRndUp_16s_1s Running optimization stage 1 on fft_inpl_kitRndUp_16s_1s ....... Finished optimization stage 1 on fft_inpl_kitRndUp_16s_1s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : cmplx.v(442) | Synthesizing module fft_inpl_cmplx_rnd in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 RND=32'b00000000000000000000000000000001 P_WIDTH=32'b00000000000000000000000000101100 Generated name = fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s @N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt in library COREFFT_LIB. INWIDTH=32'b00000000000000000000000000010000 OUTWIDTH=32'b00000000000000000000000000010010 UNSIGNED=32'b00000000000000000000000000000000 Generated name = fft_inpl_signExt_16s_18s_0s Running optimization stage 1 on fft_inpl_signExt_16s_18s_0s ....... Finished optimization stage 1 on fft_inpl_signExt_16s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : mac_lib.v(36) | Synthesizing module fft_inpl_mac18x18mx in library COREFFT_LIB. WIDTH_A=32'b00000000000000000000000000010000 WIDTH_B=32'b00000000000000000000000000010000 BYPASS_REG_A=32'b00000000000000000000000000000000 BYPASS_REG_B=32'b00000000000000000000000000000000 BYPASS_REG_P=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 BY_REGA=2'b00 BY_REGB=2'b00 BY_REGP=2'b00 P_WIDTH=32'b00000000000000000000000000101100 Generated name = fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s @N:CG364 : smartfusion2.v(569) | Synthesizing module MACC in library work. Running optimization stage 1 on MACC ....... Finished optimization stage 1 on MACC (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @W:CG360 : mac_lib.v(69) | Removing wire sel_cdin, as there is no assignment to it. Running optimization stage 1 on fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s ....... Finished optimization stage 1 on fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt in library COREFFT_LIB. INWIDTH=32'b00000000000000000000000000101100 OUTWIDTH=32'b00000000000000000000000000100001 UNSIGNED=32'b00000000000000000000000000000000 Generated name = fft_inpl_signExt_44s_33s_0s Running optimization stage 1 on fft_inpl_signExt_44s_33s_0s ....... Finished optimization stage 1 on fft_inpl_signExt_44s_33s_0s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 MINUS=32'b00000000000000000000000000000001 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 P_WIDTH=32'b00000000000000000000000000101100 SUB=1'b1 DBG=32'b00000000000000000000000000000000 Generated name = fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitDelay_reg_16s_1s Running optimization stage 1 on fft_inpl_kitDelay_reg_16s_1s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_16s_1s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) Running optimization stage 1 on fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s ....... Finished optimization stage 1 on fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 MINUS=32'b00000000000000000000000000000000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 P_WIDTH=32'b00000000000000000000000000101100 SUB=1'b0 DBG=32'b00000000000000000000000000000000 Generated name = fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s Running optimization stage 1 on fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s ....... Finished optimization stage 1 on fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : cmplx.v(414) | Synthesizing module fft_inpl_cmplx_18 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 P_WIDTH=32'b00000000000000000000000000101100 Generated name = fft_inpl_cmplx_18_16s_0s_19s_44s Running optimization stage 1 on fft_inpl_cmplx_18_16s_0s_19s_44s ....... Finished optimization stage 1 on fft_inpl_cmplx_18_16s_0s_19s_44s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) Running optimization stage 1 on fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s ....... Finished optimization stage 1 on fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000100 Generated name = fft_inpl_kitDelay_reg_16s_4s Running optimization stage 1 on fft_inpl_kitDelay_reg_16s_4s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_16s_4s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000010 DELAY=32'b00000000000000000000000000000101 Generated name = fft_inpl_kitDelay_reg_2s_5s Running optimization stage 1 on fft_inpl_kitDelay_reg_2s_5s ....... Finished optimization stage 1 on fft_inpl_kitDelay_reg_2s_5s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : kit.v(499) | Synthesizing module fft_inpl_bfly2 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 TWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 TDWIDTH=32'b00000000000000000000000000100000 MPIPE=32'b00000000000000000000000000000011 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = fft_inpl_bfly2_16s_16s_32s_32s_3s_19s Running optimization stage 1 on fft_inpl_bfly2_16s_16s_32s_32s_3s_19s ....... Finished optimization stage 1 on fft_inpl_bfly2_16s_16s_32s_32s_3s_19s (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 97MB) @N:CG364 : twiddle32.v(27) | Synthesizing module top_COREFFT_0_twiddle in library COREFFT_LIB. TDWIDTH=32'b00000000000000000000000000100000 LOGPTS=32'b00000000000000000000000000001000 Generated name = top_COREFFT_0_twiddle_32s_8 Running optimization stage 1 on top_COREFFT_0_twiddle_32s_8 ....... Finished optimization stage 1 on top_COREFFT_0_twiddle_32s_8 (CPU Time 0h:00m:00s, Memory Used current: 97MB peak: 98MB) @N:CG364 : fftDp.v(369) | Synthesizing module top_COREFFT_0_twidLUT in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 TDWIDTH=32'b00000000000000000000000000100000 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = top_COREFFT_0_twidLUT_8_32s_0s_19s Running optimization stage 1 on top_COREFFT_0_twidLUT_8_32s_0s_19s ....... Finished optimization stage 1 on top_COREFFT_0_twidLUT_8_32s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(570) | Synthesizing module fft_inpl_autoScale in library COREFFT_LIB. SCALE_MODE=32'b00000000000000000000000000000000 SCALE_EXP_ON=32'b00000000000000000000000000000000 LOGLOGPTS=32'b00000000000000000000000000000100 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_autoScale_0s_0s_4_1s @W:CG133 : kit.v(590) | Object scale_exp_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : kit.v(590) | Object scale_exp_count is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on fft_inpl_autoScale_0s_0s_4_1s ....... Finished optimization stage 1 on fft_inpl_autoScale_0s_0s_4_1s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : COREFFT.v(28) | Synthesizing module top_COREFFT_0_COREFFT_INPLC in library COREFFT_LIB. INVERSE=32'b00000000000000000000000000000000 SCALE=32'b00000000000000000000000000000000 POINTS=32'b00000000000000000000000100000000 WIDTH=32'b00000000000000000000000000010000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 SCALE_EXP_ON=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 FLOGLOGPTS=32'b00000000000000000000000000000100 DWIDTH=32'b00000000000000000000000000100000 TWIDTH=32'b00000000000000000000000000010000 TDWIDTH=32'b00000000000000000000000000100000 HALFPTS=32'b00000000000000000000000010000000 MPIPE=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 Generated name = top_COREFFT_0_COREFFT_INPLC_Z2 @N:CG364 : fftDp.v(329) | Synthesizing module top_COREFFT_0_outBuff in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = top_COREFFT_0_outBuff_8_32s_0s_19s Running optimization stage 1 on top_COREFFT_0_outBuff_8_32s_0s_19s ....... Finished optimization stage 1 on top_COREFFT_0_outBuff_8_32s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @W:CG360 : COREFFT.v(86) | Removing wire outPQ, as there is no assignment to it. @W:CG360 : COREFFT.v(87) | Removing wire ctrl_outp, as there is no assignment to it. Running optimization stage 1 on top_COREFFT_0_COREFFT_INPLC_Z2 ....... Finished optimization stage 1 on top_COREFFT_0_COREFFT_INPLC_Z2 (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) Running optimization stage 1 on top_COREFFT_0_COREFFT_Z1 ....... @W:CL318 : COREFFT_TOP.v(86) | *Output RFS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFFT_TOP.v(86) | *Output OVFLOW_FLAG has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on top_COREFFT_0_COREFFT_Z1 (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG775 : COREFIR.v(28) | Component top_COREFIR_0_COREFIR not found in library "work" or "__hyper__lib__", but found in library COREFIR_LIB @N:CG364 : COREFIR.v(28) | Synthesizing module top_COREFIR_0_COREFIR in library COREFIR_LIB. CFG_ARCH=32'b00000000000000000000000000000001 COEF_SYMM=32'b00000000000000000000000000000001 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_UNSIGN=32'b00000000000000000000000000000000 SYSTOLIC=32'b00000000000000000000000000000000 INP_REG=32'b00000000000000000000000000000001 TAPS=32'b00000000000000000000000000011111 COEF_TYPE=32'b00000000000000000000000000000001 COEF_SETS=32'b00000000000000000000000000000001 COEF_WIDTH=32'b00000000000000000000000000010000 DATA_WIDTH=32'b00000000000000000000000000010000 COEF_RAM=32'b00000000000000000000000000000000 DATA_RAM=32'b00000000000000000000000000000000 SAMPLEID=32'b00000000000000000000000000000000 ID_WIDTH=32'b00000000000000000000000000001100 SAMPLE_RATE=32'b00000000000011110100001001000000 L=32'b00000000000000000000000000000010 M=32'b00000000000000000000000000000010 CLOCK_RATE=32'b00000000100110001001011010000000 FPGA_FAMILY=32'b00000000000000000000000000010011 DIE_SIZE=32'b00000000000000000000000000011001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 PERFORMANCE=32'b00000000000000000000000000000000 RADIX=32'b00000000000000000000000000001010 FPGA_FAMILYI=32'b00000000000000000000000000010011 clk_sample_rate=32'b00000000000000000000000000001010 FLOOR_PHY=32'b00000000000000000000000000000011 PHY_TAPS_FOLD=32'b00000000000000000000000000000100 PHY_TAPS_INTP=32'b00000000000000000000000000001111 Generated name = top_COREFIR_0_COREFIR_Z3 @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB. BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000010 Generated name = enum_kitDelay_reg_16s_2s Running optimization stage 1 on enum_kitDelay_reg_16s_2s ....... Finished optimization stage 1 on enum_kitDelay_reg_16s_2s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB. BITWIDTH=32'b00000000000000000000000000000100 DELAY=32'b00000000000000000000000000000010 Generated name = enum_kitDelay_reg_4s_2s Running optimization stage 1 on enum_kitDelay_reg_4s_2s ....... Finished optimization stage 1 on enum_kitDelay_reg_4s_2s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB. DELAY=32'b00000000000000000000000000000010 Generated name = enum_kitDelay_bit_reg_2s Running optimization stage 1 on enum_kitDelay_bit_reg_2s ....... Finished optimization stage 1 on enum_kitDelay_bit_reg_2s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB. DELAY=32'b00000000000000000000000000000100 Generated name = enum_kitDelay_bit_reg_4s Running optimization stage 1 on enum_kitDelay_bit_reg_4s ....... Finished optimization stage 1 on enum_kitDelay_bit_reg_4s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(185) | Synthesizing module enum_kitSync_ngrst in library COREFIR_LIB. PULSE_WIDTH=32'b00000000000000000000000000000001 Generated name = enum_kitSync_ngrst_1s @W:CG133 : kit.v(192) | Object tick2 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on enum_kitSync_ngrst_1s ....... Finished optimization stage 1 on enum_kitSync_ngrst_1s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB. DELAY=32'b00000000000000000000000000000011 Generated name = enum_kitDelay_bit_reg_3s Running optimization stage 1 on enum_kitDelay_bit_reg_3s ....... Finished optimization stage 1 on enum_kitDelay_bit_reg_3s (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB. DELAY=32'b00000000000000000000000000101101 Generated name = enum_kitDelay_bit_reg_45 Running optimization stage 1 on enum_kitDelay_bit_reg_45 ....... Finished optimization stage 1 on enum_kitDelay_bit_reg_45 (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) @N:CG364 : coef_store.v(54) | Synthesizing module top_COREFIR_0_wide_coef in library COREFIR_LIB. TAPS=32'b00000000000000000000000000010000 COEF_BITS=32'b00000000000000000000000000010000 COEF_SETS=32'b00000000000000000000000000000001 COEF_TYPE=32'b00000000000000000000000000000001 Generated name = top_COREFIR_0_wide_coef_16s_16s_1s_1s @N:CG364 : kit.v(142) | Synthesizing module enum_coef_sr in library COREFIR_LIB. TAPS=32'b00000000000000000000000000010000 COEF_WIDTH=32'b00000000000000000000000000010000 Generated name = enum_coef_sr_16s_16s Running optimization stage 1 on enum_coef_sr_16s_16s ....... Finished optimization stage 1 on enum_coef_sr_16s_16s (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) Running optimization stage 1 on top_COREFIR_0_wide_coef_16s_16s_1s_1s ....... Finished optimization stage 1 on top_COREFIR_0_wide_coef_16s_16s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : enum_fir.v(27) | Synthesizing module top_COREFIR_0_fir_enum_g4 in library COREFIR_LIB. TAPS=32'b00000000000000000000000000011111 COEF_TYPE=32'b00000000000000000000000000000001 COEF_SETS=32'b00000000000000000000000000000001 COEF_SYMM=32'b00000000000000000000000000000001 COEF_BITS=32'b00000000000000000000000000010000 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_BITS=32'b00000000000000000000000000010000 DATA_UNSIGN=32'b00000000000000000000000000000000 ACC_WIDTH=32'b00000000000000000000000000101100 SYSTOLIC=32'b00000000000000000000000000000000 VALID_O=32'b00000000000000000000000000000001 COLUMN=32'b00000000000000000000000000011100 XREG_COEF=32'b00000000000000000000000000000100 PERFORMANCE=32'b00000000000000000000000000000000 TAPS_PHY=32'b00000000000000000000000000001111 ODD_SYMM=32'b00000000000000000000000000000001 LATENCY1=32'b00000000000000000000000000000011 SYST=32'b00000000000000000000000000000001 XREGS=32'b00000000000000000000000000000000 LATENC2=32'b00000000000000000000000000011110 LATENC3=32'b00000000000000000000000000101101 LATENCY=32'b00000000000000000000000000101101 MAXDLY=32'b00000000000000000000000000011110 Generated name = top_COREFIR_0_fir_enum_g4_Z4 @N:CG364 : kit.v(116) | Synthesizing module enum_signExt in library COREFIR_LIB. INWIDTH=32'b00000000000000000000000000010000 OUTWIDTH=32'b00000000000000000000000000010010 UNSIGNED=32'b00000000000000000000000000000000 Generated name = enum_signExt_16s_18s_0s Running optimization stage 1 on enum_signExt_16s_18s_0s ....... Finished optimization stage 1 on enum_signExt_16s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : mac.v(64) | Synthesizing module top_COREFIR_0_mac_enum_g4 in library COREFIR_LIB. ACC_WIDTH=32'b00000000000000000000000000101100 CHAIN_BREAK=32'b00000000000000000000000000000000 XREG_COEF=32'b00000000000000000000000000000100 EXTEND=32'b00000000000000000000000000000000 EXT_WIDTH=32'b00000000000000000000000000000001 Generated name = top_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1 @N:CG364 : mac_lib.v(33) | Synthesizing module top_COREFIR_0_mac18x18_enum_g4 in library COREFIR_LIB. Running optimization stage 1 on top_COREFIR_0_mac18x18_enum_g4 ....... Finished optimization stage 1 on top_COREFIR_0_mac18x18_enum_g4 (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : mac.v(31) | Synthesizing module top_COREFIR_0_add2_g4 in library COREFIR_LIB. Running optimization stage 1 on top_COREFIR_0_add2_g4 ....... Finished optimization stage 1 on top_COREFIR_0_add2_g4 (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @W:CG360 : mac.v(90) | Removing wire cdout_ext, as there is no assignment to it. @W:CG360 : mac.v(90) | Removing wire cdin_ext, as there is no assignment to it. @W:CG360 : mac.v(91) | Removing wire pre_pout, as there is no assignment to it. @W:CG360 : mac.v(92) | Removing wire dumb, as there is no assignment to it. Running optimization stage 1 on top_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1 ....... Finished optimization stage 1 on top_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1 (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : mac.v(138) | Synthesizing module top_COREFIR_0_tap_enum_g4 in library COREFIR_LIB. COEF_SYMM=32'b00000000000000000000000000000001 COEF_BITS=32'b00000000000000000000000000010000 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_BITS=32'b00000000000000000000000000010000 DATA_UNSIGN=32'b00000000000000000000000000000000 ACC_WIDTH=32'b00000000000000000000000000101100 CHAIN_BREAK=32'b00000000000000000000000000000000 XREG_COEF=32'b00000000000000000000000000000100 Generated name = top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB. BITWIDTH=32'b00000000000000000000000000010010 DELAY=32'b00000000000000000000000000000001 Generated name = enum_kitDelay_reg_18s_1s Running optimization stage 1 on enum_kitDelay_reg_18s_1s ....... Finished optimization stage 1 on enum_kitDelay_reg_18s_1s (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg in library COREFIR_LIB. DELAY=32'b00000000000000000000000000000001 Generated name = enum_kitDelay_bit_reg_1s Running optimization stage 1 on enum_kitDelay_bit_reg_1s ....... Finished optimization stage 1 on enum_kitDelay_bit_reg_1s (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @W:CG360 : mac.v(168) | Removing wire coef_val, as there is no assignment to it. Running optimization stage 1 on top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s ....... Finished optimization stage 1 on top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB) @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg in library COREFIR_LIB. BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000001 Generated name = enum_kitDelay_reg_16s_1s Running optimization stage 1 on enum_kitDelay_reg_16s_1s ....... Finished optimization stage 1 on enum_kitDelay_reg_16s_1s (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) @N:CG364 : mac.v(241) | Synthesizing module top_COREFIR_0_odd_symmetry_tap_enum_g4 in library COREFIR_LIB. COEF_BITS=32'b00000000000000000000000000010000 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_BITS=32'b00000000000000000000000000010000 DATA_UNSIGN=32'b00000000000000000000000000000000 ACC_WIDTH=32'b00000000000000000000000000101100 XREG_COEF=32'b00000000000000000000000000000100 Generated name = top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s @W:CG360 : mac.v(266) | Removing wire coef_val, as there is no assignment to it. Running optimization stage 1 on top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s ....... Finished optimization stage 1 on top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) @W:CG133 : enum_fir.v(108) | Object filled is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : enum_fir.v(110) | Object add_valid_tick is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : enum_fir.v(110) | Object add_valid_tick2 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on top_COREFIR_0_fir_enum_g4_Z4 ....... Finished optimization stage 1 on top_COREFIR_0_fir_enum_g4_Z4 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) @N:CG364 : enum_COREFIR.v(47) | Synthesizing module top_COREFIR_0_COREENUMFIR_G4 in library COREFIR_LIB. TAPS=32'b00000000000000000000000000011111 COEF_TYPE=32'b00000000000000000000000000000001 COEF_SETS=32'b00000000000000000000000000000001 COEF_SYMM=32'b00000000000000000000000000000001 COEF_WIDTH=32'b00000000000000000000000000010000 COEF_SIGN=32'b00000000000000000000000000000000 DATA_WIDTH=32'b00000000000000000000000000010000 DATA_SIGN=32'b00000000000000000000000000000000 SYSTOLIC=32'b00000000000000000000000000000000 VALID_O=32'b00000000000000000000000000000001 INP_REG=32'b00000000000000000000000000000001 CASCADE=32'b00000000000000000000000000011100 PERFORMANCE=32'b00000000000000000000000000000000 OUT_WIDTH=32'b00000000000000000000000000100101 HW_WIDTH1=32'b00000000000000000000000000100101 HW_WIDTH=32'b00000000000000000000000000100101 ACC_WIDTH=32'b00000000000000000000000000101100 XREG_COEF=32'b00000000000000000000000000000100 WRAP_LAYERS=32'b00000000000000000000000000000010 Generated name = top_COREFIR_0_COREENUMFIR_G4_Z5 Running optimization stage 1 on top_COREFIR_0_COREENUMFIR_G4_Z5 ....... Finished optimization stage 1 on top_COREFIR_0_COREENUMFIR_G4_Z5 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) Running optimization stage 1 on top_COREFIR_0_COREFIR_Z3 ....... @W:CL318 : COREFIR.v(96) | *Output DATAO has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on top_COREFIR_0_COREFIR_Z3 (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB) @N:CG364 : DATA_HANDLE_FSM.v(24) | Synthesizing module DATAHANDLE_FSM in library work. DATA_WIDTH=32'b00000000000000000000000000010000 ADDR_WIDTH=32'b00000000000000000000000000010000 Generated name = DATAHANDLE_FSM_16s_16s @W:CG296 : DATA_HANDLE_FSM.v(109) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(111) | Referenced variable FIR_ENABLE is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(119) | Referenced variable FFT_RE_DATA is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(114) | Referenced variable FIR_DATA_OUT is not in sensitivity list. @W:CG290 : DATA_HANDLE_FSM.v(124) | Referenced variable FFT_IM_DATA is not in sensitivity list. Running optimization stage 1 on DATAHANDLE_FSM_16s_16s ....... @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal PRDATA[15:0]; possible missing assignment in an if or case statement. @A:CL282 : DATA_HANDLE_FSM.v(128) | Feedback mux created for signal COEF_WR_EN. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal FIR_RADDR[9:0]; possible missing assignment in an if or case statement. @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal FFT_RE_RADDR[9:0]; possible missing assignment in an if or case statement. @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal FFT_IM_RADDR[9:0]; possible missing assignment in an if or case statement. @W:CL190 : DATA_HANDLE_FSM.v(128) | Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : DATA_HANDLE_FSM.v(128) | Pruning unused register PREADY. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on DATAHANDLE_FSM_16s_16s (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : top_FFT_IM_Buffer_TPSRAM.v(5) | Synthesizing module top_FFT_IM_Buffer_TPSRAM in library work. Running optimization stage 1 on top_FFT_IM_Buffer_TPSRAM ....... Finished optimization stage 1 on top_FFT_IM_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : top_FFT_RE_Buffer_TPSRAM.v(5) | Synthesizing module top_FFT_RE_Buffer_TPSRAM in library work. Running optimization stage 1 on top_FFT_RE_Buffer_TPSRAM ....... Finished optimization stage 1 on top_FFT_RE_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : FILTER_CONTROL_FSM.v(22) | Synthesizing module FILTERCONTROL_FSM in library work. Running optimization stage 1 on FILTERCONTROL_FSM ....... Finished optimization stage 1 on FILTERCONTROL_FSM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : smartfusion2.v(729) | Synthesizing module CCC in library work. Running optimization stage 1 on CCC ....... Finished optimization stage 1 on CCC (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG364 : FIR_FILTER_CCC_0_FCCC.v(5) | Synthesizing module FIR_FILTER_CCC_0_FCCC in library work. Running optimization stage 1 on FIR_FILTER_CCC_0_FCCC ....... Finished optimization stage 1 on FIR_FILTER_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 1 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z6 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z6 ....... Finished optimization stage 1 on CoreAPB3_Z6 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z7 Running optimization stage 1 on CoreResetP_Z7 ....... @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreResetP_Z7 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. Running optimization stage 1 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 1 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. Running optimization stage 1 on RCOSC_25_50MHZ ....... Finished optimization stage 1 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : FIR_FILTER_FABOSC_0_OSC.v(5) | Synthesizing module FIR_FILTER_FABOSC_0_OSC in library work. Running optimization stage 1 on FIR_FILTER_FABOSC_0_OSC ....... @W:CL318 : FIR_FILTER_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : FIR_FILTER_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : FIR_FILTER_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : FIR_FILTER_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on FIR_FILTER_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. Running optimization stage 1 on INBUF ....... Finished optimization stage 1 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. Running optimization stage 1 on TRIBUFF ....... Finished optimization stage 1 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : FIR_FILTER_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. Running optimization stage 1 on MSS_075 ....... Finished optimization stage 1 on MSS_075 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : FIR_FILTER_MSS.v(9) | Synthesizing module FIR_FILTER_MSS in library work. Running optimization stage 1 on FIR_FILTER_MSS ....... Finished optimization stage 1 on FIR_FILTER_MSS (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : smartfusion2.v(720) | Synthesizing module SYSRESET in library work. Running optimization stage 1 on SYSRESET ....... Finished optimization stage 1 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : FIR_FILTER.v(9) | Synthesizing module FIR_FILTER in library work. Running optimization stage 1 on FIR_FILTER ....... Finished optimization stage 1 on FIR_FILTER (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : top_FIR_IN_Buffer_TPSRAM.v(5) | Synthesizing module top_FIR_IN_Buffer_TPSRAM in library work. Running optimization stage 1 on top_FIR_IN_Buffer_TPSRAM ....... Finished optimization stage 1 on top_FIR_IN_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : top_FIR_OUT_Buffer_TPSRAM.v(5) | Synthesizing module top_FIR_OUT_Buffer_TPSRAM in library work. Running optimization stage 1 on top_FIR_OUT_Buffer_TPSRAM ....... Finished optimization stage 1 on top_FIR_OUT_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on top_FIR_OUT_Buffer_TPSRAM ....... Finished optimization stage 2 on top_FIR_OUT_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on top_FIR_IN_Buffer_TPSRAM ....... Finished optimization stage 2 on top_FIR_IN_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on FIR_FILTER ....... Finished optimization stage 2 on FIR_FILTER (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on SYSRESET ....... Finished optimization stage 2 on SYSRESET (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on FIR_FILTER_MSS ....... Finished optimization stage 2 on FIR_FILTER_MSS (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on MSS_075 ....... Finished optimization stage 2 on MSS_075 (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on TRIBUFF ....... Finished optimization stage 2 on TRIBUFF (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on INBUF ....... Finished optimization stage 2 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on FIR_FILTER_FABOSC_0_OSC ....... @N:CL159 : FIR_FILTER_FABOSC_0_OSC.v(14) | Input XTL is unused. Finished optimization stage 2 on FIR_FILTER_FABOSC_0_OSC (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on RCOSC_25_50MHZ ....... Finished optimization stage 2 on RCOSC_25_50MHZ (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on RCOSC_25_50MHZ_FAB ....... Finished optimization stage 2 on RCOSC_25_50MHZ_FAB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) Running optimization stage 2 on CoreResetP_Z7 ....... @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused. Finished optimization stage 2 on CoreResetP_Z7 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on CoreAPB3_Z6 ....... @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. Finished optimization stage 2 on CoreAPB3_Z6 (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on FIR_FILTER_CCC_0_FCCC ....... Finished optimization stage 2 on FIR_FILTER_CCC_0_FCCC (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on CCC ....... Finished optimization stage 2 on CCC (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on FILTERCONTROL_FSM ....... @N:CL201 : FILTER_CONTROL_FSM.v(74) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Finished optimization stage 2 on FILTERCONTROL_FSM (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_FFT_RE_Buffer_TPSRAM ....... Finished optimization stage 2 on top_FFT_RE_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_FFT_IM_Buffer_TPSRAM ....... Finished optimization stage 2 on top_FFT_IM_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on DATAHANDLE_FSM_16s_16s ....... @N:CL201 : DATA_HANDLE_FSM.v(128) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : DATA_HANDLE_FSM.v(60) | Input port bits 15 to 12 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : DATA_HANDLE_FSM.v(60) | Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : DATA_HANDLE_FSM.v(59) | Input PENABLE is unused. @N:CL159 : DATA_HANDLE_FSM.v(58) | Input FILTER_COMPLETE is unused. Finished optimization stage 2 on DATAHANDLE_FSM_16s_16s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_COREENUMFIR_G4_Z5 ....... Finished optimization stage 2 on top_COREFIR_0_COREENUMFIR_G4_Z5 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s ....... Finished optimization stage 2 on top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on enum_kitDelay_reg_16s_1s ....... Finished optimization stage 2 on enum_kitDelay_reg_16s_1s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on enum_kitDelay_bit_reg_1s ....... Finished optimization stage 2 on enum_kitDelay_bit_reg_1s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on enum_kitDelay_reg_18s_1s ....... Finished optimization stage 2 on enum_kitDelay_reg_18s_1s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s ....... Finished optimization stage 2 on top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_add2_g4 ....... @N:CL159 : mac.v(42) | Input clkEn is unused. Finished optimization stage 2 on top_COREFIR_0_add2_g4 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_mac18x18_enum_g4 ....... Finished optimization stage 2 on top_COREFIR_0_mac18x18_enum_g4 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1 ....... Finished optimization stage 2 on top_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on enum_signExt_16s_18s_0s ....... Finished optimization stage 2 on enum_signExt_16s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on top_COREFIR_0_fir_enum_g4_Z4 ....... Finished optimization stage 2 on top_COREFIR_0_fir_enum_g4_Z4 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 104MB) Running optimization stage 2 on enum_coef_sr_16s_16s ....... Finished optimization stage 2 on enum_coef_sr_16s_16s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on top_COREFIR_0_wide_coef_16s_16s_1s_1s ....... @N:CL159 : coef_store.v(67) | Input set is unused. Finished optimization stage 2 on top_COREFIR_0_wide_coef_16s_16s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitDelay_bit_reg_45 ....... @N:CL135 : kit.v(55) | Found sequential shift genblk1.delayLine with address depth of 45 words and data bit width of 1. Finished optimization stage 2 on enum_kitDelay_bit_reg_45 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitDelay_bit_reg_3s ....... @N:CL135 : kit.v(55) | Found sequential shift genblk1.delayLine with address depth of 3 words and data bit width of 1. Finished optimization stage 2 on enum_kitDelay_bit_reg_3s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitSync_ngrst_1s ....... Finished optimization stage 2 on enum_kitSync_ngrst_1s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitDelay_bit_reg_4s ....... @N:CL135 : kit.v(55) | Found sequential shift genblk1.delayLine with address depth of 4 words and data bit width of 1. Finished optimization stage 2 on enum_kitDelay_bit_reg_4s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitDelay_bit_reg_2s ....... Finished optimization stage 2 on enum_kitDelay_bit_reg_2s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitDelay_reg_4s_2s ....... Finished optimization stage 2 on enum_kitDelay_reg_4s_2s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on enum_kitDelay_reg_16s_2s ....... Finished optimization stage 2 on enum_kitDelay_reg_16s_2s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on top_COREFIR_0_COREFIR_Z3 ....... @N:CL159 : COREFIR.v(90) | Input COEF_REF is unused. @N:CL159 : COREFIR.v(92) | Input SAMPLE_ID is unused. @N:CL159 : COREFIR.v(93) | Input RCLK is unused. Finished optimization stage 2 on top_COREFIR_0_COREFIR_Z3 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on top_COREFFT_0_outBuff_8_32s_0s_19s ....... Finished optimization stage 2 on top_COREFFT_0_outBuff_8_32s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on top_COREFFT_0_COREFFT_INPLC_Z2 ....... Finished optimization stage 2 on top_COREFFT_0_COREFFT_INPLC_Z2 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on fft_inpl_autoScale_0s_0s_4_1s ....... @A:CL153 : kit.v(590) | *Unassigned bits of scale_exp_r[3:0] are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : kit.v(584) | Input fftRd_done_tick is unused. Finished optimization stage 2 on fft_inpl_autoScale_0s_0s_4_1s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on top_COREFFT_0_twidLUT_8_32s_0s_19s ....... Finished optimization stage 2 on top_COREFFT_0_twidLUT_8_32s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on top_COREFFT_0_twiddle_32s_8 ....... Finished optimization stage 2 on top_COREFFT_0_twiddle_32s_8 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on fft_inpl_bfly2_16s_16s_32s_32s_3s_19s ....... @W:CL260 : kit.v(560) | Pruning register bit 16 of outQ[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 2 on fft_inpl_bfly2_16s_16s_32s_32s_3s_19s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_2s_5s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_2s_5s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_16s_4s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_16s_4s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_cmplx_18_16s_0s_19s_44s ....... Finished optimization stage 2 on fft_inpl_cmplx_18_16s_0s_19s_44s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s ....... Finished optimization stage 2 on fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_16s_1s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_16s_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s ....... Finished optimization stage 2 on fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_signExt_44s_33s_0s ....... @W:CL246 : kit.v(369) | Input port bits 42 to 32 of inp[43:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on fft_inpl_signExt_44s_33s_0s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on MACC ....... Finished optimization stage 2 on MACC (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s ....... Finished optimization stage 2 on fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_signExt_16s_18s_0s ....... Finished optimization stage 2 on fft_inpl_signExt_16s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s ....... Finished optimization stage 2 on fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitRndUp_16s_1s ....... Finished optimization stage 2 on fft_inpl_kitRndUp_16s_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_switch_32s ....... Finished optimization stage 2 on fft_inpl_switch_32s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on top_COREFFT_0_ram_smGen ....... Finished optimization stage 2 on top_COREFFT_0_ram_smGen (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s ....... Finished optimization stage 2 on top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on top_COREFFT_0_inBuffer_8_32s_1s_0s_19s ....... Finished optimization stage 2 on top_COREFFT_0_inBuffer_8_32s_1s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on top_COREFFT_0_inPlace_8_32s_1s_0s_19s ....... @N:CL159 : fftDp.v(258) | Input load is unused. Finished optimization stage 2 on top_COREFFT_0_inPlace_8_32s_1s_0s_19s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_sm_top_256s_128s_8_3_10s_1s ....... Finished optimization stage 2 on fft_inpl_sm_top_256s_128s_8_3_10s_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_outBufA_256s_8_1s ....... @N:CL159 : fftSm.v(549) | Input rTimerTC_tick is unused. Finished optimization stage 2 on fft_inpl_outBufA_256s_8_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_3_2s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_3_2s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_twid_wA_gen_8_3 ....... Finished optimization stage 2 on fft_inpl_twid_wA_gen_8_3 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_bcounter_7 ....... Finished optimization stage 2 on fft_inpl_bcounter_7 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitSync_ngrst_1s ....... Finished optimization stage 2 on fft_inpl_kitSync_ngrst_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_4s ....... Finished optimization stage 2 on fft_inpl_kitDelay_bit_reg_4s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_twid_rA_8_3 ....... Finished optimization stage 2 on fft_inpl_twid_rA_8_3 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_inBuf_fftA_pipe_8_3 ....... Finished optimization stage 2 on fft_inpl_inBuf_fftA_pipe_8_3 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_inBuf_ldA_256s_8 ....... @N:CL159 : fftSm.v(493) | Input clkEn is unused. Finished optimization stage 2 on fft_inpl_inBuf_ldA_256s_8 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_counter_8_255s ....... Finished optimization stage 2 on fft_inpl_counter_8_255s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_1s_10s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_1s_10s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_7_2s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_7_2s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitCountS_7_127s_0s ....... Finished optimization stage 2 on fft_inpl_kitCountS_7_127s_0s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_1s ....... Finished optimization stage 2 on fft_inpl_kitDelay_bit_reg_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_5_2s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_5_2s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_reg_10_2s ....... Finished optimization stage 2 on fft_inpl_kitDelay_reg_10_2s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_rdFFTtimer_128s_8_3_10s_1s ....... Finished optimization stage 2 on fft_inpl_rdFFTtimer_128s_8_3_10s_1s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_3s ....... Finished optimization stage 2 on fft_inpl_kitDelay_bit_reg_3s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_counter_5_7 ....... Finished optimization stage 2 on fft_inpl_counter_5_7 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_counter_w_10_137s ....... Finished optimization stage 2 on fft_inpl_counter_w_10_137s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitEdge_0s ....... Finished optimization stage 2 on fft_inpl_kitEdge_0s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_2s ....... Finished optimization stage 2 on fft_inpl_kitDelay_bit_reg_2s (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on fft_inpl_slowClock ....... Finished optimization stage 2 on fft_inpl_slowClock (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on top_COREFFT_0_COREFFT_Z1 ....... @N:CL159 : COREFFT_TOP.v(85) | Input CLKEN is unused. @N:CL159 : COREFFT_TOP.v(85) | Input RST is unused. @N:CL159 : COREFFT_TOP.v(85) | Input START is unused. @N:CL159 : COREFFT_TOP.v(85) | Input INVERSE_STRM is unused. @N:CL159 : COREFFT_TOP.v(85) | Input REFRESH is unused. Finished optimization stage 2 on top_COREFFT_0_COREFFT_Z1 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on top_Coef_Buffer_TPSRAM ....... Finished optimization stage 2 on top_Coef_Buffer_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) Running optimization stage 2 on RAM1K18 ....... Finished optimization stage 2 on RAM1K18 (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB) For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:50s; CPU Time elapsed 0h:00m:46s; Memory used current: 106MB peak: 106MB) Process took 0h:00m:50s realtime, 0h:00m:46s cputime Process completed successfully. # Sun May 30 18:58:14 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode @N:NF107 : top.v(9) | Selected library: work cell: top view verilog as top level @N:NF107 : top.v(9) | Selected library: work cell: top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun May 30 18:58:15 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:51s; CPU Time elapsed 0h:00m:47s; Memory used current: 22MB peak: 31MB) Process took 0h:00m:51s realtime, 0h:00m:47s cputime Process completed successfully. # Sun May 30 18:58:15 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202009synp2, Build 102R, Built Feb 17 2021 10:19:36, @ @N: : | Running in 64-bit mode @N:NF107 : top.v(9) | Selected library: work cell: top view verilog as top level @N:NF107 : top.v(9) | Selected library: work cell: top view verilog as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sun May 30 18:58:17 2021 ###########################################################] Premap Report # Sun May 30 18:58:18 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 130MB) Reading constraint file: C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(8) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB) @W:BN132 : fftsm.v(675) | Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:FX1171 : kit.v(599) | Found instance COREFFT_0.genblk1.DUT_INPLACE.autoScale_0.bflyMonitor with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : kit.v(599) | Found instance COREFFT_0.genblk1.DUT_INPLACE.autoScale_0.ldMonitor with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:BN132 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : corefft_top.v(86) | Tristate driver OVFLOW_FLAG (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) on net OVFLOW_FLAG (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) has its enable tied to GND. @N:MO111 : corefft_top.v(86) | Tristate driver RFS (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) on net RFS (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_1 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_1 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_2 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_2 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_3 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_3 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_4 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_4 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_5 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_5 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_6 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_6 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_7 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_7 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_8 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_8 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(676) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance FIR_FILTER_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(769) | Sequential instance FIR_FILTER_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(676) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(695) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(714) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(733) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1388) | Sequential instance FIR_FILTER_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_1(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_1(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_1(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_0(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_0(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_3(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_0(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_2(verilog) because it does not drive other instances. @N:BN115 : cmplx.v(407) | Removing instance signExt_p (in view: COREFFT_LIB.fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_44s_33s_0s_0(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_3(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_4(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_3(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_0(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_2(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_6(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s_2(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_5(verilog) because it does not drive other instances. @N:BN115 : cmplx.v(407) | Removing instance signExt_p (in view: COREFFT_LIB.fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_44s_33s_0s_1(verilog) because it does not drive other instances. @N:BN362 : corefft.v(229) | Removing sequential instance buf_ready_r (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_INPLC_Z2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_14(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_2(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_14(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_1(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_14(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_0(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_13(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_2(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_13(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_1(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_13(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_0(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_12(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_5(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_12(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_4(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_12(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_3(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_11(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_8(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_11(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_7(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_11(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_6(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_10(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_11(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_10(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_10(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_10(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_9(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_9(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_14(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_9(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_13(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_9(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_12(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_8(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_17(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_8(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_16(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_8(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_15(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_7(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_20(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_7(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_19(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_7(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_18(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_6(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_23(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_6(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_22(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_6(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_21(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_5(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_26(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_5(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_25(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_5(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_24(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_4(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_29(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_4(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_28(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_4(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_27(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_3(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_32(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_3(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_31(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_3(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_30(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_2(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_35(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_2(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_34(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_2(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_33(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_1(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_38(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_1(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_37(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_1(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_36(verilog) because it does not drive other instances. @N:BN115 : mac.v(192) | Removing instance symm_tap\.signExt_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_0(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_41(verilog) because it does not drive other instances. @N:BN115 : mac.v(197) | Removing instance symm_tap\.signExt_symm_data (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_0(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_40(verilog) because it does not drive other instances. @N:BN115 : mac.v(220) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s_0(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_39(verilog) because it does not drive other instances. @N:BN115 : mac.v(281) | Removing instance signExt_data (in view: COREFIR_LIB.top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_4_42(verilog) because it does not drive other instances. @N:BN115 : mac.v(293) | Removing instance signExt_coef (in view: COREFIR_LIB.top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s(verilog)) of type view:COREFIR_LIB.enum_signExt_16s_18s_0s_3(verilog) because it does not drive other instances. @N:BN115 : enum_corefir.v(108) | Removing instance wrap_coef_sel (in view: COREFIR_LIB.top_COREFIR_0_COREENUMFIR_G4_Z5(verilog)) of type view:COREFIR_LIB.enum_kitDelay_reg_4s_2s(verilog) because it does not drive other instances. @N:BN362 : fftsm.v(675) | Removing sequential instance swCross (in view: COREFFT_LIB.fft_inpl_inBuf_fftA_pipe_8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : fftsm.v(265) | Removing sequential instance fftRd_done_tick (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : kit.v(218) | Removing sequential instance pulse (in view: COREFIR_LIB.enum_kitSync_ngrst_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : filter_control_fsm.v(74) | Removing sequential instance FILTER_COMPLETE (in view: work.FILTERCONTROL_FSM(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : corefft.v(229) | Removing sequential instance datao_valid_r (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_INPLC_Z2(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : kit.v(200) | Removing sequential instance tick1 (in view: COREFIR_LIB.enum_kitSync_ngrst_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN115 : fftsm.v(582) | Removing instance bit_dly_1 (in view: COREFFT_LIB.fft_inpl_outBufA_256s_8_1s(verilog)) of type view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine\[2\] (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z7(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine\[1\] (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine\[0\] (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=109 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 195MB) @W:MT686 : synthesis.fdc(8) | No path from master pin (-source) to source of clock FIR_FILTER_0/CCC_0/GL0 Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz 20.000 declared default_clkgroup 15 1 . FIR_FILTER_0/CCC_0/GL0 100.0 MHz 10.000 generated (from FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup 2334 0 - System 100.0 MHz 10.000 system system_clkgroup 46 0 - fft_inpl_slowClock|divider_inferred_clock[2] 100.0 MHz 10.000 inferred Inferred_clkgroup_0 17 ======================================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 15 FIR_FILTER_0.FABOSC_0.I_RCOSC_25_50MHZ.CLKOUT(RCOSC_25_50MHZ) FIR_FILTER_0.CORERESETP_0.release_sdif0_core.C - FIR_FILTER_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB.A(RCOSC_25_50MHZ_FAB) FIR_FILTER_0/CCC_0/GL0 2334 FIR_FILTER_0.CCC_0.CCC_INST.GL0(CCC) FIR_OUT_Buffer.top_FIR_OUT_Buffer_TPSRAM_R0C0.B_CLK - FIR_FILTER_0.CCC_0.GL0_INST.I(BUFG) System 46 - DATAHANDLE_FSM_0.FFT_IM_RADDR[9:0].C - - fft_inpl_slowClock|divider_inferred_clock[2] 17 COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2:0].Q[2](dffr) COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0.B_CLK - COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.slowClk.I[0](inv) ======================================================================================================================================================================================================================================================================================================================================= @W:MT532 : data_handle_fsm.v(111) | Found signal identified as System clock which controls 46 sequential elements including DATAHANDLE_FSM_0.PRDATA[15:0]. Using this clock, which has no specified timing constraint, can adversely impact design performance. @W:MT530 : kit.v(203) | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 17 sequential elements including COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine\[3\]. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 191MB peak: 196MB) Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_16s_16s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(128) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_16s_16s(verilog)); safe FSM implementation is not required. Encoding state machine fsm[4:0] (in view: work.FILTERCONTROL_FSM(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Finished constraint checker preprocessing (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 196MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 197MB peak: 197MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 105MB peak: 197MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Sun May 30 18:58:22 2021 ###########################################################] Map & Optimize Report # Sun May 30 18:58:23 2021 Copyright (C) 1994-2021 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: R-2020.09M-SP1-1 Install: C:\Microsemi\Libero_SoC_v2021.1\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202009act, Build 069R, Built Mar 17 2021 10:25:05, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 130MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 130MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 130MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 169MB) @N:MO111 : corefft_top.v(86) | Tristate driver OVFLOW_FLAG (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) on net OVFLOW_FLAG (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) has its enable tied to GND. @N:MO111 : corefft_top.v(86) | Tristate driver RFS (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) on net RFS (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_Z1(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_1 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_1 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_2 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_2 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_3 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_3 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_4 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_4 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_5 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_5 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_6 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_6 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_7 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_7 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @N:MO111 : corefir.v(96) | Tristate driver DATAO_8 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) on net DATAO_8 (in view: COREFIR_LIB.top_COREFIR_0_COREFIR_Z3(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(963) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(946) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(929) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(244) | Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_1.genblk1.dly_d.genblk1.delayLine[0][15:0] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_0.genblk1.dly_d.genblk1.delayLine[0][15:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[6].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[0].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[7].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[14].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[12].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[3].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[10].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[8].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[11].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[5].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[9].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[1].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[2].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[13].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[4].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. #### START OF SSF LOG MESSAGES #### #### END OF SSF LOG MESSAGES #### Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 180MB peak: 180MB) @N:MO231 : kit.v(111) | Found counter in view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) instance wTimer_0.Q[6:0] @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[1\][3] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[1\][4] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[1\][7] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[1\][8] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[1\][9] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[0\][3] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[0\][4] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[0\][7] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[0\][8] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[0\][9] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:MO231 : kit.v(139) | Found counter in view:COREFFT_LIB.fft_inpl_counter_w_10_137s(verilog) instance Q[9:0] @N:MO231 : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_5_7(verilog) instance Q[4:0] @N:MO231 : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_8_255s(verilog) instance Q[7:0] @N:MO231 : kit.v(168) | Found counter in view:COREFFT_LIB.fft_inpl_twid_wA_gen_8_3(verilog) instance slowTimer.Q[6:0] Encoding state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_16s_16s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(128) | There are no possible illegal states for state machine fsm[3:0] (in view: work.DATAHANDLE_FSM_16s_16s(verilog)); safe FSM implementation is not required. Encoding state machine fsm[4:0] (in view: work.FILTERCONTROL_FSM(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N:MO231 : filter_control_fsm.v(74) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance COEF_RADDR[5:0] @N:MO231 : filter_control_fsm.v(74) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance FFT_WADDR[9:0] @N:MO231 : filter_control_fsm.v(74) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance FIR_WR_ADDR[9:0] Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 185MB peak: 185MB) @N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[3] (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_INPLC_Z2(verilog)) because it does not drive other instances. @N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[4] (in view: COREFFT_LIB.top_COREFFT_0_COREFFT_INPLC_Z2(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.INIT_DONE_int (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[6] (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 187MB peak: 187MB) Available hyper_sources - for debug and ip models None Found Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 187MB peak: 191MB) @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[6\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[6\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[0\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[0\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[7\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[7\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[14\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[14\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[12\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[12\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[3\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[3\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[10\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[10\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[8\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[8\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[11\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[11\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[5\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[5\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[9\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[9\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[1\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[1\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[2\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[2\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[13\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[13\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : kit.v(90) | Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[4\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[4\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance. Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 188MB peak: 191MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 188MB peak: 191MB) @W:BN132 : fftsm.v(675) | Removing instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.offsetPQ_r1[6] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.mask1_r[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : fftsm.v(675) | Removing instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_rA_0.offsetPQ_r1[6] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_rA_0.mask1_r[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 188MB peak: 191MB) @N:MO106 : twiddle32.v(35) | Found ROM COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1[31:0] (in view: work.top(verilog)) with 128 words by 32 bits. @N:BN362 : coreresetp.v(1549) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif2_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1517) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif1_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1485) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif0_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif3_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif2_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif1_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif0_core_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.ddr_settled_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(963) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q2 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(929) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(856) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(755) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif3_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif2_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif1_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif0_core_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.ddr_settled_clk_base (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1613) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.ddr_settled (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1581) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.release_sdif3_core (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(912) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(912) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif3_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(898) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(898) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif2_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(884) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(884) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif1_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(870) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif0_areset_n_rcosc (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[4] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[2] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[0] (in view: work.top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 191MB peak: 191MB) Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 193MB peak: 193MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:07s 2.08ns 1592 / 2184 @N:FP130 : | Promoting Net MSS_HPMS_READY_int_arst on CLKINT I_382 @N:FP130 : | Promoting Net COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider_i_0[2] on CLKINT I_383 @N:FP130 : | Promoting Net DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 on CLKINT I_384 @N:FP130 : | Promoting Net DATAHANDLE_FSM_0.FIR_RADDR4 on CLKINT I_385 @N:FP130 : | Promoting Net DATAHANDLE_FSM_0.FIR_RADDR5 on CLKINT I_386 @N:FP130 : | Promoting Net DATAHANDLE_FSM_0.FIR_RADDR3 on CLKINT I_387 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 196MB peak: 196MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 198MB peak: 198MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 2310 clock pin(s) of sequential element(s) 0 instances converted, 2310 sequential instances remain driven by gated/generated clocks ====================================================================================================== Gated/Generated Clocks ====================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 FIR_FILTER_0.CCC_0.CCC_INST CCC 2247 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ClockId0002 COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2] SLE 17 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.twid_wEn No gated clock conversion method for cell cell:ACG4.SLE ClockId0003 DATAHANDLE_FSM_0.FIR_RADDR3 CFG2 46 DATAHANDLE_FSM_0.FIR_RADDR[0] No gated clock conversion method for cell cell:ACG4.SLE ==================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 157MB peak: 198MB) Writing Analyst data base C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 199MB peak: 199MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Writing FDC file C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\top_synplify.fdc Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 202MB peak: 202MB) Finished Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 203MB) Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 196MB peak: 203MB) @W:MT246 : fir_filter_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT with period 20.00ns @N:MT615 : | Found clock FIR_FILTER_0/CCC_0/GL0 with period 10.00ns @W:MT420 : | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] with period 10.00ns. Please declare a user-defined clock on net COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2]. ##### START OF TIMING REPORT #####[ # Timing report written on Sun May 30 18:58:38 2021 # Top view: top Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 2.892 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_0/CCC_0/GL0 100.0 MHz 140.7 MHz 10.000 7.108 2.892 generated (from FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT) default_clkgroup FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 50.0 MHz NA 20.000 NA NA declared default_clkgroup fft_inpl_slowClock|divider_inferred_clock[2] 100.0 MHz 155.1 MHz 10.000 6.446 3.554 inferred Inferred_clkgroup_0 System 100.0 MHz 381.3 MHz 10.000 2.622 7.378 system system_clkgroup ========================================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System FIR_FILTER_0/CCC_0/GL0 | 10.000 7.378 | No paths - | No paths - | No paths - FIR_FILTER_0/CCC_0/GL0 System | 10.000 4.830 | No paths - | No paths - | No paths - FIR_FILTER_0/CCC_0/GL0 FIR_FILTER_0/CCC_0/GL0 | 10.000 2.892 | No paths - | No paths - | No paths - fft_inpl_slowClock|divider_inferred_clock[2] FIR_FILTER_0/CCC_0/GL0 | No paths - | No paths - | No paths - | Diff grp - fft_inpl_slowClock|divider_inferred_clock[2] fft_inpl_slowClock|divider_inferred_clock[2] | No paths - | 10.000 3.554 | No paths - | No paths - ================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: FIR_FILTER_0/CCC_0/GL0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[12] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[12] 3.046 2.892 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[15] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[15] 3.056 2.919 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_SEL FIR_FILTER_MSS_TMP_0_FIC_0_APB_MASTER_PSELx 3.083 3.264 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[13] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[13] 3.017 3.387 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[14] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[14] 3.012 3.430 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[6] DATAHANDLE_FSM_0_FIR_WADDR[4] 3.131 3.943 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[7] DATAHANDLE_FSM_0_FIR_WADDR[5] 3.033 3.982 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[8] DATAHANDLE_FSM_0_FIR_WADDR[6] 3.128 4.006 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[3] DATAHANDLE_FSM_0_FIR_WADDR[1] 3.035 4.040 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_ADDR[2] DATAHANDLE_FSM_0_FIR_WADDR[0] 3.014 4.094 ============================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[2] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] 8.802 2.892 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[13] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[13] 8.992 3.082 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[15] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[15] 9.009 3.099 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[14] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[14] 9.032 3.122 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[9] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[9] 9.065 3.155 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[1] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[1] 9.084 3.174 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[7] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[7] 9.099 3.189 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[8] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[8] 9.104 3.194 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[12] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[12] 9.108 3.198 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_0/CCC_0/GL0 MSS_075 F_HM0_RDATA[4] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[4] 9.109 3.199 ========================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.198 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.802 - Propagation time: 5.910 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 2.892 Number of logic level(s): 3 Starting point: FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[12] Ending point: FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by FIR_FILTER_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE The end point is clocked by FIR_FILTER_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[12] Out 3.046 3.046 r - FIR_FILTER_0_AMBA_SLAVE_0_PADDR[12] Net - - 0.216 - 1 FIR_FILTER_0.CoreAPB3_0.iPSELS_1[0] CFG2 B In - 3.262 r - FIR_FILTER_0.CoreAPB3_0.iPSELS_1[0] CFG2 Y Out 0.125 3.387 f - iPSELS_1[0] Net - - 0.216 - 1 FIR_FILTER_0.CoreAPB3_0.iPSELS[0] CFG4 D In - 3.603 f - FIR_FILTER_0.CoreAPB3_0.iPSELS[0] CFG4 Y Out 0.250 3.853 f - FIR_FILTER_0_AMBA_SLAVE_0_PSELx Net - - 1.010 - 18 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST_RNO_1 CFG2 A In - 4.863 f - FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST_RNO_1 CFG2 Y Out 0.076 4.939 f - FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] Net - - 0.971 - 1 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 5.910 f - ============================================================================================================================== Total path delay (propagation time + setup) of 7.108 is 4.694(66.0%) logic and 2.413(34.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: fft_inpl_slowClock|divider_inferred_clock[2] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[2] 0.076 3.554 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[1] 0.094 3.609 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[0] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[0] 0.094 4.309 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[3] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[3] 0.094 5.023 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[4] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[4] 0.094 5.414 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[5] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[5] 0.094 7.051 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[6] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[6] 0.094 7.204 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.pulse fft_inpl_slowClock|divider_inferred_clock[2] SLE Q pulse 0.094 8.202 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.twid_wEn fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wEn_w 0.094 8.763 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine\[3\] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q synced_ngrst 0.076 8.986 ======================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[0] N_35_i 9.708 3.554 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[7] twidData_w[7] 9.708 4.199 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[10] twidData_w[9] 9.708 4.307 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[4] twidData_w[4] 9.708 4.322 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[11] twidData_w[10] 9.708 4.394 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[12] twidData_w[11] 9.708 4.408 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[13] twidData_w[12] 9.708 4.432 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[5] twidData_w[5] 9.708 4.493 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[6] twidData_w[6] 9.708 4.524 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[3] N_110_i 9.708 4.636 ============================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.292 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.708 - Propagation time: 6.154 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.554 Number of logic level(s): 7 Starting point: COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] / Q Ending point: COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 / B_DIN[0] The start point is clocked by fft_inpl_slowClock|divider_inferred_clock[2] [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by fft_inpl_slowClock|divider_inferred_clock[2] [falling] (rise=0.000 fall=5.000 period=10.000) on pin B_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] SLE Q Out 0.076 0.076 r - twid_wA_w[2] Net - - 1.631 - 83 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m2 CFG2 A In - 1.707 r - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m2 CFG2 Y Out 0.087 1.794 f - m2 Net - - 0.995 - 16 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m3 CFG3 C In - 2.789 f - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m3 CFG3 Y Out 0.182 2.971 f - m3 Net - - 0.648 - 3 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m11_1 CFG4 D In - 3.619 f - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m11_1 CFG4 Y Out 0.250 3.870 f - m11_1 Net - - 0.432 - 2 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m11_2_1 CFG4 C In - 4.302 f - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m11_2_1 CFG4 Y Out 0.196 4.498 r - m11_2_1 Net - - 0.216 - 1 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m11_2 CFG4 B In - 4.714 r - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m11_2 CFG4 Y Out 0.143 4.857 r - m11_2 Net - - 0.216 - 1 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m20 CFG3 C In - 5.073 r - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m20 CFG3 Y Out 0.196 5.270 f - m20 Net - - 0.432 - 2 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.N_35_i CFG3 C In - 5.702 f - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.N_35_i CFG3 Y Out 0.182 5.884 f - N_35_i Net - - 0.270 - 1 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.top_COREFFT_0_ram_smGen_R0C0 RAM1K18 B_DIN[0] In - 6.154 f - ============================================================================================================================================================================= Total path delay (propagation time + setup) of 6.446 is 1.606(24.9%) logic and 4.840(75.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- DATAHANDLE_FSM_0.PRDATA[2] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[2] 0.094 7.378 DATAHANDLE_FSM_0.PRDATA[13] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[13] 0.094 7.567 DATAHANDLE_FSM_0.PRDATA[15] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[15] 0.094 7.585 DATAHANDLE_FSM_0.PRDATA[14] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[14] 0.094 7.607 DATAHANDLE_FSM_0.PRDATA[9] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[9] 0.094 7.641 DATAHANDLE_FSM_0.PRDATA[1] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[1] 0.094 7.660 DATAHANDLE_FSM_0.PRDATA[7] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[7] 0.094 7.675 DATAHANDLE_FSM_0.PRDATA[8] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[8] 0.094 7.679 DATAHANDLE_FSM_0.PRDATA[12] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[12] 0.094 7.684 DATAHANDLE_FSM_0.PRDATA[4] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[4] 0.094 7.684 ========================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------ FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[2] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] 8.802 7.378 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[13] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[13] 8.992 7.567 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[15] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[15] 9.009 7.585 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[14] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[14] 9.032 7.607 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[9] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[9] 9.065 7.641 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[1] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[1] 9.084 7.660 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[7] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[7] 9.099 7.675 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[8] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[8] 9.104 7.679 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[12] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[12] 9.108 7.684 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[4] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[4] 9.109 7.684 ============================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.198 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.802 - Propagation time: 1.425 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 7.377 Number of logic level(s): 1 Starting point: DATAHANDLE_FSM_0.PRDATA[2] / Q Ending point: FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by System [rising] on pin CLK The end point is clocked by FIR_FILTER_0/CCC_0/GL0 [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ DATAHANDLE_FSM_0.PRDATA[2] SLE Q Out 0.094 0.094 f - FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[2] Net - - 0.216 - 1 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST_RNO_1 CFG2 B In - 0.310 f - FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST_RNO_1 CFG2 Y Out 0.143 0.453 f - FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] Net - - 0.971 - 1 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 1.425 f - ============================================================================================================================== Total path delay (propagation time + setup) of 2.623 is 1.435(54.7%) logic and 1.188(45.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(9) | Timing constraint (through [get_nets { FIR_FILTER_0.CORERESETP_0.ddr_settled FIR_FILTER_0.CORERESETP_0.count_ddr_enable FIR_FILTER_0.CORERESETP_0.release_sdif*_core FIR_FILTER_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(10) | Timing constraint (from [get_cells { FIR_FILTER_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(11) | Timing constraint (from [get_cells { FIR_FILTER_0.CORERESETP_0.MSS_HPMS_READY_int FIR_FILTER_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { FIR_FILTER_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(12) | Timing constraint (through [get_nets { FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE FIR_FILTER_0.CORERESETP_0.SDIF*_PERST_N FIR_FILTER_0.CORERESETP_0.SDIF*_PSEL FIR_FILTER_0.CORERESETP_0.SDIF*_PWRITE FIR_FILTER_0.CORERESETP_0.SDIF*_PRDATA[*] FIR_FILTER_0.CORERESETP_0.SOFT_EXT_RESET_OUT FIR_FILTER_0.CORERESETP_0.SOFT_RESET_F2M FIR_FILTER_0.CORERESETP_0.SOFT_M3_RESET FIR_FILTER_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_FDDR_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design @W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_pins { FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(14) | Timing constraint (through [get_pins { FIR_FILTER_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 198MB peak: 203MB) Finished timing report (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 198MB peak: 203MB) --------------------------------------- Resource Usage Report for top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 7 uses MSS_075 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 7 uses CFG2 183 uses CFG3 638 uses CFG4 170 uses Carry cells: ARI1 441 uses - used for arithmetic functions ARI1 42 uses - used for Wide-Mux implementation Total ARI1 483 uses Sequential Cells: SLE 2231 uses DSP Blocks: 20 of 84 (23%) MACC: 20 Mults I/O ports: 3 I/O primitives: 2 INBUF 1 use TRIBUFF 1 use Global Clock Buffers: 7 RAM/ROM usage summary Total Block RAMs (RAM1K18) : 12 of 109 (11%) Total LUTs: 1481 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 432; LUTs = 432; MACC Interface Logic : SLEs = 720; LUTs = 720; Total number of SLEs after P&R: 2231 + 0 + 432 + 720 = 3383; Total number of LUTs after P&R: 1481 + 0 + 432 + 720 = 2633; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 76MB peak: 203MB) Process took 0h:00m:15s realtime, 0h:00m:14s cputime # Sun May 30 18:58:38 2021 ###########################################################]