| Project Settings |
|---|
| Project Name | top_syn | Device Name | synthesis: Microchip SmartFusion2 : M2S090TS |
| Implementation Name | synthesis | Top Module | [auto] |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 10000 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
212 |
83 |
0 |
- |
00m:51s |
- |
30-05-2021
18:58:15 |
| (premap) | Complete |
112 |
22 |
0 |
0m:03s |
0m:03s |
197MB |
30-05-2021
18:58:22 |
| (fpga_mapper) | Complete |
85 |
46 |
0 |
0m:14s |
0m:15s |
203MB |
30-05-2021
18:58:38 |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 30-05-2021
18:58:17 |
| Area Summary |
|---|
| |
| Carry Cells | 483 |
Sequential Cells | 2231 |
| DSP Blocks
(dsp_used) | 20 |
I/O Cells | 2 |
| Global Clock Buffers | 7 |
RAM1K18
(v_ram) | 12 |
| LUTs
(total_luts) | 1481 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| FIR_FILTER_0/CCC_0/GL0 | 100.0 MHz | 140.7 MHz | 2.892 |
| FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 50.0 MHz | NA | NA |
| fft_inpl_slowClock|divider_inferred_clock[2] | 100.0 MHz | 155.1 MHz | 3.554 |
| System | 100.0 MHz | 381.3 MHz | 7.378 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 3 |
| |
|