#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-KUMARJ #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\hdl\DATA_HANDLE_FSM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\hdl\FILTER_CONTROL_FSM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER\CCC_0\FIR_FILTER_CCC_0_FCCC.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER\FABOSC_0\FIR_FILTER_FABOSC_0_OSC.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_MSS\FIR_FILTER_MSS_syn.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_MSS\FIR_FILTER_MSS.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER\FIR_FILTER.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\Coef_Buffer\FIR_FILTER_top_Coef_Buffer_TPSRAM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\FFT_IM_Buffer\FIR_FILTER_top_FFT_IM_Buffer_TPSRAM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\FFT_RE_Buffer\FIR_FILTER_top_FFT_RE_Buffer_TPSRAM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\FIR_IN_Buffer\FIR_FILTER_top_FIR_IN_Buffer_TPSRAM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\FIR_OUT_Buffer\FIR_FILTER_top_FIR_OUT_Buffer_TPSRAM.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFFT_0\rtl\in_place\vlog\core\FIR_FILTER_top_COREFFT_0_ram_smGen.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\COREFFT\6.4.105\rtl\in_place\vlog\core\kit.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFFT_0\twiddle32.v" @N:CG347 : twiddle32.v(35) | Read parallel_case directive @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\COREFFT\6.4.105\rtl\in_place\vlog\core\mac_lib.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\COREFFT\6.4.105\rtl\in_place\vlog\core\cmplx.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\COREFFT\6.4.105\rtl\in_place\vlog\core\fftSm.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac_lib.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v" @I:"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\coef_store.v":"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\FIR_FILTER_top_COREFIR_0_coef.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_COREFIR.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\COREFIR_0\rtl\vlog\core\top\COREFIR.v" @I::"E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\component\work\FIR_FILTER_top\FIR_FILTER_top.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module FIR_FILTER_top @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : FIR_FILTER_top_Coef_Buffer_TPSRAM.v(5) | Synthesizing module FIR_FILTER_top_Coef_Buffer_TPSRAM @W:CG775 : COREFFT_TOP.v(25) | Found Component FIR_FILTER_top_COREFFT_0_COREFFT in library COREFFT_LIB @N:CG364 : COREFFT_TOP.v(25) | Synthesizing module FIR_FILTER_top_COREFFT_0_COREFFT FPGA_FAMILY=32'b00000000000000000000000000010011 URAM_MAXDEPTH=32'b00000000000000000000000000000000 CFG_ARCH=32'b00000000000000000000000000000001 DATA_BITS=32'b00000000000000000000000000010010 TWID_BITS=32'b00000000000000000000000000010010 FFT_SIZE=32'b00000000000000000000000100000000 SCALE_ON=32'b00000000000000000000000000000001 SCALE_SCH=32'b00000000000000000000000011111111 ORDER=32'b00000000000000000000000000000000 INVERSE=32'b00000000000000000000000000000000 SCALE=32'b00000000000000000000000000000000 POINTS=32'b00000000000000000000000100000000 WIDTH=32'b00000000000000000000000000010000 MEMBUF=32'b00000000000000000000000000000001 SCALE_EXP_ON=32'b00000000000000000000000000000000 DIE_SIZE=32'b00000000000000000000000000011001 DOWNSCALE=32'b00000000000000000000000011111111 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 FLOGLOGPTS=32'b00000000000000000000000000000100 Generated name = FIR_FILTER_top_COREFFT_0_COREFFT_Z1 @N:CG364 : kit.v(445) | Synthesizing module fft_inpl_slowClock @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_bit_reg_2s @W:CG133 : kit.v(194) | No assignment to delayLine_2_ @N:CG364 : kit.v(29) | Synthesizing module fft_inpl_kitEdge FRONT_EDGE=32'b00000000000000000000000000000000 Generated name = fft_inpl_kitEdge_0s @N:CG364 : kit.v(126) | Synthesizing module fft_inpl_counter_w WIDTH=32'b00000000000000000000000000001010 TC=32'b00000000000000000000000010001001 Generated name = fft_inpl_counter_w_10_137s @N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter WIDTH=32'b00000000000000000000000000000101 TC=32'b00000000000000000000000000000111 Generated name = fft_inpl_counter_5_7 @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000011 Generated name = fft_inpl_kitDelay_bit_reg_3s @W:CG133 : kit.v(194) | No assignment to delayLine_3_ @N:CG364 : fftSm.v(361) | Synthesizing module fft_inpl_rdFFTtimer HALFPTS=32'b00000000000000000000000010000000 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_rdFFTtimer_128s_8_3_10s_1s @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000001010 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_10_2s @W:CG133 : kit.v(235) | No assignment to delayLine_2_ @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000000101 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_5_2s @W:CG133 : kit.v(235) | No assignment to delayLine_2_ @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitDelay_bit_reg_1s @W:CG133 : kit.v(194) | No assignment to delayLine_1_ @N:CG364 : kit.v(99) | Synthesizing module fft_inpl_kitCountS WIDTH=32'b00000000000000000000000000000111 DCVALUE=32'b00000000000000000000000001111111 BUILD_DC=32'b00000000000000000000000000000000 Generated name = fft_inpl_kitCountS_7_127s_0s @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000000111 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_7_2s @W:CG133 : kit.v(235) | No assignment to delayLine_2_ @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000000001 DELAY=32'b00000000000000000000000000001010 Generated name = fft_inpl_kitDelay_reg_1s_10s @W:CG133 : kit.v(235) | No assignment to delayLine_10_ @N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter WIDTH=32'b00000000000000000000000000001000 TC=32'b00000000000000000000000011111111 Generated name = fft_inpl_counter_8_255s @N:CG364 : fftSm.v(481) | Synthesizing module fft_inpl_inBuf_ldA PTS=32'b00000000000000000000000100000000 LOGPTS=32'b00000000000000000000000000001000 Generated name = fft_inpl_inBuf_ldA_256s_8 @W:CG360 : fftSm.v(502) | No assignment to wire load_over @N:CG364 : fftSm.v(623) | Synthesizing module fft_inpl_inBuf_fftA_pipe LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_inBuf_fftA_pipe_8_3 @W:CL265 : fftSm.v(675) | Pruning bit 6 of mask1_r[6:0] -- not in use ... @N:CG364 : fftSm.v(695) | Synthesizing module fft_inpl_twid_rA LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_twid_rA_8_3 @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000100 Generated name = fft_inpl_kitDelay_bit_reg_4s @W:CG133 : kit.v(194) | No assignment to delayLine_4_ @N:CG364 : kit.v(405) | Synthesizing module fft_inpl_kitSync_ngrst PULSE_WIDTH=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitSync_ngrst_1s @W:CG133 : kit.v(412) | No assignment to tick2 @N:CG364 : kit.v(161) | Synthesizing module fft_inpl_bcounter WIDTH=32'b00000000000000000000000000000111 Generated name = fft_inpl_bcounter_7 @N:CG364 : fftSm.v(739) | Synthesizing module fft_inpl_twid_wA_gen LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_twid_wA_gen_8_3 @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000000011 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_3_2s @W:CG133 : kit.v(235) | No assignment to delayLine_2_ @N:CG364 : fftSm.v(532) | Synthesizing module fft_inpl_outBufA PTS=32'b00000000000000000000000100000000 LOGPTS=32'b00000000000000000000000000001000 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_outBufA_256s_8_1s @N:CG364 : fftSm.v(29) | Synthesizing module fft_inpl_sm_top PTS=32'b00000000000000000000000100000000 HALFPTS=32'b00000000000000000000000010000000 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_sm_top_256s_128s_8_3_10s_1s @W:CL168 : fftSm.v(234) | Pruning instance wStage_dly_2 -- not in use ... @W:CL168 : fftSm.v(118) | Pruning instance edge_detect_0 -- not in use ... @N:CG364 : fftDp.v(216) | Synthesizing module FIR_FILTER_top_COREFFT_0_inPlace LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = FIR_FILTER_top_COREFFT_0_inPlace_8_32s_1s_0s_19s @N:CG364 : fftDp.v(130) | Synthesizing module FIR_FILTER_top_COREFFT_0_inBuffer LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = FIR_FILTER_top_COREFFT_0_inBuffer_8_32s_1s_0s_19s @N:CG364 : fftDp.v(36) | Synthesizing module FIR_FILTER_top_COREFFT_0_wrapRam LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 FPGA_FAMILY=32'b00000000000000000000000000010011 URAM_MAXDEPTH=32'b00000000000000000000000000000000 RAM_DEPTH=32'b00000000000000000000000010000000 SMARTGEN=32'b00000000000000000000000000000001 Generated name = FIR_FILTER_top_COREFFT_0_wrapRam_8_32s_19s_0s_128s_1s @N:CG364 : FIR_FILTER_top_COREFFT_0_ram_smGen.v(5) | Synthesizing module FIR_FILTER_top_COREFFT_0_ram_smGen @W:CG133 : fftDp.v(234) | No assignment to wA_bfly_r @W:CG133 : fftDp.v(235) | No assignment to wA_load_r @W:CG133 : fftDp.v(237) | No assignment to wEn_bfly_r @W:CG133 : fftDp.v(237) | No assignment to wEn_odd_r @W:CG133 : fftDp.v(237) | No assignment to wEn_even_r @N:CG364 : kit.v(460) | Synthesizing module fft_inpl_switch DWIDTH=32'b00000000000000000000000000100000 Generated name = fft_inpl_switch_32s @N:CG364 : kit.v(326) | Synthesizing module fft_inpl_kitRndUp WIDTH_OUT=32'b00000000000000000000000000010000 RND_MODE=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitRndUp_16s_1s @N:CG364 : cmplx.v(442) | Synthesizing module fft_inpl_cmplx_rnd WIDTH=32'b00000000000000000000000000010000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 RND=32'b00000000000000000000000000000001 P_WIDTH=32'b00000000000000000000000000101100 Generated name = fft_inpl_cmplx_rnd_16s_0s_19s_1s_44s @N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt INWIDTH=32'b00000000000000000000000000010000 OUTWIDTH=32'b00000000000000000000000000010010 UNSIGNED=32'b00000000000000000000000000000000 Generated name = fft_inpl_signExt_16s_18s_0s @N:CG364 : mac_lib.v(36) | Synthesizing module fft_inpl_mac18x18mx WIDTH_A=32'b00000000000000000000000000010000 WIDTH_B=32'b00000000000000000000000000010000 BYPASS_REG_A=32'b00000000000000000000000000000000 BYPASS_REG_B=32'b00000000000000000000000000000000 BYPASS_REG_P=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 BY_REGA=2'b00 BY_REGB=2'b00 BY_REGP=2'b00 P_WIDTH=32'b00000000000000000000000000101100 Generated name = fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_19s_0_0_0_44s @N:CG364 : smartfusion2.v(567) | Synthesizing module MACC @N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt INWIDTH=32'b00000000000000000000000000101100 OUTWIDTH=32'b00000000000000000000000000100001 UNSIGNED=32'b00000000000000000000000000000000 Generated name = fft_inpl_signExt_44s_33s_0s @N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 WIDTH=32'b00000000000000000000000000010000 MINUS=32'b00000000000000000000000000000001 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 P_WIDTH=32'b00000000000000000000000000101100 SUB=1'b1 DBG=32'b00000000000000000000000000000000 Generated name = fft_inpl_half_cmplx_18_16s_1s_0s_19s_44s_1_0s @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitDelay_reg_16s_1s @W:CG133 : kit.v(235) | No assignment to delayLine_1_ @N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 WIDTH=32'b00000000000000000000000000010000 MINUS=32'b00000000000000000000000000000000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 P_WIDTH=32'b00000000000000000000000000101100 SUB=1'b0 DBG=32'b00000000000000000000000000000000 Generated name = fft_inpl_half_cmplx_18_16s_0s_0s_19s_44s_0_0s @N:CG364 : cmplx.v(414) | Synthesizing module fft_inpl_cmplx_18 WIDTH=32'b00000000000000000000000000010000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 P_WIDTH=32'b00000000000000000000000000101100 Generated name = fft_inpl_cmplx_18_16s_0s_19s_44s @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000100 Generated name = fft_inpl_kitDelay_reg_16s_4s @W:CG133 : kit.v(235) | No assignment to delayLine_4_ @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg BITWIDTH=32'b00000000000000000000000000000010 DELAY=32'b00000000000000000000000000000101 Generated name = fft_inpl_kitDelay_reg_2s_5s @W:CG133 : kit.v(235) | No assignment to delayLine_5_ @N:CG364 : kit.v(499) | Synthesizing module fft_inpl_bfly2 WIDTH=32'b00000000000000000000000000010000 TWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 TDWIDTH=32'b00000000000000000000000000100000 MPIPE=32'b00000000000000000000000000000011 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = fft_inpl_bfly2_16s_16s_32s_32s_3s_19s @N:CG364 : twiddle32.v(27) | Synthesizing module FIR_FILTER_top_COREFFT_0_twiddle TDWIDTH=32'b00000000000000000000000000100000 LOGPTS=32'b00000000000000000000000000001000 Generated name = FIR_FILTER_top_COREFFT_0_twiddle_32s_8 @N:CG364 : fftDp.v(336) | Synthesizing module FIR_FILTER_top_COREFFT_0_twidLUT LOGPTS=32'b00000000000000000000000000001000 TDWIDTH=32'b00000000000000000000000000100000 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = FIR_FILTER_top_COREFFT_0_twidLUT_8_32s_0s_19s @N:CG364 : kit.v(570) | Synthesizing module fft_inpl_autoScale SCALE_MODE=32'b00000000000000000000000000000000 SCALE_EXP_ON=32'b00000000000000000000000000000000 LOGLOGPTS=32'b00000000000000000000000000000100 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_autoScale_0s_0s_4_1s @W:CG133 : kit.v(590) | No assignment to scale_exp_r @W:CG133 : kit.v(590) | No assignment to scale_exp_count @N:CG364 : COREFFT.v(28) | Synthesizing module FIR_FILTER_top_COREFFT_0_COREFFT_INPLC INVERSE=32'b00000000000000000000000000000000 SCALE=32'b00000000000000000000000000000000 POINTS=32'b00000000000000000000000100000000 WIDTH=32'b00000000000000000000000000010000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 SCALE_EXP_ON=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 FLOGLOGPTS=32'b00000000000000000000000000000100 DWIDTH=32'b00000000000000000000000000100000 TWIDTH=32'b00000000000000000000000000010000 TDWIDTH=32'b00000000000000000000000000100000 HALFPTS=32'b00000000000000000000000010000000 MPIPE=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 Generated name = FIR_FILTER_top_COREFFT_0_COREFFT_INPLC_Z2 @N:CG364 : fftDp.v(296) | Synthesizing module FIR_FILTER_top_COREFFT_0_outBuff LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 URAM_MAXDEPTH=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000010011 Generated name = FIR_FILTER_top_COREFFT_0_outBuff_8_32s_0s_19s @W:CG360 : COREFFT.v(86) | No assignment to wire outPQ @W:CG360 : COREFFT.v(87) | No assignment to wire ctrl_outp @W:CG775 : COREFIR.v(28) | Found Component FIR_FILTER_top_COREFIR_0_COREFIR in library COREFIR_LIB @N:CG364 : COREFIR.v(28) | Synthesizing module FIR_FILTER_top_COREFIR_0_COREFIR CFG_ARCH=32'b00000000000000000000000000000001 COEF_SYMM=32'b00000000000000000000000000000001 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_UNSIGN=32'b00000000000000000000000000000000 SYSTOLIC=32'b00000000000000000000000000000000 INP_REG=32'b00000000000000000000000000000001 TAPS=32'b00000000000000000000000000011111 COEF_TYPE=32'b00000000000000000000000000000001 COEF_SETS=32'b00000000000000000000000000000001 COEF_WIDTH=32'b00000000000000000000000000010000 DATA_WIDTH=32'b00000000000000000000000000010000 COEF_RAM=32'b00000000000000000000000000000000 DATA_RAM=32'b00000000000000000000000000000000 SAMPLEID=32'b00000000000000000000000000000000 ID_WIDTH=32'b00000000000000000000000000001100 SAMPLE_RATE=32'b00000000000011110100001001000000 L=32'b00000000000000000000000000000010 M=32'b00000000000000000000000000000010 CLOCK_RATE=32'b00000000100110001001011010000000 FPGA_FAMILY=32'b00000000000000000000000000010011 DIE_SIZE=32'b00000000000000000000000000011001 URAM_MAXDEPTH=32'b00000000000000000000000000000000 PERFORMANCE=32'b00000000000000000000000000000000 RADIX=32'b00000000000000000000000000001010 FPGA_FAMILYI=32'b00000000000000000000000000010011 clk_sample_rate=32'b00000000000000000000000000001010 FLOOR_PHY=32'b00000000000000000000000000000011 PHY_TAPS_FOLD=32'b00000000000000000000000000000100 PHY_TAPS_INTP=32'b00000000000000000000000000001111 Generated name = FIR_FILTER_top_COREFIR_0_COREFIR_Z3 @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000010 Generated name = enum_kitDelay_reg_16s_2s @W:CG133 : kit.v(81) | No assignment to delayLine_2_ @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg BITWIDTH=32'b00000000000000000000000000000100 DELAY=32'b00000000000000000000000000000010 Generated name = enum_kitDelay_reg_4s_2s @W:CG133 : kit.v(81) | No assignment to delayLine_2_ @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000010 Generated name = enum_kitDelay_bit_reg_2s @W:CG133 : kit.v(46) | No assignment to delayLine_2_ @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000100 Generated name = enum_kitDelay_bit_reg_4s @W:CG133 : kit.v(46) | No assignment to delayLine_4_ @N:CG364 : kit.v(185) | Synthesizing module enum_kitSync_ngrst PULSE_WIDTH=32'b00000000000000000000000000000001 Generated name = enum_kitSync_ngrst_1s @W:CG133 : kit.v(192) | No assignment to tick2 @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000011 Generated name = enum_kitDelay_bit_reg_3s @W:CG133 : kit.v(46) | No assignment to delayLine_3_ @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg DELAY=32'b00000000000000000000000000101101 Generated name = enum_kitDelay_bit_reg_45 @W:CG133 : kit.v(46) | No assignment to delayLine_45_ @N:CG364 : coef_store.v(54) | Synthesizing module FIR_FILTER_top_COREFIR_0_wide_coef TAPS=32'b00000000000000000000000000010000 COEF_BITS=32'b00000000000000000000000000010000 COEF_SETS=32'b00000000000000000000000000000001 COEF_TYPE=32'b00000000000000000000000000000001 Generated name = FIR_FILTER_top_COREFIR_0_wide_coef_16s_16s_1s_1s @N:CG364 : kit.v(142) | Synthesizing module enum_coef_sr TAPS=32'b00000000000000000000000000010000 COEF_WIDTH=32'b00000000000000000000000000010000 Generated name = enum_coef_sr_16s_16s @N:CG364 : enum_fir.v(27) | Synthesizing module FIR_FILTER_top_COREFIR_0_fir_enum_g4 TAPS=32'b00000000000000000000000000011111 COEF_TYPE=32'b00000000000000000000000000000001 COEF_SETS=32'b00000000000000000000000000000001 COEF_SYMM=32'b00000000000000000000000000000001 COEF_BITS=32'b00000000000000000000000000010000 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_BITS=32'b00000000000000000000000000010000 DATA_UNSIGN=32'b00000000000000000000000000000000 ACC_WIDTH=32'b00000000000000000000000000101100 SYSTOLIC=32'b00000000000000000000000000000000 VALID_O=32'b00000000000000000000000000000001 COLUMN=32'b00000000000000000000000000011100 XREG_COEF=32'b00000000000000000000000000000100 PERFORMANCE=32'b00000000000000000000000000000000 TAPS_PHY=32'b00000000000000000000000000001111 ODD_SYMM=32'b00000000000000000000000000000001 LATENCY1=32'b00000000000000000000000000000011 SYST=32'b00000000000000000000000000000001 XREGS=32'b00000000000000000000000000000000 LATENC2=32'b00000000000000000000000000011110 LATENC3=32'b00000000000000000000000000101101 LATENCY=32'b00000000000000000000000000101101 MAXDLY=32'b00000000000000000000000000011110 Generated name = FIR_FILTER_top_COREFIR_0_fir_enum_g4_Z4 @N:CG364 : kit.v(116) | Synthesizing module enum_signExt INWIDTH=32'b00000000000000000000000000010000 OUTWIDTH=32'b00000000000000000000000000010010 UNSIGNED=32'b00000000000000000000000000000000 Generated name = enum_signExt_16s_18s_0s @N:CG364 : mac.v(64) | Synthesizing module FIR_FILTER_top_COREFIR_0_mac_enum_g4 ACC_WIDTH=32'b00000000000000000000000000101100 CHAIN_BREAK=32'b00000000000000000000000000000000 XREG_COEF=32'b00000000000000000000000000000100 EXTEND=32'b00000000000000000000000000000000 EXT_WIDTH=32'b00000000000000000000000000000001 Generated name = FIR_FILTER_top_COREFIR_0_mac_enum_g4_44_0s_4s_0s_1 @N:CG364 : mac_lib.v(33) | Synthesizing module FIR_FILTER_top_COREFIR_0_mac18x18_enum_g4 @N:CG364 : mac.v(31) | Synthesizing module FIR_FILTER_top_COREFIR_0_add2_g4 @W:CG360 : mac.v(90) | No assignment to wire cdout_ext @W:CG360 : mac.v(90) | No assignment to wire cdin_ext @W:CG360 : mac.v(91) | No assignment to wire pre_pout @W:CG360 : mac.v(92) | No assignment to wire dumb @N:CG364 : mac.v(138) | Synthesizing module FIR_FILTER_top_COREFIR_0_tap_enum_g4 COEF_SYMM=32'b00000000000000000000000000000001 COEF_BITS=32'b00000000000000000000000000010000 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_BITS=32'b00000000000000000000000000010000 DATA_UNSIGN=32'b00000000000000000000000000000000 ACC_WIDTH=32'b00000000000000000000000000101100 CHAIN_BREAK=32'b00000000000000000000000000000000 XREG_COEF=32'b00000000000000000000000000000100 Generated name = FIR_FILTER_top_COREFIR_0_tap_enum_g4_1s_16s_0s_16s_0s_44_0s_4s @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg BITWIDTH=32'b00000000000000000000000000010010 DELAY=32'b00000000000000000000000000000001 Generated name = enum_kitDelay_reg_18s_1s @W:CG133 : kit.v(81) | No assignment to delayLine_1_ @N:CG364 : kit.v(38) | Synthesizing module enum_kitDelay_bit_reg DELAY=32'b00000000000000000000000000000001 Generated name = enum_kitDelay_bit_reg_1s @W:CG133 : kit.v(46) | No assignment to delayLine_1_ @W:CG360 : mac.v(168) | No assignment to wire coef_val @N:CG364 : kit.v(72) | Synthesizing module enum_kitDelay_reg BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000001 Generated name = enum_kitDelay_reg_16s_1s @W:CG133 : kit.v(81) | No assignment to delayLine_1_ @N:CG364 : mac.v(241) | Synthesizing module FIR_FILTER_top_COREFIR_0_odd_symmetry_tap_enum_g4 COEF_BITS=32'b00000000000000000000000000010000 COEF_UNSIGN=32'b00000000000000000000000000000000 DATA_BITS=32'b00000000000000000000000000010000 DATA_UNSIGN=32'b00000000000000000000000000000000 ACC_WIDTH=32'b00000000000000000000000000101100 XREG_COEF=32'b00000000000000000000000000000100 Generated name = FIR_FILTER_top_COREFIR_0_odd_symmetry_tap_enum_g4_16s_0s_16s_0s_44_4s @W:CG360 : mac.v(266) | No assignment to wire coef_val @W:CG133 : enum_fir.v(96) | No assignment to short_dly_line_-1_ @W:CG133 : enum_fir.v(96) | No assignment to short_dly_line_0_ @W:CG133 : enum_fir.v(108) | No assignment to filled @W:CG133 : enum_fir.v(110) | No assignment to add_valid_tick @W:CG133 : enum_fir.v(110) | No assignment to add_valid_tick2 @N:CG364 : enum_COREFIR.v(47) | Synthesizing module FIR_FILTER_top_COREFIR_0_COREENUMFIR_G4 TAPS=32'b00000000000000000000000000011111 COEF_TYPE=32'b00000000000000000000000000000001 COEF_SETS=32'b00000000000000000000000000000001 COEF_SYMM=32'b00000000000000000000000000000001 COEF_WIDTH=32'b00000000000000000000000000010000 COEF_SIGN=32'b00000000000000000000000000000000 DATA_WIDTH=32'b00000000000000000000000000010000 DATA_SIGN=32'b00000000000000000000000000000000 SYSTOLIC=32'b00000000000000000000000000000000 VALID_O=32'b00000000000000000000000000000001 INP_REG=32'b00000000000000000000000000000001 CASCADE=32'b00000000000000000000000000011100 PERFORMANCE=32'b00000000000000000000000000000000 OUT_WIDTH=32'b00000000000000000000000000100101 HW_WIDTH1=32'b00000000000000000000000000100101 HW_WIDTH=32'b00000000000000000000000000100101 ACC_WIDTH=32'b00000000000000000000000000101100 XREG_COEF=32'b00000000000000000000000000000100 WRAP_LAYERS=32'b00000000000000000000000000000010 Generated name = FIR_FILTER_top_COREFIR_0_COREENUMFIR_G4_Z5 @N:CG364 : DATA_HANDLE_FSM.v(24) | Synthesizing module DATAHANDLE_FSM DATA_WIDTH=32'b00000000000000000000000000010000 ADDR_WIDTH=32'b00000000000000000000000000010000 Generated name = DATAHANDLE_FSM_16s_16s @W:CG296 : DATA_HANDLE_FSM.v(109) | Incomplete sensitivity list - assuming completeness @W:CG290 : DATA_HANDLE_FSM.v(111) | Referenced variable FIR_ENABLE is not in sensitivity list @W:CG290 : DATA_HANDLE_FSM.v(119) | Referenced variable FFT_RE_DATA is not in sensitivity list @W:CG290 : DATA_HANDLE_FSM.v(114) | Referenced variable FIR_DATA_OUT is not in sensitivity list @W:CG290 : DATA_HANDLE_FSM.v(124) | Referenced variable FFT_IM_DATA is not in sensitivity list @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal PRDATA[15:0]; possible missing assignment in an if or case statement. @A:CL282 : DATA_HANDLE_FSM.v(128) | Feedback mux created for signal COEF_WR_EN -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal FIR_RADDR[9:0]; possible missing assignment in an if or case statement. @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal FFT_RE_RADDR[9:0]; possible missing assignment in an if or case statement. @W:CL118 : DATA_HANDLE_FSM.v(111) | Latch generated from always block for signal FFT_IM_RADDR[9:0]; possible missing assignment in an if or case statement. @W:CL190 : DATA_HANDLE_FSM.v(128) | Optimizing register bit PREADY to a constant 1 @W:CL169 : DATA_HANDLE_FSM.v(128) | Pruning register PREADY @N:CG364 : FIR_FILTER_top_FFT_IM_Buffer_TPSRAM.v(5) | Synthesizing module FIR_FILTER_top_FFT_IM_Buffer_TPSRAM @N:CG364 : FIR_FILTER_top_FFT_RE_Buffer_TPSRAM.v(5) | Synthesizing module FIR_FILTER_top_FFT_RE_Buffer_TPSRAM @N:CG364 : FILTER_CONTROL_FSM.v(22) | Synthesizing module FILTERCONTROL_FSM @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : FIR_FILTER_CCC_0_FCCC.v(5) | Synthesizing module FIR_FILTER_CCC_0_FCCC @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0011 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z6 @W:CG360 : coreapb3.v(244) | No assignment to wire IA_PRDATA @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z7 @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : FIR_FILTER_FABOSC_0_OSC.v(5) | Synthesizing module FIR_FILTER_FABOSC_0_OSC @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : FIR_FILTER_MSS_syn.v(5) | Synthesizing module MSS_075 @N:CG364 : FIR_FILTER_MSS.v(9) | Synthesizing module FIR_FILTER_MSS @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : FIR_FILTER.v(9) | Synthesizing module FIR_FILTER @N:CG364 : FIR_FILTER_top_FIR_IN_Buffer_TPSRAM.v(5) | Synthesizing module FIR_FILTER_top_FIR_IN_Buffer_TPSRAM @N:CG364 : FIR_FILTER_top_FIR_OUT_Buffer_TPSRAM.v(5) | Synthesizing module FIR_FILTER_top_FIR_OUT_Buffer_TPSRAM @N:CG364 : FIR_FILTER_top.v(9) | Synthesizing module FIR_FILTER_top @W:CL157 : FIR_FILTER_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : FIR_FILTER_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : FIR_FILTER_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : FIR_FILTER_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : FIR_FILTER_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused @W:CL159 : coreapb3.v(72) | Input IADDR is unused @W:CL159 : coreapb3.v(73) | Input PRESETN is unused @W:CL159 : coreapb3.v(74) | Input PCLK is unused @W:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(122) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(123) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(124) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(125) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(126) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(127) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(128) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(129) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(130) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(131) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(132) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(133) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(134) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(135) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(136) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused @N:CL201 : FILTER_CONTROL_FSM.v(74) | Trying to extract state machine for register fsm Extracted state machine for register fsm State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @N:CL201 : DATA_HANDLE_FSM.v(128) | Trying to extract state machine for register fsm Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : DATA_HANDLE_FSM.v(60) | Input port bits 15 to 12 of PADDR[15:0] are unused @W:CL246 : DATA_HANDLE_FSM.v(60) | Input port bits 1 to 0 of PADDR[15:0] are unused @W:CL159 : DATA_HANDLE_FSM.v(59) | Input PENABLE is unused @W:CL159 : DATA_HANDLE_FSM.v(58) | Input FILTER_COMPLETE is unused @W:CL159 : mac.v(42) | Input clkEn is unused @W:CL159 : coef_store.v(67) | Input set is unused @N:CL135 : kit.v(55) | Found seqShift genblk1.delayLine, depth=45, width=1 @N:CL135 : kit.v(55) | Found seqShift genblk1.delayLine, depth=3, width=1 @N:CL135 : kit.v(55) | Found seqShift genblk1.delayLine, depth=4, width=1 @W:CL157 : COREFIR.v(96) | *Output DATAO has undriven bits -- simulation mismatch possible. @W:CL159 : COREFIR.v(90) | Input COEF_REF is unused @W:CL159 : COREFIR.v(92) | Input SAMPLE_ID is unused @W:CL159 : COREFIR.v(93) | Input RCLK is unused @A:CL153 : kit.v(590) | *Unassigned bits of scale_exp_r[3:0] are referenced and tied to 0 -- simulation mismatch possible. @W:CL159 : kit.v(584) | Input fftRd_done_tick is unused @W:CL260 : kit.v(560) | Pruning register bit 16 of outQ[31:0] @W:CL246 : kit.v(369) | Input port bits 42 to 32 of inp[43:0] are unused @W:CL159 : fftDp.v(225) | Input load is unused @W:CL159 : fftSm.v(549) | Input rTimerTC_tick is unused @W:CL159 : fftSm.v(493) | Input clkEn is unused @W:CL157 : COREFFT_TOP.v(78) | *Output RFS has undriven bits -- simulation mismatch possible. @W:CL157 : COREFFT_TOP.v(78) | *Output OVFLOW_FLAG has undriven bits -- simulation mismatch possible. @W:CL159 : COREFFT_TOP.v(77) | Input CLKEN is unused @W:CL159 : COREFFT_TOP.v(77) | Input RST is unused @W:CL159 : COREFFT_TOP.v(77) | Input START is unused @W:CL159 : COREFFT_TOP.v(77) | Input INVERSE_STRM is unused @W:CL159 : COREFFT_TOP.v(77) | Input REFRESH is unused At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 85MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 29 16:29:46 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 29 16:29:47 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 29 16:29:47 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File E:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\bin64\syn_nfilter.exe changed - recompiling File E:\FIR_FILTER_DEMO\synthesis\synwork\FIR_FILTER_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 83MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 29 16:29:48 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @L: E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\synthesis\FIR_FILTER_top_scck.rpt Printing clock summary report in "E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\synthesis\FIR_FILTER_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 120MB) @W:BN132 : fftsm.v(675) | Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0], because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0] @W:BN132 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int, because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.FDDR_CORE_RESET_N_int @N:BN362 : fftsm.v(675) | Removing sequential instance swCross of view:PrimLib.dffe(prim) in hierarchy view:COREFFT_LIB.fft_inpl_inBuf_fftA_pipe_8_3_0(verilog) because there are no references to its outputs @N:BN362 : corefft.v(229) | Removing sequential instance buf_ready_r of view:PrimLib.dff(prim) in hierarchy view:COREFFT_LIB.FIR_FILTER_top_COREFFT_0_COREFFT_INPLC_Z2(verilog) because there are no references to its outputs @N:BN362 : kit.v(341) | Removing sequential instance valOutp of view:PrimLib.dffre(prim) in hierarchy view:COREFFT_LIB.fft_inpl_kitRndUp_16s_1s_1(verilog) because there are no references to its outputs @N:BN362 : kit.v(341) | Removing sequential instance valOutp of view:PrimLib.dffre(prim) in hierarchy view:COREFFT_LIB.fft_inpl_kitRndUp_16s_1s_0(verilog) because there are no references to its outputs @N:BN362 : kit.v(478) | Removing sequential instance validOut of view:PrimLib.dff(prim) in hierarchy view:COREFFT_LIB.fft_inpl_switch_32s_0(verilog) because there are no references to its outputs @N:BN362 : kit.v(218) | Removing sequential instance pulse of view:PrimLib.dff(prim) in hierarchy view:COREFIR_LIB.enum_kitSync_ngrst_1s(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : fftsm.v(265) | Removing sequential instance fftRd_done_tick of view:PrimLib.dff(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(478) | Removing sequential instance pipe1 of view:PrimLib.dff(prim) in hierarchy view:COREFFT_LIB.fft_inpl_switch_32s_0(verilog) because there are no references to its outputs @N:BN115 : enum_corefir.v(108) | Removing instance wrap_coef_sel of view:COREFIR_LIB.enum_kitDelay_reg_4s_2s(verilog) because there are no references to its outputs @N:BN362 : filter_control_fsm.v(74) | Removing sequential instance FILTER_COMPLETE of view:PrimLib.dffre(prim) in hierarchy view:work.FILTERCONTROL_FSM(verilog) because there are no references to its outputs @N:BN362 : corefft.v(229) | Removing sequential instance datao_valid_r of view:PrimLib.dff(prim) in hierarchy view:COREFFT_LIB.FIR_FILTER_top_COREFFT_0_COREFFT_INPLC_Z2(verilog) because there are no references to its outputs @N:BN362 : kit.v(90) | Removing sequential instance genblk1\.delayLine_1_[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREFIR_LIB.enum_kitDelay_reg_4s_2s(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : kit.v(200) | Removing sequential instance tick1 of view:PrimLib.dff(prim) in hierarchy view:COREFIR_LIB.enum_kitSync_ngrst_1s(verilog) because there are no references to its outputs @N:BN115 : fftsm.v(582) | Removing instance bit_dly_1 of view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because there are no references to its outputs @N:BN362 : kit.v(90) | Removing sequential instance genblk1\.delayLine_0_[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREFIR_LIB.enum_kitDelay_reg_4s_2s(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine_2_ of view:PrimLib.dffre(prim) in hierarchy view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z7(verilog) because there are no references to its outputs @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine_1_ of view:PrimLib.dffre(prim) in hierarchy view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because there are no references to its outputs @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine_0_ of view:PrimLib.dffre(prim) in hierarchy view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because there are no references to its outputs @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR6 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR5 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR4 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=109 set on top level netlist FIR_FILTER_top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 161MB peak: 164MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group -------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 FIR_FILTER_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 System 100.0 MHz 10.000 system system_clkgroup fft_inpl_slowClock|divider_inferred_clock[2] 100.0 MHz 10.000 inferred Inferred_clkgroup_2 ========================================================================================================================== @W:MT532 : data_handle_fsm.v(111) | Found signal identified as System clock which controls 46 sequential elements including DATAHANDLE_FSM_0.PRDATA[15:0]. Using this clock, which has no specified timing constraint, can adversely impact design performance. @W:MT530 : fir_filter_top_coef_buffer_tpsram.v(31) | Found inferred clock FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock which controls 2291 sequential elements including Coef_Buffer.FIR_FILTER_top_Coef_Buffer_TPSRAM_R0C0. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(912) | Found inferred clock FIR_FILTER_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including FIR_FILTER_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : kit.v(203) | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 16 sequential elements including COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine_3_. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\synthesis\FIR_FILTER_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 92MB peak: 164MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Mon Feb 29 16:29:51 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) @W:MO111 : corefft_top.v(78) | Tristate driver OVFLOW_FLAG on net OVFLOW_FLAG has its enable tied to GND (module FIR_FILTER_top_COREFFT_0_COREFFT_Z1) @W:MO111 : corefft_top.v(78) | Tristate driver RFS on net RFS has its enable tied to GND (module FIR_FILTER_top_COREFFT_0_COREFFT_Z1) @W:MO111 : corefir.v(96) | Tristate driver DATAO_1 on net DATAO_1 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_2 on net DATAO_2 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_3 on net DATAO_3 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_4 on net DATAO_4 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_5 on net DATAO_5 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_6 on net DATAO_6 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_7 on net DATAO_7 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_8 on net DATAO_8 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_9 on net DATAO_9 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_10 on net DATAO_10 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_11 on net DATAO_11 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_12 on net DATAO_12 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_13 on net DATAO_13 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_14 on net DATAO_14 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_15 on net DATAO_15 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_16 on net DATAO_16 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_17 on net DATAO_17 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_18 on net DATAO_18 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_19 on net DATAO_19 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_20 on net DATAO_20 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_21 on net DATAO_21 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_22 on net DATAO_22 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_23 on net DATAO_23 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_24 on net DATAO_24 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_25 on net DATAO_25 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_26 on net DATAO_26 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_27 on net DATAO_27 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_28 on net DATAO_28 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_29 on net DATAO_29 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_30 on net DATAO_30 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_31 on net DATAO_31 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_32 on net DATAO_32 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_33 on net DATAO_33 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_34 on net DATAO_34 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_35 on net DATAO_35 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : corefir.v(96) | Tristate driver DATAO_36 on net DATAO_36 has its enable tied to GND (module FIR_FILTER_top_COREFIR_0_COREFIR_Z3) @W:MO111 : fir_filter_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module FIR_FILTER_FABOSC_0_OSC) @W:MO111 : fir_filter_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module FIR_FILTER_FABOSC_0_OSC) @W:MO111 : fir_filter_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module FIR_FILTER_FABOSC_0_OSC) @W:MO111 : fir_filter_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module FIR_FILTER_FABOSC_0_OSC) @W:MO171 : coreresetp.v(676) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance FIR_FILTER_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance FIR_FILTER_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance FIR_FILTER_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:BN132 : kit.v(244) | Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_1.genblk1.dly_d.genblk1.delayLine_0_[15:0], because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_0.genblk1.dly_d.genblk1.delayLine_0_[15:0] @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[6].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[0].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[7].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[14].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[12].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[3].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[10].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[8].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ @W:BN132 : kit.v(55) | Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[11].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine_0_, because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine_0_ Available hyper_sources - for debug and ip models None Found @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR6 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR5 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR4 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 appears to be an unidentified clock source. Assuming default frequency. Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 149MB) @N: : kit.v(111) | Found counter in view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) inst wTimer_0.Q[6:0] @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_1_[3] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_1_[4] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_1_[7] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_1_[8] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_1_[9] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_0_[3] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine_0_[4] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_0_[7] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_0_[8] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine_0_[9] of view:PrimLib.dffr(prim) in hierarchy view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) because there are no references to its outputs @N: : kit.v(139) | Found counter in view:COREFFT_LIB.fft_inpl_counter_w_10_137s(verilog) inst Q[9:0] @N: : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_5_7(verilog) inst Q[4:0] @N: : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_8_255s(verilog) inst Q[7:0] @N:FX404 : fftsm.v(671) | Found addmux in view:COREFFT_LIB.fft_inpl_inBuf_fftA_pipe_8_3_1(verilog) inst bflyA_w[6:0] from un1_bflyA_w[6:0] @N: : kit.v(168) | Found counter in view:COREFFT_LIB.fft_inpl_twid_wA_gen_8_3(verilog) inst slowTimer.Q[6:0] @N:FX404 : fftsm.v(671) | Found addmux in view:COREFFT_LIB.fft_inpl_inBuf_fftA_pipe_8_3_0(verilog) inst bflyA_w[6:0] from un1_bflyA_w[6:0] Encoding state machine fsm[3:0] (view:work.DATAHANDLE_FSM_16s_16s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : data_handle_fsm.v(128) | No possible illegal states for state machine fsm[3:0],safe FSM implementation is disabled Encoding state machine fsm[4:0] (view:work.FILTERCONTROL_FSM(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N: : filter_control_fsm.v(74) | Found counter in view:work.FILTERCONTROL_FSM(verilog) inst COEF_RADDR[5:0] @N: : filter_control_fsm.v(74) | Found counter in view:work.FILTERCONTROL_FSM(verilog) inst FFT_WADDR[9:0] @N: : filter_control_fsm.v(74) | Found counter in view:work.FILTERCONTROL_FSM(verilog) inst FIR_WR_ADDR[9:0] Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z7(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[3] in hierarchy view:COREFFT_LIB.FIR_FILTER_top_COREFFT_0_COREFFT_INPLC_Z2(verilog) because there are no references to its outputs @N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[4] in hierarchy view:COREFFT_LIB.FIR_FILTER_top_COREFFT_0_COREFFT_INPLC_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 152MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 154MB) @N:BN362 : coreresetp.v(1613) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.ddr_settled in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @A:BN291 : coreresetp.v(1613) | Boundary register FIR_FILTER_0.CORERESETP_0.ddr_settled packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @A:BN291 : coreresetp.v(1646) | Boundary register FIR_FILTER_0.CORERESETP_0.ddr_settled_q1 packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coreresetp.v(963) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(929) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(870) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif0_areset_n_rcosc in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(856) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc_q1 in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FIR_FILTER_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.FIR_FILTER_top(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 154MB) @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�6ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�6ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�0ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�0ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�7ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�7ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�14ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�14ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�12ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�12ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�3ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�3ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�10ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�10ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�8ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�8ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�11ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�11ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�5ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�5ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�9ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�9ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�1ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�1ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�2ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�2ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�13ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�13ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] @W:FX665 : kit.v(90) | Removing instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�4ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[17] because it is equivalent to instance COREFIR_0.enum_g4�enum_fir_g4.fir_enum_g4_0.taps�tap�4ݮa_tap.symm_tap�pipe_reg_0.genblk1�delayLine_0_[16] Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 153MB peak: 154MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 154MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 154MB) @N:MO106 : twiddle32.v(35) | Found ROM, 'COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1[31:0]', 128 words by 32 bits Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 153MB peak: 157MB) Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 164MB peak: 166MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s 1.16ns 1574 / 2184 @N:FP130 : | Promoting Net FIR_FILTER_0_MSS_READY on CLKINT I_241 @N:FP130 : | Promoting Net COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider_i_1[2] on CLKINT I_242 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 166MB peak: 169MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 171MB peak: 171MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 2246 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 63 clock pin(s) of sequential element(s) 0 instances converted, 63 sequential instances remain driven by gated/generated clocks ================================================ Non-Gated/Non-Generated Clocks ================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------------------------------- ClockId0003 FIR_FILTER_0.CCC_0.GL0_INST CLKINT 2246 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST ================================================================================================================================ ====================================================================================================== Gated/Generated Clocks ======================================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 COREFFT_0.genblk1.DUT_INPLACE.slowClock_0.divider[2] SLE 17 COREFFT_0.genblk1.DUT_INPLACE.sm_0.twid_wA_0.preRstAfterInit No gated clock conversion method for cell cell:ACG4.SLE ClockId0002 DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 CFG2 46 DATAHANDLE_FSM_0.PRDATA[10] No gated clock conversion method for cell cell:ACG4.SLE ===================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 131MB peak: 172MB) Writing Analyst data base E:\Libero_11p7_updates\downloaded\SF2_Eval_FIR_FILTER_DEMO_DF\Design files\FIR_FILTER_DEMO\synthesis\synwork\FIR_FILTER_top_m.srm @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR4 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR6 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR5 appears to be an unidentified clock source. Assuming default frequency. Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 168MB peak: 172MB) Writing EDIF Netlist and constraint files @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR4 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR6 appears to be an unidentified clock source. Assuming default frequency. @W:MT462 : data_handle_fsm.v(111) | Net DATAHANDLE_FSM_0.FIR_RADDR5 appears to be an unidentified clock source. Assuming default frequency. @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 169MB peak: 174MB) Start final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 168MB peak: 174MB) @W:MT246 : fir_filter_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock FIR_FILTER_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FIR_FILTER_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FIR_FILTER_0.CCC_0.GL0_net" @W:MT420 : | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] with period 10.00ns. Please declare a user-defined clock on object "n:COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2]" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Mon Feb 29 16:29:59 2016 # Top view: FIR_FILTER_top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.953 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 124.3 MHz 10.000 8.047 1.953 inferred Inferred_clkgroup_0 FIR_FILTER_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 fft_inpl_slowClock|divider_inferred_clock[2] 100.0 MHz 160.8 MHz 10.000 6.217 3.783 inferred Inferred_clkgroup_2 System 100.0 MHz 331.8 MHz 10.000 3.014 6.986 system system_clkgroup ================================================================================================================================================================ @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 6.986 | No paths - | No paths - | No paths - FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock System | 10.000 4.692 | No paths - | No paths - | No paths - FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 1.953 | No paths - | No paths - | No paths - fft_inpl_slowClock|divider_inferred_clock[2] FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock | No paths - | No paths - | No paths - | Diff grp - fft_inpl_slowClock|divider_inferred_clock[2] fft_inpl_slowClock|divider_inferred_clock[2] | No paths - | 10.000 3.783 | No paths - | No paths - ================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[12] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[12] 3.046 1.953 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[15] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[15] 3.056 1.981 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_SEL FIR_FILTER_MSS_TMP_0_FIC_0_APB_MASTER_PSELx 3.083 2.592 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[13] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[13] 3.017 2.716 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[14] FIR_FILTER_0_AMBA_SLAVE_0_PADDR[14] 3.012 2.758 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[11] DATAHANDLE_FSM_0_FIR_WADDR[9] 3.035 3.795 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[9] DATAHANDLE_FSM_0_FIR_WADDR[7] 3.042 3.856 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[7] DATAHANDLE_FSM_0_FIR_WADDR[5] 3.033 3.863 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[6] DATAHANDLE_FSM_0_FIR_WADDR[4] 3.131 3.873 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[5] DATAHANDLE_FSM_0_FIR_WADDR[3] 3.021 3.915 ================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[2] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] 8.703 1.953 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[13] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[13] 8.893 2.143 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[15] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[15] 8.910 2.160 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[14] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[14] 8.933 2.183 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[9] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[9] 8.966 2.216 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[1] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[1] 8.985 2.235 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[7] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[7] 9.000 2.250 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[8] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[8] 9.005 2.255 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[12] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[12] 9.009 2.259 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_RDATA[4] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[4] 9.010 2.260 =============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.297 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.703 - Propagation time: 6.750 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.953 Number of logic level(s): 3 Starting point: FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[12] Ending point: FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[12] Out 3.046 3.046 - FIR_FILTER_0_AMBA_SLAVE_0_PADDR[12] Net - - 0.971 - 1 FIR_FILTER_0.CoreAPB3_0.iPSELS_1[0] CFG2 B In - 4.017 - FIR_FILTER_0.CoreAPB3_0.iPSELS_1[0] CFG2 Y Out 0.125 4.142 - iPSELS_1[0] Net - - 0.483 - 1 FIR_FILTER_0.CoreAPB3_0.iPSELS[0] CFG4 D In - 4.625 - FIR_FILTER_0.CoreAPB3_0.iPSELS[0] CFG4 Y Out 0.250 4.875 - FIR_FILTER_0_AMBA_SLAVE_0_PSELx Net - - 0.827 - 19 DATAHANDLE_FSM_0.PRDATA_RNILJOB[2] CFG2 A In - 5.703 - DATAHANDLE_FSM_0.PRDATA_RNILJOB[2] CFG2 Y Out 0.076 5.778 - FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] Net - - 0.971 - 1 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 6.750 - ======================================================================================================================== Total path delay (propagation time + setup) of 8.047 is 4.793(59.6%) logic and 3.253(40.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: fft_inpl_slowClock|divider_inferred_clock[2] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[2] 0.094 3.783 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[1] 0.094 3.843 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[0] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[0] 0.094 4.175 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[3] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[3] 0.094 4.522 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[4] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[4] 0.094 5.142 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[5] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[5] 0.094 5.995 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.pulse fft_inpl_slowClock|divider_inferred_clock[2] SLE Q pulse_rst 0.094 7.220 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[6] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[6] 0.094 7.344 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.twid_wEn fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wEn_w 0.094 8.363 COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine_3_ fft_inpl_slowClock|divider_inferred_clock[2] SLE Q synced_ngrst 0.076 8.811 ===================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[4] twidData_w[4] 9.708 3.783 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[9] twidData_w[8] 9.708 4.110 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[5] twidData_w[5] 9.708 4.175 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[6] twidData_w[6] 9.708 4.189 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[10] twidData_w[9] 9.708 4.203 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[7] twidData_w[7] 9.708 4.247 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[12] twidData_w[11] 9.708 4.274 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[3] N_110_i 9.719 4.321 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[13] twidData_w[12] 9.708 4.322 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM1K18 B_DIN[11] twidData_w[10] 9.708 4.352 ======================================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.292 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.708 - Propagation time: 5.925 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.783 Number of logic level(s): 6 Starting point: COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] / Q Ending point: COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 / B_DIN[4] The start point is clocked by fft_inpl_slowClock|divider_inferred_clock[2] [falling] on pin CLK The end point is clocked by fft_inpl_slowClock|divider_inferred_clock[2] [falling] on pin B_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] SLE Q Out 0.094 0.094 - twid_wA_w[2] Net - - 1.209 - 87 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m7 CFG2 B In - 1.303 - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m7 CFG2 Y Out 0.143 1.446 - m7 Net - - 0.761 - 12 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m123 CFG2 A In - 2.207 - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m123 CFG2 Y Out 0.076 2.282 - m123 Net - - 0.548 - 2 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m125_ns_1 CFG4 C In - 2.830 - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m125_ns_1 CFG4 Y Out 0.194 3.024 - m125_ns_1 Net - - 0.483 - 1 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m125_ns CFG4 B In - 3.507 - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m125_ns CFG4 Y Out 0.143 3.651 - m125_ns Net - - 0.483 - 1 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m130 CFG3 C In - 4.134 - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m130 CFG3 Y Out 0.196 4.330 - m130 Net - - 0.548 - 2 COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m131 CFG3 A In - 4.878 - COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_31_0_.m131 CFG3 Y Out 0.076 4.954 - twidData_w[4] Net - - 0.971 - 1 COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.SmFu4_sram\.smGen_RAM_0.FIR_FILTER_top_COREFFT_0_ram_smGen_R0C0 RAM1K18 B_DIN[4] In - 5.925 - ======================================================================================================================================================================================== Total path delay (propagation time + setup) of 6.217 is 1.214(19.5%) logic and 5.003(80.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- DATAHANDLE_FSM_0.PRDATA[2] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[2] 0.094 6.986 DATAHANDLE_FSM_0.PRDATA[13] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[13] 0.094 7.176 DATAHANDLE_FSM_0.PRDATA[15] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[15] 0.094 7.193 DATAHANDLE_FSM_0.PRDATA[14] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[14] 0.094 7.216 DATAHANDLE_FSM_0.PRDATA[9] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[9] 0.094 7.249 DATAHANDLE_FSM_0.PRDATA[1] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[1] 0.094 7.268 DATAHANDLE_FSM_0.PRDATA[7] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[7] 0.094 7.283 DATAHANDLE_FSM_0.PRDATA[8] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[8] 0.094 7.288 DATAHANDLE_FSM_0.PRDATA[12] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[12] 0.094 7.292 DATAHANDLE_FSM_0.PRDATA[4] System SLE Q FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[4] 0.094 7.293 ========================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------ FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[2] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] 8.703 6.986 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[13] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[13] 8.893 7.176 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[15] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[15] 8.910 7.193 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[14] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[14] 8.933 7.216 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[9] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[9] 8.966 7.249 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[1] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[1] 8.985 7.268 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[7] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[7] 9.000 7.283 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[8] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[8] 9.005 7.288 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[12] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[12] 9.009 7.292 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST System MSS_075 F_HM0_RDATA[4] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[4] 9.010 7.293 ============================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.297 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.703 - Propagation time: 1.717 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 6.986 Number of logic level(s): 1 Starting point: DATAHANDLE_FSM_0.PRDATA[2] / Q Ending point: FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2] The start point is clocked by System [rising] on pin CLK The end point is clocked by FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ DATAHANDLE_FSM_0.PRDATA[2] SLE Q Out 0.094 0.094 - FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[2] Net - - 0.509 - 1 DATAHANDLE_FSM_0.PRDATA_RNILJOB[2] CFG2 B In - 0.603 - DATAHANDLE_FSM_0.PRDATA_RNILJOB[2] CFG2 Y Out 0.143 0.746 - FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[2] Net - - 0.971 - 1 FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_RDATA[2] In - 1.717 - ======================================================================================================================== Total path delay (propagation time + setup) of 3.014 is 1.534(50.9%) logic and 1.480(49.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 168MB peak: 174MB) Finished timing report (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 168MB peak: 174MB) --------------------------------------- Resource Usage Report for FIR_FILTER_top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 3 uses MSS_075 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 7 uses CFG2 176 uses CFG3 679 uses CFG4 189 uses Carry primitives used for arithmetic functions: ARI1 441 uses Sequential Cells: SLE 2230 uses DSP Blocks: 20 MACC: 20 Mults I/O ports: 3 I/O primitives: 2 INBUF 1 use TRIBUFF 1 use Global Clock Buffers: 3 RAM/ROM usage summary Block Rams (RAM1K18) : 12 Total LUTs: 1492 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 432; LUTs = 432; MACC Interface Logic : SLEs = 720; LUTs = 720; Total number of SLEs after P&R: 2230 + 0 + 432 + 720 = 3382; Total number of LUTs after P&R: 1492 + 0 + 432 + 720 = 2644; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 59MB peak: 174MB) Process took 0h:00m:07s realtime, 0h:00m:07s cputime # Mon Feb 29 16:29:59 2016 ###########################################################]