@W: BN544 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":8:0:8:0|create_generated_clock with both -multiply_by and -divide_by not supported for this target technology
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\fftsm.v":675:2:675:7|Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance FIR_FILTER_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance FIR_FILTER_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance FIR_FILTER_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance FIR_FILTER_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
@W: MO129 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance FIR_FILTER_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
@W: MT686 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":8:0:8:0|No path from master pin (-source) to source of clock FIR_FILTER_0/CCC_0/GL0 
@W: MT532 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\hdl\data_handle_fsm.v":111:6:111:7|Found signal identified as System clock which controls 46 sequential elements including DATAHANDLE_FSM_0.PRDATA[15:0].  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W: MT530 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\kit.v":203:6:203:11|Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 17 sequential elements including COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine\[3\]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MF511 |Found issues with constraints. Please check constraint checker report "C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\top_cck.rpt" .
