@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\kit.v":244:6:244:11|Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_1.genblk1.dly_d.genblk1.delayLine[0][15:0] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_0.genblk1.dly_d.genblk1.delayLine[0][15:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[6].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[0].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[7].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[14].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[12].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[3].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[10].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[8].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[11].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[5].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[9].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[1].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[2].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[13].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":55:6:55:11|Removing sequential instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.taps.tap[4].a_tap.symm_tap.symm_add_balance_0.genblk1.delayLine[0] because it is equivalent to instance COREFIR_0.enum_g4.enum_fir_g4.fir_enum_g4_0.odd_tap.last_tap.symm_add_balance_0.genblk1.delayLine[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[6\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[6\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[0\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[0\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[7\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[7\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[14\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[14\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[12\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[12\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[3\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[3\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[10\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[10\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[8\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[8\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[11\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[11\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[5\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[5\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[9\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[9\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[1\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[1\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[2\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[2\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[13\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[13\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefir\8.6.101\rtl\vlog\core\kit.v":90:6:90:11|Removing instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[4\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][17] (in view: work.top(verilog)) because it is equivalent to instance COREFIR_0.enum_g4\.enum_fir_g4.fir_enum_g4_0.taps\.tap\[4\]\.a_tap.symm_tap\.pipe_reg_0.genblk1\.delayLine\[0\][16] (in view: work.top(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\fftsm.v":675:2:675:7|Removing instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.offsetPQ_r1[6] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.mask1_r[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\fftsm.v":675:2:675:7|Removing instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_rA_0.offsetPQ_r1[6] because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_rA_0.mask1_r[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT246 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\dg0438\libero_project\component\work\fir_filter\ccc_0\fir_filter_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] with period 10.00ns. Please declare a user-defined clock on net COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2].
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":9:0:9:0|Timing constraint (through [get_nets { FIR_FILTER_0.CORERESETP_0.ddr_settled FIR_FILTER_0.CORERESETP_0.count_ddr_enable FIR_FILTER_0.CORERESETP_0.release_sdif*_core FIR_FILTER_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":10:0:10:0|Timing constraint (from [get_cells { FIR_FILTER_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc FIR_FILTER_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":11:0:11:0|Timing constraint (from [get_cells { FIR_FILTER_0.CORERESETP_0.MSS_HPMS_READY_int FIR_FILTER_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { FIR_FILTER_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":12:0:12:0|Timing constraint (through [get_nets { FIR_FILTER_0.CORERESETP_0.CONFIG1_DONE FIR_FILTER_0.CORERESETP_0.CONFIG2_DONE FIR_FILTER_0.CORERESETP_0.SDIF*_PERST_N FIR_FILTER_0.CORERESETP_0.SDIF*_PSEL FIR_FILTER_0.CORERESETP_0.SDIF*_PWRITE FIR_FILTER_0.CORERESETP_0.SDIF*_PRDATA[*] FIR_FILTER_0.CORERESETP_0.SOFT_EXT_RESET_OUT FIR_FILTER_0.CORERESETP_0.SOFT_RESET_F2M FIR_FILTER_0.CORERESETP_0.SOFT_M3_RESET FIR_FILTER_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_FDDR_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET FIR_FILTER_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":13:0:13:0|Timing constraint (through [get_pins { FIR_FILTER_0.FIR_FILTER_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/dg0438/libero_project/designer/top/synthesis.fdc":14:0:14:0|Timing constraint (through [get_pins { FIR_FILTER_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
